[qemu.git] / hw / pl190.c

/*
 * Arm PrimeCell PL190 Vector Interrupt Controller
 *
 * Copyright (c) 2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "sysbus.h"

/* The number of virtual priority levels.  16 user vectors plus the
   unvectored IRQ.  Chained interrupts would require an additional level
   if implemented.  */

#define PL190_NUM_PRIO 17

typedef struct {
    SysBusDevice busdev;
    uint32_t level;
    uint32_t soft_level;
    uint32_t irq_enable;
    uint32_t fiq_select;
    uint8_t vect_control[16];
    uint32_t vect_addr[PL190_NUM_PRIO];
    /* Mask containing interrupts with higher priority than this one.  */
    uint32_t prio_mask[PL190_NUM_PRIO + 1];
    int protected;
    /* Current priority level.  */
    int priority;
    int prev_prio[PL190_NUM_PRIO];
    qemu_irq irq;
    qemu_irq fiq;
} pl190_state;

static const unsigned char pl190_id[] =
{ 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 };

static inline uint32_t pl190_irq_level(pl190_state *s)
{
    return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select;
}

/* Update interrupts.  */
static void pl190_update(pl190_state *s)
{
    uint32_t level = pl190_irq_level(s);
    int set;

    set = (level & s->prio_mask[s->priority]) != 0;
    qemu_set_irq(s->irq, set);
    set = ((s->level | s->soft_level) & s->fiq_select) != 0;
    qemu_set_irq(s->fiq, set);
}

static void pl190_set_irq(void *opaque, int irq, int level)
{
    pl190_state *s = (pl190_state *)opaque;

    if (level)
        s->level |= 1u << irq;
    else
        s->level &= ~(1u << irq);
    pl190_update(s);
}

static void pl190_update_vectors(pl190_state *s)
{
    uint32_t mask;
    int i;
    int n;

    mask = 0;
    for (i = 0; i < 16; i++)
      {
        s->prio_mask[i] = mask;
        if (s->vect_control[i] & 0x20)
          {
            n = s->vect_control[i] & 0x1f;
            mask |= 1 << n;
          }
      }
    s->prio_mask[16] = mask;
    pl190_update(s);
}

static uint32_t pl190_read(void *opaque, target_phys_addr_t offset)
{
    pl190_state *s = (pl190_state *)opaque;
    int i;

    if (offset >= 0xfe0 && offset < 0x1000) {
        return pl190_id[(offset - 0xfe0) >> 2];
    }
    if (offset >= 0x100 && offset < 0x140) {
        return s->vect_addr[(offset - 0x100) >> 2];
    }
    if (offset >= 0x200 && offset < 0x240) {
        return s->vect_control[(offset - 0x200) >> 2];
    }
    switch (offset >> 2) {
    case 0: /* IRQSTATUS */
        return pl190_irq_level(s);
    case 1: /* FIQSATUS */
        return (s->level | s->soft_level) & s->fiq_select;
    case 2: /* RAWINTR */
        return s->level | s->soft_level;
    case 3: /* INTSELECT */
        return s->fiq_select;
    case 4: /* INTENABLE */
        return s->irq_enable;
    case 6: /* SOFTINT */
        return s->soft_level;
    case 8: /* PROTECTION */
        return s->protected;
    case 12: /* VECTADDR */
        /* Read vector address at the start of an ISR.  Increases the
           current priority level to that of the current interrupt.  */
        for (i = 0; i < s->priority; i++)
          {
            if ((s->level | s->soft_level) & s->prio_mask[i])
              break;
          }
        /* Reading this value with no pending interrupts is undefined.
           We return the default address.  */
        if (i == PL190_NUM_PRIO)
          return s->vect_addr[16];
        if (i < s->priority)
          {
            s->prev_prio[i] = s->priority;
            s->priority = i;
            pl190_update(s);
          }
        return s->vect_addr[s->priority];
    case 13: /* DEFVECTADDR */
        return s->vect_addr[16];
    default:
        hw_error("pl190_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val)
{
    pl190_state *s = (pl190_state *)opaque;

    if (offset >= 0x100 && offset < 0x140) {
        s->vect_addr[(offset - 0x100) >> 2] = val;
        pl190_update_vectors(s);
        return;
    }
    if (offset >= 0x200 && offset < 0x240) {
        s->vect_control[(offset - 0x200) >> 2] = val;
        pl190_update_vectors(s);
        return;
    }
    switch (offset >> 2) {
    case 0: /* SELECT */
        /* This is a readonly register, but linux tries to write to it
           anyway.  Ignore the write.  */
        break;
    case 3: /* INTSELECT */
        s->fiq_select = val;
        break;
    case 4: /* INTENABLE */
        s->irq_enable |= val;
        break;
    case 5: /* INTENCLEAR */
        s->irq_enable &= ~val;
        break;
    case 6: /* SOFTINT */
        s->soft_level |= val;
        break;
    case 7: /* SOFTINTCLEAR */
        s->soft_level &= ~val;
        break;
    case 8: /* PROTECTION */
        /* TODO: Protection (supervisor only access) is not implemented.  */
        s->protected = val & 1;
        break;
    case 12: /* VECTADDR */
        /* Restore the previous priority level.  The value written is
           ignored.  */
        if (s->priority < PL190_NUM_PRIO)
            s->priority = s->prev_prio[s->priority];
        break;
    case 13: /* DEFVECTADDR */
        s->vect_addr[16] = val;
        break;
    case 0xc0: /* ITCR */
        if (val) {
            hw_error("pl190: Test mode not implemented\n");
        }
        break;
    default:
        hw_error("pl190_write: Bad offset %x\n", (int)offset);
        return;
    }
    pl190_update(s);
}

static CPUReadMemoryFunc * const pl190_readfn[] = {
   pl190_read,
   pl190_read,
   pl190_read
};

static CPUWriteMemoryFunc * const pl190_writefn[] = {
   pl190_write,
   pl190_write,
   pl190_write
};

static void pl190_reset(DeviceState *d)
{
  pl190_state *s = DO_UPCAST(pl190_state, busdev.qdev, d);
  int i;

  for (i = 0; i < 16; i++)
    {
      s->vect_addr[i] = 0;
      s->vect_control[i] = 0;
    }
  s->vect_addr[16] = 0;
  s->prio_mask[17] = 0xffffffff;
  s->priority = PL190_NUM_PRIO;
  pl190_update_vectors(s);
}

static int pl190_init(SysBusDevice *dev)
{
    pl190_state *s = FROM_SYSBUS(pl190_state, dev);
    int iomemtype;

    iomemtype = cpu_register_io_memory(pl190_readfn,
                                       pl190_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
    sysbus_init_irq(dev, &s->irq);
    sysbus_init_irq(dev, &s->fiq);
    return 0;
}

static const VMStateDescription vmstate_pl190 = {
    .name = "pl190",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(level, pl190_state),
        VMSTATE_UINT32(soft_level, pl190_state),
        VMSTATE_UINT32(irq_enable, pl190_state),
        VMSTATE_UINT32(fiq_select, pl190_state),
        VMSTATE_UINT8_ARRAY(vect_control, pl190_state, 16),
        VMSTATE_UINT32_ARRAY(vect_addr, pl190_state, PL190_NUM_PRIO),
        VMSTATE_UINT32_ARRAY(prio_mask, pl190_state, PL190_NUM_PRIO+1),
        VMSTATE_INT32(protected, pl190_state),
        VMSTATE_INT32(priority, pl190_state),
        VMSTATE_INT32_ARRAY(prev_prio, pl190_state, PL190_NUM_PRIO),
        VMSTATE_END_OF_LIST()
    }
};

static SysBusDeviceInfo pl190_info = {
    .init = pl190_init,
    .qdev.name = "pl190",
    .qdev.size = sizeof(pl190_state),
    .qdev.vmsd = &vmstate_pl190,
    .qdev.reset = pl190_reset,
    .qdev.no_user = 1,
};

static void pl190_register_devices(void)
{
    sysbus_register_withprop(&pl190_info);
}

device_init(pl190_register_devices)
Commit	Line	Data
5fafdf24	1	/*
cdbdb648 PB	2	* Arm PrimeCell PL190 Vector Interrupt Controller
	3	*
	4	* Copyright (c) 2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
97aff481	10	#include "sysbus.h"
cdbdb648 PB	11
	12	/* The number of virtual priority levels. 16 user vectors plus the
	13	unvectored IRQ. Chained interrupts would require an additional level
	14	if implemented. */
	15
	16	#define PL190_NUM_PRIO 17
	17
	18	typedef struct {
97aff481	19	SysBusDevice busdev;
cdbdb648 PB	20	uint32_t level;
	21	uint32_t soft_level;
	22	uint32_t irq_enable;
	23	uint32_t fiq_select;
cdbdb648 PB	24	uint8_t vect_control[16];
	25	uint32_t vect_addr[PL190_NUM_PRIO];
	26	/* Mask containing interrupts with higher priority than this one. */
	27	uint32_t prio_mask[PL190_NUM_PRIO + 1];
	28	int protected;
	29	/* Current priority level. */
	30	int priority;
	31	int prev_prio[PL190_NUM_PRIO];
d537cf6c PB	32	qemu_irq irq;
d537cf6c PB	33	qemu_irq fiq;
cdbdb648 PB	34	} pl190_state;
	35
	36	static const unsigned char pl190_id[] =
	37	{ 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 };
	38
	39	static inline uint32_t pl190_irq_level(pl190_state *s)
	40	{
	41	return (s->level \| s->soft_level) & s->irq_enable & ~s->fiq_select;
	42	}
	43
	44	/* Update interrupts. */
	45	static void pl190_update(pl190_state *s)
	46	{
	47	uint32_t level = pl190_irq_level(s);
	48	int set;
	49
	50	set = (level & s->prio_mask[s->priority]) != 0;
d537cf6c	51	qemu_set_irq(s->irq, set);
cdbdb648	52	set = ((s->level \| s->soft_level) & s->fiq_select) != 0;
d537cf6c	53	qemu_set_irq(s->fiq, set);
cdbdb648 PB	54	}
	55
	56	static void pl190_set_irq(void *opaque, int irq, int level)
	57	{
	58	pl190_state s = (pl190_state )opaque;
	59
	60	if (level)
	61	s->level \|= 1u << irq;
	62	else
	63	s->level &= ~(1u << irq);
	64	pl190_update(s);
	65	}
	66
	67	static void pl190_update_vectors(pl190_state *s)
	68	{
	69	uint32_t mask;
	70	int i;
	71	int n;
	72
	73	mask = 0;
	74	for (i = 0; i < 16; i++)
	75	{
	76	s->prio_mask[i] = mask;
	77	if (s->vect_control[i] & 0x20)
	78	{
	79	n = s->vect_control[i] & 0x1f;
	80	mask \|= 1 << n;
	81	}
	82	}
	83	s->prio_mask[16] = mask;
	84	pl190_update(s);
	85	}
	86
c227f099	87	static uint32_t pl190_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	88	{
	89	pl190_state s = (pl190_state )opaque;
	90	int i;
	91
cdbdb648 PB	92	if (offset >= 0xfe0 && offset < 0x1000) {
	93	return pl190_id[(offset - 0xfe0) >> 2];
	94	}
	95	if (offset >= 0x100 && offset < 0x140) {
	96	return s->vect_addr[(offset - 0x100) >> 2];
	97	}
	98	if (offset >= 0x200 && offset < 0x240) {
	99	return s->vect_control[(offset - 0x200) >> 2];
	100	}
	101	switch (offset >> 2) {
	102	case 0: /* IRQSTATUS */
	103	return pl190_irq_level(s);
	104	case 1: /* FIQSATUS */
	105	return (s->level \| s->soft_level) & s->fiq_select;
	106	case 2: /* RAWINTR */
	107	return s->level \| s->soft_level;
	108	case 3: /* INTSELECT */
	109	return s->fiq_select;
	110	case 4: /* INTENABLE */
	111	return s->irq_enable;
	112	case 6: /* SOFTINT */
	113	return s->soft_level;
	114	case 8: /* PROTECTION */
	115	return s->protected;
	116	case 12: /* VECTADDR */
	117	/* Read vector address at the start of an ISR. Increases the
	118	current priority level to that of the current interrupt. */
	119	for (i = 0; i < s->priority; i++)
	120	{
	121	if ((s->level \| s->soft_level) & s->prio_mask[i])
	122	break;
	123	}
	124	/* Reading this value with no pending interrupts is undefined.
	125	We return the default address. */
	126	if (i == PL190_NUM_PRIO)
	127	return s->vect_addr[16];
	128	if (i < s->priority)
	129	{
	130	s->prev_prio[i] = s->priority;
	131	s->priority = i;
	132	pl190_update(s);
	133	}
	134	return s->vect_addr[s->priority];
	135	case 13: /* DEFVECTADDR */
	136	return s->vect_addr[16];
	137	default:
2ac71179	138	hw_error("pl190_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	139	return 0;
	140	}
	141	}
	142
c227f099	143	static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val)
cdbdb648 PB	144	{
	145	pl190_state s = (pl190_state )opaque;
	146
cdbdb648 PB	147	if (offset >= 0x100 && offset < 0x140) {
	148	s->vect_addr[(offset - 0x100) >> 2] = val;
	149	pl190_update_vectors(s);
	150	return;
	151	}
	152	if (offset >= 0x200 && offset < 0x240) {
	153	s->vect_control[(offset - 0x200) >> 2] = val;
	154	pl190_update_vectors(s);
	155	return;
	156	}
	157	switch (offset >> 2) {
	158	case 0: /* SELECT */
	159	/* This is a readonly register, but linux tries to write to it
	160	anyway. Ignore the write. */
	161	break;
	162	case 3: /* INTSELECT */
	163	s->fiq_select = val;
	164	break;
	165	case 4: /* INTENABLE */
	166	s->irq_enable \|= val;
	167	break;
	168	case 5: /* INTENCLEAR */
	169	s->irq_enable &= ~val;
	170	break;
	171	case 6: /* SOFTINT */
	172	s->soft_level \|= val;
	173	break;
	174	case 7: /* SOFTINTCLEAR */
	175	s->soft_level &= ~val;
	176	break;
	177	case 8: /* PROTECTION */
	178	/* TODO: Protection (supervisor only access) is not implemented. */
	179	s->protected = val & 1;
	180	break;
	181	case 12: /* VECTADDR */
	182	/* Restore the previous priority level. The value written is
	183	ignored. */
	184	if (s->priority < PL190_NUM_PRIO)
	185	s->priority = s->prev_prio[s->priority];
	186	break;
	187	case 13: /* DEFVECTADDR */
730986e4	188	s->vect_addr[16] = val;
cdbdb648 PB	189	break;
cdbdb648 PB	190	case 0xc0: /* ITCR */
2ac71179 PB	191	if (val) {
	192	hw_error("pl190: Test mode not implemented\n");
	193	}
cdbdb648 PB	194	break;
cdbdb648 PB	195	default:
2ac71179	196	hw_error("pl190_write: Bad offset %x\n", (int)offset);
cdbdb648 PB	197	return;
	198	}
	199	pl190_update(s);
	200	}
	201
d60efc6b	202	static CPUReadMemoryFunc * const pl190_readfn[] = {
cdbdb648 PB	203	pl190_read,
	204	pl190_read,
	205	pl190_read
	206	};
	207
d60efc6b	208	static CPUWriteMemoryFunc * const pl190_writefn[] = {
cdbdb648 PB	209	pl190_write,
	210	pl190_write,
	211	pl190_write
	212	};
	213
ac49d750	214	static void pl190_reset(DeviceState *d)
cdbdb648	215	{
ac49d750	216	pl190_state *s = DO_UPCAST(pl190_state, busdev.qdev, d);
cdbdb648 PB	217	int i;
	218
	219	for (i = 0; i < 16; i++)
	220	{
	221	s->vect_addr[i] = 0;
	222	s->vect_control[i] = 0;
	223	}
	224	s->vect_addr[16] = 0;
	225	s->prio_mask[17] = 0xffffffff;
	226	s->priority = PL190_NUM_PRIO;
	227	pl190_update_vectors(s);
	228	}
	229
81a322d4	230	static int pl190_init(SysBusDevice *dev)
cdbdb648	231	{
97aff481	232	pl190_state *s = FROM_SYSBUS(pl190_state, dev);
cdbdb648 PB	233	int iomemtype;
cdbdb648 PB	234
1eed09cb	235	iomemtype = cpu_register_io_memory(pl190_readfn,
2507c12a AG	236	pl190_writefn, s,
2507c12a AG	237	DEVICE_NATIVE_ENDIAN);
97aff481	238	sysbus_init_mmio(dev, 0x1000, iomemtype);
067a3ddc	239	qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
97aff481 PB	240	sysbus_init_irq(dev, &s->irq);
97aff481 PB	241	sysbus_init_irq(dev, &s->fiq);
81a322d4	242	return 0;
cdbdb648	243	}
97aff481	244
ac49d750 PM	245	static const VMStateDescription vmstate_pl190 = {
	246	.name = "pl190",
	247	.version_id = 1,
	248	.minimum_version_id = 1,
	249	.fields = (VMStateField[]) {
	250	VMSTATE_UINT32(level, pl190_state),
	251	VMSTATE_UINT32(soft_level, pl190_state),
	252	VMSTATE_UINT32(irq_enable, pl190_state),
	253	VMSTATE_UINT32(fiq_select, pl190_state),
ac49d750 PM	254	VMSTATE_UINT8_ARRAY(vect_control, pl190_state, 16),
	255	VMSTATE_UINT32_ARRAY(vect_addr, pl190_state, PL190_NUM_PRIO),
	256	VMSTATE_UINT32_ARRAY(prio_mask, pl190_state, PL190_NUM_PRIO+1),
	257	VMSTATE_INT32(protected, pl190_state),
	258	VMSTATE_INT32(priority, pl190_state),
	259	VMSTATE_INT32_ARRAY(prev_prio, pl190_state, PL190_NUM_PRIO),
	260	VMSTATE_END_OF_LIST()
	261	}
	262	};
	263
	264	static SysBusDeviceInfo pl190_info = {
	265	.init = pl190_init,
	266	.qdev.name = "pl190",
	267	.qdev.size = sizeof(pl190_state),
	268	.qdev.vmsd = &vmstate_pl190,
	269	.qdev.reset = pl190_reset,
	270	.qdev.no_user = 1,
	271	};
	272
97aff481 PB	273	static void pl190_register_devices(void)
97aff481 PB	274	{
ac49d750	275	sysbus_register_withprop(&pl190_info);
97aff481 PB	276	}
	277
	278	device_init(pl190_register_devices)