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Commit | Line | Data |
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87ecb68b PB |
1 | #ifndef QEMU_IRQ_H |
2 | #define QEMU_IRQ_H | |
3 | ||
d537cf6c PB |
4 | /* Generic IRQ/GPIO pin infrastructure. */ |
5 | ||
6 | typedef void (*qemu_irq_handler)(void *opaque, int n, int level); | |
d537cf6c PB |
7 | |
8 | void qemu_set_irq(qemu_irq irq, int level); | |
9 | ||
10 | static inline void qemu_irq_raise(qemu_irq irq) | |
11 | { | |
12 | qemu_set_irq(irq, 1); | |
13 | } | |
14 | ||
15 | static inline void qemu_irq_lower(qemu_irq irq) | |
16 | { | |
17 | qemu_set_irq(irq, 0); | |
18 | } | |
19 | ||
106627d0 AZ |
20 | static inline void qemu_irq_pulse(qemu_irq irq) |
21 | { | |
22 | qemu_set_irq(irq, 1); | |
23 | qemu_set_irq(irq, 0); | |
24 | } | |
25 | ||
d537cf6c PB |
26 | /* Returns an array of N IRQs. */ |
27 | qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n); | |
51bf9e7e | 28 | void qemu_free_irqs(qemu_irq *s); |
d537cf6c | 29 | |
b50a6563 AZ |
30 | /* Returns a new IRQ with opposite polarity. */ |
31 | qemu_irq qemu_irq_invert(qemu_irq irq); | |
87ecb68b | 32 | |
9793212b PM |
33 | /* Returns a new IRQ which feeds into both the passed IRQs */ |
34 | qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); | |
35 | ||
22ec3283 AK |
36 | /* Returns a new IRQ set which connects 1:1 to another IRQ set, which |
37 | * may be set later. | |
38 | */ | |
39 | qemu_irq *qemu_irq_proxy(qemu_irq **target, int n); | |
40 | ||
87ecb68b | 41 | #endif |