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Commit | Line | Data |
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da9fcfa5 AT |
1 | /* |
2 | * QEMU Empty Slot | |
3 | * | |
4 | * The empty_slot device emulates known to a bus but not connected devices. | |
5 | * | |
6 | * Copyright (c) 2010 Artyom Tarasenko | |
7 | * | |
8 | * This code is licensed under the GNU GPL v2 or (at your option) any later | |
9 | * version. | |
10 | */ | |
11 | ||
12 | #include "hw.h" | |
13 | #include "sysbus.h" | |
14 | #include "empty_slot.h" | |
15 | ||
16 | //#define DEBUG_EMPTY_SLOT | |
17 | ||
18 | #ifdef DEBUG_EMPTY_SLOT | |
19 | #define DPRINTF(fmt, ...) \ | |
20 | do { printf("empty_slot: " fmt , ## __VA_ARGS__); } while (0) | |
21 | #else | |
22 | #define DPRINTF(fmt, ...) do {} while (0) | |
23 | #endif | |
24 | ||
25 | typedef struct EmptySlot { | |
26 | SysBusDevice busdev; | |
27 | uint64_t size; | |
28 | } EmptySlot; | |
29 | ||
30 | static uint32_t empty_slot_readl(void *opaque, target_phys_addr_t addr) | |
31 | { | |
32 | DPRINTF("read from " TARGET_FMT_plx "\n", addr); | |
33 | return 0; | |
34 | } | |
35 | ||
36 | static void empty_slot_writel(void *opaque, target_phys_addr_t addr, | |
37 | uint32_t val) | |
38 | { | |
39 | DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", val, addr); | |
40 | } | |
41 | ||
42 | CPUReadMemoryFunc * const empty_slot_read[3] = { | |
43 | empty_slot_readl, | |
44 | empty_slot_readl, | |
45 | empty_slot_readl, | |
46 | }; | |
47 | ||
48 | static CPUWriteMemoryFunc * const empty_slot_write[3] = { | |
49 | empty_slot_writel, | |
50 | empty_slot_writel, | |
51 | empty_slot_writel, | |
52 | }; | |
53 | ||
54 | void empty_slot_init(target_phys_addr_t addr, uint64_t slot_size) | |
55 | { | |
1a00282a SW |
56 | if (slot_size > 0) { |
57 | /* Only empty slots larger than 0 byte need handling. */ | |
58 | DeviceState *dev; | |
59 | SysBusDevice *s; | |
60 | EmptySlot *e; | |
da9fcfa5 | 61 | |
1a00282a SW |
62 | dev = qdev_create(NULL, "empty_slot"); |
63 | s = sysbus_from_qdev(dev); | |
64 | e = FROM_SYSBUS(EmptySlot, s); | |
65 | e->size = slot_size; | |
da9fcfa5 | 66 | |
1a00282a | 67 | qdev_init_nofail(dev); |
da9fcfa5 | 68 | |
1a00282a SW |
69 | sysbus_mmio_map(s, 0, addr); |
70 | } | |
da9fcfa5 AT |
71 | } |
72 | ||
73 | static int empty_slot_init1(SysBusDevice *dev) | |
74 | { | |
75 | EmptySlot *s = FROM_SYSBUS(EmptySlot, dev); | |
76 | ram_addr_t empty_slot_offset; | |
77 | ||
78 | empty_slot_offset = cpu_register_io_memory(empty_slot_read, | |
2507c12a AG |
79 | empty_slot_write, s, |
80 | DEVICE_NATIVE_ENDIAN); | |
da9fcfa5 AT |
81 | sysbus_init_mmio(dev, s->size, empty_slot_offset | IO_MEM_RAM); |
82 | return 0; | |
83 | } | |
84 | ||
85 | static SysBusDeviceInfo empty_slot_info = { | |
86 | .init = empty_slot_init1, | |
87 | .qdev.name = "empty_slot", | |
88 | .qdev.size = sizeof(EmptySlot), | |
89 | }; | |
90 | ||
91 | static void empty_slot_register_devices(void) | |
92 | { | |
93 | sysbus_register_withprop(&empty_slot_info); | |
94 | } | |
95 | ||
96 | device_init(empty_slot_register_devices); |