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ac97: Use PCI DMA stub functions
[qemu.git] / hw / bt.h
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1ae26a18
AZ		 1/*
2 * QEMU Bluetooth HCI helpers.
3 *
4 * Copyright (C) 2007 OpenMoko, Inc.
5 * Written by Andrzej Zaborowski <[email protected]>
6 *
4e38eb54
AZ		 7 * Useful definitions taken from BlueZ project's headers.
8 * Copyright (C) 2000-2001 Qualcomm Incorporated
9 * Copyright (C) 2002-2003 Maxim Krasnyansky <[email protected]>
10 * Copyright (C) 2002-2006 Marcel Holtmann <[email protected]>
11 *
1ae26a18
AZ		 12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
8167ee88 23 * along with this program; if not, see <http://www.gnu.org/licenses/>.
1ae26a18
AZ		 24 */
25
26/* BD Address */
27typedef struct {
28 uint8_t b[6];
541dc0d4 29} QEMU_PACKED bdaddr_t;
1ae26a18 30
c227f099
AL		 31#define BDADDR_ANY (&(bdaddr_t) {{0, 0, 0, 0, 0, 0}})
32#define BDADDR_ALL (&(bdaddr_t) {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}})
33#define BDADDR_LOCAL (&(bdaddr_t) {{0, 0, 0, 0xff, 0xff, 0xff}})
1ae26a18
AZ		 34
35/* Copy, swap, convert BD Address */
c227f099 36static inline int bacmp(const bdaddr_t *ba1, const bdaddr_t *ba2)
1ae26a18 37{
c227f099 38 return memcmp(ba1, ba2, sizeof(bdaddr_t));
1ae26a18 39}
c227f099 40static inline void bacpy(bdaddr_t *dst, const bdaddr_t *src)
1ae26a18 41{
c227f099 42 memcpy(dst, src, sizeof(bdaddr_t));
1ae26a18
AZ		 43}
44
45#define BAINIT(orig) { .b = { \
46 (orig)->b[0], (orig)->b[1], (orig)->b[2], \
47 (orig)->b[3], (orig)->b[4], (orig)->b[5], \
48}, }
49
50/* The twisted structures of a bluetooth environment */
51struct bt_device_s;
52struct bt_scatternet_s;
53struct bt_piconet_s;
54struct bt_link_s;
55
56struct bt_scatternet_s {
57 struct bt_device_s *slave;
58};
59
60struct bt_link_s {
61 struct bt_device_s *slave, *host;
62 uint16_t handle; /* Master (host) side handle */
63 uint16_t acl_interval;
64 enum {
65 acl_active,
66 acl_hold,
67 acl_sniff,
68 acl_parked,
69 } acl_mode;
70};
71
72struct bt_device_s {
73 int lt_addr;
c227f099 74 bdaddr_t bd_addr;
1ae26a18
AZ		 75 int mtu;
76 int setup;
77 struct bt_scatternet_s *net;
78
79 uint8_t key[16];
80 int key_present;
81 uint8_t class[3];
82
83 uint8_t reject_reason;
84
85 uint64_t lmp_caps;
86 const char *lmp_name;
87 void (*lmp_connection_request)(struct bt_link_s *link);
88 void (*lmp_connection_complete)(struct bt_link_s *link);
89 void (*lmp_disconnect_master)(struct bt_link_s *link);
90 void (*lmp_disconnect_slave)(struct bt_link_s *link);
91 void (*lmp_acl_data)(struct bt_link_s *link, const uint8_t *data,
92 int start, int len);
93 void (*lmp_acl_resp)(struct bt_link_s *link, const uint8_t *data,
94 int start, int len);
95 void (*lmp_mode_change)(struct bt_link_s *link);
96
97 void (*handle_destroy)(struct bt_device_s *device);
98 struct bt_device_s *next; /* Next in the piconet/scatternet */
99
100 int inquiry_scan;
101 int page_scan;
102
103 uint16_t clkoff; /* Note: Always little-endian */
104};
105
106/* bt.c */
107void bt_device_init(struct bt_device_s *dev, struct bt_scatternet_s *net);
108void bt_device_done(struct bt_device_s *dev);
58a26b47 109
4e38eb54
AZ		 110/* bt-hci.c */
111struct HCIInfo *bt_new_hci(struct bt_scatternet_s *net);
112
ab2b6f50
AZ		 113/* bt-vhci.c */
114void bt_vhci_init(struct HCIInfo *info);
115
58a26b47
AZ		 116/* bt-hci-csr.c */
117enum {
118 csrhci_pin_reset,
119 csrhci_pin_wakeup,
120 __csrhci_pins,
121};
122qemu_irq *csrhci_pins_get(CharDriverState *chr);
123CharDriverState *uart_hci_init(qemu_irq wakeup);
124
4d2d181c
AZ		 125/* bt-l2cap.c */
126struct bt_l2cap_device_s;
127struct bt_l2cap_conn_params_s;
128struct bt_l2cap_psm_s;
129void bt_l2cap_device_init(struct bt_l2cap_device_s *dev,
130 struct bt_scatternet_s *net);
131void bt_l2cap_device_done(struct bt_l2cap_device_s *dev);
132void bt_l2cap_psm_register(struct bt_l2cap_device_s *dev, int psm,
133 int min_mtu, int (*new_channel)(struct bt_l2cap_device_s *dev,
134 struct bt_l2cap_conn_params_s *params));
135
136struct bt_l2cap_device_s {
137 struct bt_device_s device;
138 struct bt_l2cap_psm_s *first_psm;
139};
140
141struct bt_l2cap_conn_params_s {
142 /* Input */
143 uint8_t *(*sdu_out)(struct bt_l2cap_conn_params_s *chan, int len);
144 void (*sdu_submit)(struct bt_l2cap_conn_params_s *chan);
145 int remote_mtu;
146 /* Output */
147 void *opaque;
148 void (*sdu_in)(void *opaque, const uint8_t *data, int len);
149 void (*close)(void *opaque);
150};
151
152enum bt_l2cap_psm_predef {
153 BT_PSM_SDP = 0x0001,
154 BT_PSM_RFCOMM = 0x0003,
155 BT_PSM_TELEPHONY = 0x0005,
156 BT_PSM_TCS = 0x0007,
157 BT_PSM_BNEP = 0x000f,
158 BT_PSM_HID_CTRL = 0x0011,
159 BT_PSM_HID_INTR = 0x0013,
160 BT_PSM_UPNP = 0x0015,
161 BT_PSM_AVCTP = 0x0017,
162 BT_PSM_AVDTP = 0x0019,
163};
164
165/* bt-sdp.c */
166void bt_l2cap_sdp_init(struct bt_l2cap_device_s *dev);
167
ab2b6f50
AZ		 168/* bt-hid.c */
169struct bt_device_s *bt_mouse_init(struct bt_scatternet_s *net);
170struct bt_device_s *bt_tablet_init(struct bt_scatternet_s *net);
171struct bt_device_s *bt_keyboard_init(struct bt_scatternet_s *net);
172
58a26b47
AZ		 173/* Link Management Protocol layer defines */
174
175#define LLID_ACLU_CONT 0x1
176#define LLID_ACLU_START 0x2
177#define LLID_ACLC 0x3
178
179enum lmp_pdu_type {
180 LMP_NAME_REQ = 0x0001,
181 LMP_NAME_RES = 0x0002,
182 LMP_ACCEPTED = 0x0003,
183 LMP_NOT_ACCEPTED = 0x0004,
184 LMP_CLKOFFSET_REQ = 0x0005,
185 LMP_CLKOFFSET_RES = 0x0006,
186 LMP_DETACH = 0x0007,
187 LMP_IN_RAND = 0x0008,
188 LMP_COMB_KEY = 0x0009,
189 LMP_UNIT_KEY = 0x000a,
190 LMP_AU_RAND = 0x000b,
191 LMP_SRES = 0x000c,
192 LMP_TEMP_RAND = 0x000d,
193 LMP_TEMP_KEY = 0x000e,
194 LMP_CRYPT_MODE_REQ = 0x000f,
195 LMP_CRYPT_KEY_SIZE_REQ = 0x0010,
196 LMP_START_ENCRYPT_REQ = 0x0011,
197 LMP_STOP_ENCRYPT_REQ = 0x0012,
198 LMP_SWITCH_REQ = 0x0013,
199 LMP_HOLD = 0x0014,
200 LMP_HOLD_REQ = 0x0015,
201 LMP_SNIFF_REQ = 0x0017,
202 LMP_UNSNIFF_REQ = 0x0018,
203 LMP_LMP_PARK_REQ = 0x0019,
204 LMP_SET_BCAST_SCAN_WND = 0x001b,
205 LMP_MODIFY_BEACON = 0x001c,
206 LMP_UNPARK_BD_ADDR_REQ = 0x001d,
207 LMP_UNPARK_PM_ADDR_REQ = 0x001e,
208 LMP_INCR_POWER_REQ = 0x001f,
209 LMP_DECR_POWER_REQ = 0x0020,
210 LMP_MAX_POWER = 0x0021,
211 LMP_MIN_POWER = 0x0022,
212 LMP_AUTO_RATE = 0x0023,
213 LMP_PREFERRED_RATE = 0x0024,
214 LMP_VERSION_REQ = 0x0025,
215 LMP_VERSION_RES = 0x0026,
216 LMP_FEATURES_REQ = 0x0027,
217 LMP_FEATURES_RES = 0x0028,
218 LMP_QUALITY_OF_SERVICE = 0x0029,
219 LMP_QOS_REQ = 0x002a,
220 LMP_RM_SCO_LINK_REQ = 0x002b,
221 LMP_SCO_LINK_REQ = 0x002c,
222 LMP_MAX_SLOT = 0x002d,
223 LMP_MAX_SLOT_REQ = 0x002e,
224 LMP_TIMING_ACCURACY_REQ = 0x002f,
225 LMP_TIMING_ACCURACY_RES = 0x0030,
226 LMP_SETUP_COMPLETE = 0x0031,
227 LMP_USE_SEMIPERM_KEY = 0x0032,
228 LMP_HOST_CONNECTION_REQ = 0x0033,
229 LMP_SLOT_OFFSET = 0x0034,
230 LMP_PAGE_MODE_REQ = 0x0035,
231 LMP_PAGE_SCAN_MODE_REQ = 0x0036,
232 LMP_SUPERVISION_TIMEOUT = 0x0037,
233 LMP_TEST_ACTIVATE = 0x0038,
234 LMP_TEST_CONTROL = 0x0039,
235 LMP_CRYPT_KEY_MASK_REQ = 0x003a,
236 LMP_CRYPT_KEY_MASK_RES = 0x003b,
237 LMP_SET_AFH = 0x003c,
238 LMP_ACCEPTED_EXT = 0x7f01,
239 LMP_NOT_ACCEPTED_EXT = 0x7f02,
240 LMP_FEATURES_REQ_EXT = 0x7f03,
241 LMP_FEATURES_RES_EXT = 0x7f04,
242 LMP_PACKET_TYPE_TBL_REQ = 0x7f0b,
243 LMP_ESCO_LINK_REQ = 0x7f0c,
244 LMP_RM_ESCO_LINK_REQ = 0x7f0d,
245 LMP_CHANNEL_CLASS_REQ = 0x7f10,
246 LMP_CHANNEL_CLASS = 0x7f11,
247};
248
249/* Host Controller Interface layer defines */
250
251enum hci_packet_type {
252 HCI_COMMAND_PKT = 0x01,
253 HCI_ACLDATA_PKT = 0x02,
254 HCI_SCODATA_PKT = 0x03,
255 HCI_EVENT_PKT = 0x04,
256 HCI_VENDOR_PKT = 0xff,
257};
258
259enum bt_packet_type {
260 HCI_2DH1 = 1 << 1,
261 HCI_3DH1 = 1 << 2,
262 HCI_DM1 = 1 << 3,
263 HCI_DH1 = 1 << 4,
264 HCI_2DH3 = 1 << 8,
265 HCI_3DH3 = 1 << 9,
266 HCI_DM3 = 1 << 10,
267 HCI_DH3 = 1 << 11,
268 HCI_2DH5 = 1 << 12,
269 HCI_3DH5 = 1 << 13,
270 HCI_DM5 = 1 << 14,
271 HCI_DH5 = 1 << 15,
272};
273
274enum sco_packet_type {
275 HCI_HV1 = 1 << 5,
276 HCI_HV2 = 1 << 6,
277 HCI_HV3 = 1 << 7,
278};
279
280enum ev_packet_type {
281 HCI_EV3 = 1 << 3,
282 HCI_EV4 = 1 << 4,
283 HCI_EV5 = 1 << 5,
284 HCI_2EV3 = 1 << 6,
285 HCI_3EV3 = 1 << 7,
286 HCI_2EV5 = 1 << 8,
287 HCI_3EV5 = 1 << 9,
288};
289
290enum hci_error_code {
291 HCI_SUCCESS = 0x00,
292 HCI_UNKNOWN_COMMAND = 0x01,
293 HCI_NO_CONNECTION = 0x02,
294 HCI_HARDWARE_FAILURE = 0x03,
295 HCI_PAGE_TIMEOUT = 0x04,
296 HCI_AUTHENTICATION_FAILURE = 0x05,
297 HCI_PIN_OR_KEY_MISSING = 0x06,
298 HCI_MEMORY_FULL = 0x07,
299 HCI_CONNECTION_TIMEOUT = 0x08,
300 HCI_MAX_NUMBER_OF_CONNECTIONS = 0x09,
301 HCI_MAX_NUMBER_OF_SCO_CONNECTIONS = 0x0a,
302 HCI_ACL_CONNECTION_EXISTS = 0x0b,
303 HCI_COMMAND_DISALLOWED = 0x0c,
304 HCI_REJECTED_LIMITED_RESOURCES = 0x0d,
305 HCI_REJECTED_SECURITY = 0x0e,
306 HCI_REJECTED_PERSONAL = 0x0f,
307 HCI_HOST_TIMEOUT = 0x10,
308 HCI_UNSUPPORTED_FEATURE = 0x11,
309 HCI_INVALID_PARAMETERS = 0x12,
310 HCI_OE_USER_ENDED_CONNECTION = 0x13,
311 HCI_OE_LOW_RESOURCES = 0x14,
312 HCI_OE_POWER_OFF = 0x15,
313 HCI_CONNECTION_TERMINATED = 0x16,
314 HCI_REPEATED_ATTEMPTS = 0x17,
315 HCI_PAIRING_NOT_ALLOWED = 0x18,
316 HCI_UNKNOWN_LMP_PDU = 0x19,
317 HCI_UNSUPPORTED_REMOTE_FEATURE = 0x1a,
318 HCI_SCO_OFFSET_REJECTED = 0x1b,
319 HCI_SCO_INTERVAL_REJECTED = 0x1c,
320 HCI_AIR_MODE_REJECTED = 0x1d,
321 HCI_INVALID_LMP_PARAMETERS = 0x1e,
322 HCI_UNSPECIFIED_ERROR = 0x1f,
323 HCI_UNSUPPORTED_LMP_PARAMETER_VALUE = 0x20,
324 HCI_ROLE_CHANGE_NOT_ALLOWED = 0x21,
325 HCI_LMP_RESPONSE_TIMEOUT = 0x22,
326 HCI_LMP_ERROR_TRANSACTION_COLLISION = 0x23,
327 HCI_LMP_PDU_NOT_ALLOWED = 0x24,
328 HCI_ENCRYPTION_MODE_NOT_ACCEPTED = 0x25,
329 HCI_UNIT_LINK_KEY_USED = 0x26,
330 HCI_QOS_NOT_SUPPORTED = 0x27,
331 HCI_INSTANT_PASSED = 0x28,
332 HCI_PAIRING_NOT_SUPPORTED = 0x29,
333 HCI_TRANSACTION_COLLISION = 0x2a,
334 HCI_QOS_UNACCEPTABLE_PARAMETER = 0x2c,
335 HCI_QOS_REJECTED = 0x2d,
336 HCI_CLASSIFICATION_NOT_SUPPORTED = 0x2e,
337 HCI_INSUFFICIENT_SECURITY = 0x2f,
338 HCI_PARAMETER_OUT_OF_RANGE = 0x30,
339 HCI_ROLE_SWITCH_PENDING = 0x32,
340 HCI_SLOT_VIOLATION = 0x34,
341 HCI_ROLE_SWITCH_FAILED = 0x35,
342};
343
344enum acl_flag_bits {
345 ACL_CONT = 1 << 0,
346 ACL_START = 1 << 1,
347 ACL_ACTIVE_BCAST = 1 << 2,
348 ACL_PICO_BCAST = 1 << 3,
349};
350
351enum baseband_link_type {
352 SCO_LINK = 0x00,
353 ACL_LINK = 0x01,
354};
355
356enum lmp_feature_bits0 {
357 LMP_3SLOT = 1 << 0,
358 LMP_5SLOT = 1 << 1,
359 LMP_ENCRYPT = 1 << 2,
360 LMP_SOFFSET = 1 << 3,
361 LMP_TACCURACY = 1 << 4,
362 LMP_RSWITCH = 1 << 5,
363 LMP_HOLD_MODE = 1 << 6,
364 LMP_SNIFF_MODE = 1 << 7,
365};
366
367enum lmp_feature_bits1 {
368 LMP_PARK = 1 << 0,
369 LMP_RSSI = 1 << 1,
370 LMP_QUALITY = 1 << 2,
371 LMP_SCO = 1 << 3,
372 LMP_HV2 = 1 << 4,
373 LMP_HV3 = 1 << 5,
374 LMP_ULAW = 1 << 6,
375 LMP_ALAW = 1 << 7,
376};
377
378enum lmp_feature_bits2 {
379 LMP_CVSD = 1 << 0,
380 LMP_PSCHEME = 1 << 1,
381 LMP_PCONTROL = 1 << 2,
382 LMP_TRSP_SCO = 1 << 3,
383 LMP_BCAST_ENC = 1 << 7,
384};
385
386enum lmp_feature_bits3 {
387 LMP_EDR_ACL_2M = 1 << 1,
388 LMP_EDR_ACL_3M = 1 << 2,
389 LMP_ENH_ISCAN = 1 << 3,
390 LMP_ILACE_ISCAN = 1 << 4,
391 LMP_ILACE_PSCAN = 1 << 5,
392 LMP_RSSI_INQ = 1 << 6,
393 LMP_ESCO = 1 << 7,
394};
395
396enum lmp_feature_bits4 {
397 LMP_EV4 = 1 << 0,
398 LMP_EV5 = 1 << 1,
399 LMP_AFH_CAP_SLV = 1 << 3,
400 LMP_AFH_CLS_SLV = 1 << 4,
401 LMP_EDR_3SLOT = 1 << 7,
402};
403
404enum lmp_feature_bits5 {
405 LMP_EDR_5SLOT = 1 << 0,
406 LMP_SNIFF_SUBR = 1 << 1,
407 LMP_AFH_CAP_MST = 1 << 3,
408 LMP_AFH_CLS_MST = 1 << 4,
409 LMP_EDR_ESCO_2M = 1 << 5,
410 LMP_EDR_ESCO_3M = 1 << 6,
411 LMP_EDR_3S_ESCO = 1 << 7,
412};
413
414enum lmp_feature_bits6 {
415 LMP_EXT_INQ = 1 << 0,
416};
417
418enum lmp_feature_bits7 {
419 LMP_EXT_FEAT = 1 << 7,
420};
421
422enum hci_link_policy {
423 HCI_LP_RSWITCH = 1 << 0,
424 HCI_LP_HOLD = 1 << 1,
425 HCI_LP_SNIFF = 1 << 2,
426 HCI_LP_PARK = 1 << 3,
427};
428
429enum hci_link_mode {
430 HCI_LM_ACCEPT = 1 << 15,
431 HCI_LM_MASTER = 1 << 0,
432 HCI_LM_AUTH = 1 << 1,
433 HCI_LM_ENCRYPT = 1 << 2,
434 HCI_LM_TRUSTED = 1 << 3,
435 HCI_LM_RELIABLE = 1 << 4,
436 HCI_LM_SECURE = 1 << 5,
437};
438
439/* HCI Commands */
440
441/* Link Control */
442#define OGF_LINK_CTL 0x01
443
444#define OCF_INQUIRY 0x0001
445typedef struct {
446 uint8_t lap[3];
447 uint8_t length; /* 1.28s units */
448 uint8_t num_rsp;
541dc0d4 449} QEMU_PACKED inquiry_cp;
58a26b47
AZ		 450#define INQUIRY_CP_SIZE 5
451
452typedef struct {
453 uint8_t status;
c227f099 454 bdaddr_t bdaddr;
541dc0d4 455} QEMU_PACKED status_bdaddr_rp;
58a26b47
AZ		 456#define STATUS_BDADDR_RP_SIZE 7
457
458#define OCF_INQUIRY_CANCEL 0x0002
459
460#define OCF_PERIODIC_INQUIRY 0x0003
461typedef struct {
462 uint16_t max_period; /* 1.28s units */
463 uint16_t min_period; /* 1.28s units */
464 uint8_t lap[3];
465 uint8_t length; /* 1.28s units */
466 uint8_t num_rsp;
541dc0d4 467} QEMU_PACKED periodic_inquiry_cp;
58a26b47
AZ		 468#define PERIODIC_INQUIRY_CP_SIZE 9
469
470#define OCF_EXIT_PERIODIC_INQUIRY 0x0004
471
472#define OCF_CREATE_CONN 0x0005
473typedef struct {
c227f099 474 bdaddr_t bdaddr;
58a26b47
AZ		 475 uint16_t pkt_type;
476 uint8_t pscan_rep_mode;
477 uint8_t pscan_mode;
478 uint16_t clock_offset;
479 uint8_t role_switch;
541dc0d4 480} QEMU_PACKED create_conn_cp;
58a26b47
AZ		 481#define CREATE_CONN_CP_SIZE 13
482
483#define OCF_DISCONNECT 0x0006
484typedef struct {
485 uint16_t handle;
486 uint8_t reason;
541dc0d4 487} QEMU_PACKED disconnect_cp;
58a26b47
AZ		 488#define DISCONNECT_CP_SIZE 3
489
490#define OCF_ADD_SCO 0x0007
491typedef struct {
492 uint16_t handle;
493 uint16_t pkt_type;
541dc0d4 494} QEMU_PACKED add_sco_cp;
58a26b47
AZ		 495#define ADD_SCO_CP_SIZE 4
496
497#define OCF_CREATE_CONN_CANCEL 0x0008
498typedef struct {
499 uint8_t status;
c227f099 500 bdaddr_t bdaddr;
541dc0d4 501} QEMU_PACKED create_conn_cancel_cp;
58a26b47
AZ		 502#define CREATE_CONN_CANCEL_CP_SIZE 6
503
504typedef struct {
505 uint8_t status;
c227f099 506 bdaddr_t bdaddr;
541dc0d4 507} QEMU_PACKED create_conn_cancel_rp;
58a26b47
AZ		 508#define CREATE_CONN_CANCEL_RP_SIZE 7
509
510#define OCF_ACCEPT_CONN_REQ 0x0009
511typedef struct {
c227f099 512 bdaddr_t bdaddr;
58a26b47 513 uint8_t role;
541dc0d4 514} QEMU_PACKED accept_conn_req_cp;
58a26b47
AZ		 515#define ACCEPT_CONN_REQ_CP_SIZE 7
516
517#define OCF_REJECT_CONN_REQ 0x000A
518typedef struct {
c227f099 519 bdaddr_t bdaddr;
58a26b47 520 uint8_t reason;
541dc0d4 521} QEMU_PACKED reject_conn_req_cp;
58a26b47
AZ		 522#define REJECT_CONN_REQ_CP_SIZE 7
523
524#define OCF_LINK_KEY_REPLY 0x000B
525typedef struct {
c227f099 526 bdaddr_t bdaddr;
58a26b47 527 uint8_t link_key[16];
541dc0d4 528} QEMU_PACKED link_key_reply_cp;
58a26b47
AZ		 529#define LINK_KEY_REPLY_CP_SIZE 22
530
531#define OCF_LINK_KEY_NEG_REPLY 0x000C
532
533#define OCF_PIN_CODE_REPLY 0x000D
534typedef struct {
c227f099 535 bdaddr_t bdaddr;
58a26b47
AZ		 536 uint8_t pin_len;
537 uint8_t pin_code[16];
541dc0d4 538} QEMU_PACKED pin_code_reply_cp;
58a26b47
AZ		 539#define PIN_CODE_REPLY_CP_SIZE 23
540
541#define OCF_PIN_CODE_NEG_REPLY 0x000E
542
543#define OCF_SET_CONN_PTYPE 0x000F
544typedef struct {
545 uint16_t handle;
546 uint16_t pkt_type;
541dc0d4 547} QEMU_PACKED set_conn_ptype_cp;
58a26b47
AZ		 548#define SET_CONN_PTYPE_CP_SIZE 4
549
550#define OCF_AUTH_REQUESTED 0x0011
551typedef struct {
552 uint16_t handle;
541dc0d4 553} QEMU_PACKED auth_requested_cp;
58a26b47
AZ		 554#define AUTH_REQUESTED_CP_SIZE 2
555
556#define OCF_SET_CONN_ENCRYPT 0x0013
557typedef struct {
558 uint16_t handle;
559 uint8_t encrypt;
541dc0d4 560} QEMU_PACKED set_conn_encrypt_cp;
58a26b47
AZ		 561#define SET_CONN_ENCRYPT_CP_SIZE 3
562
563#define OCF_CHANGE_CONN_LINK_KEY 0x0015
564typedef struct {
565 uint16_t handle;
541dc0d4 566} QEMU_PACKED change_conn_link_key_cp;
58a26b47
AZ		 567#define CHANGE_CONN_LINK_KEY_CP_SIZE 2
568
569#define OCF_MASTER_LINK_KEY 0x0017
570typedef struct {
571 uint8_t key_flag;
541dc0d4 572} QEMU_PACKED master_link_key_cp;
58a26b47
AZ		 573#define MASTER_LINK_KEY_CP_SIZE 1
574
575#define OCF_REMOTE_NAME_REQ 0x0019
576typedef struct {
c227f099 577 bdaddr_t bdaddr;
58a26b47
AZ		 578 uint8_t pscan_rep_mode;
579 uint8_t pscan_mode;
580 uint16_t clock_offset;
541dc0d4 581} QEMU_PACKED remote_name_req_cp;
58a26b47
AZ		 582#define REMOTE_NAME_REQ_CP_SIZE 10
583
584#define OCF_REMOTE_NAME_REQ_CANCEL 0x001A
585typedef struct {
c227f099 586 bdaddr_t bdaddr;
541dc0d4 587} QEMU_PACKED remote_name_req_cancel_cp;
58a26b47
AZ		 588#define REMOTE_NAME_REQ_CANCEL_CP_SIZE 6
589
590typedef struct {
591 uint8_t status;
c227f099 592 bdaddr_t bdaddr;
541dc0d4 593} QEMU_PACKED remote_name_req_cancel_rp;
58a26b47
AZ		 594#define REMOTE_NAME_REQ_CANCEL_RP_SIZE 7
595
596#define OCF_READ_REMOTE_FEATURES 0x001B
597typedef struct {
598 uint16_t handle;
541dc0d4 599} QEMU_PACKED read_remote_features_cp;
58a26b47
AZ		 600#define READ_REMOTE_FEATURES_CP_SIZE 2
601
602#define OCF_READ_REMOTE_EXT_FEATURES 0x001C
603typedef struct {
604 uint16_t handle;
605 uint8_t page_num;
541dc0d4 606} QEMU_PACKED read_remote_ext_features_cp;
58a26b47
AZ		 607#define READ_REMOTE_EXT_FEATURES_CP_SIZE 3
608
609#define OCF_READ_REMOTE_VERSION 0x001D
610typedef struct {
611 uint16_t handle;
541dc0d4 612} QEMU_PACKED read_remote_version_cp;
58a26b47
AZ		 613#define READ_REMOTE_VERSION_CP_SIZE 2
614
615#define OCF_READ_CLOCK_OFFSET 0x001F
616typedef struct {
617 uint16_t handle;
541dc0d4 618} QEMU_PACKED read_clock_offset_cp;
58a26b47
AZ		 619#define READ_CLOCK_OFFSET_CP_SIZE 2
620
621#define OCF_READ_LMP_HANDLE 0x0020
622typedef struct {
623 uint16_t handle;
541dc0d4 624} QEMU_PACKED read_lmp_handle_cp;
58a26b47
AZ		 625#define READ_LMP_HANDLE_CP_SIZE 2
626
627typedef struct {
628 uint8_t status;
629 uint16_t handle;
630 uint8_t lmp_handle;
631 uint32_t reserved;
541dc0d4 632} QEMU_PACKED read_lmp_handle_rp;
58a26b47
AZ		 633#define READ_LMP_HANDLE_RP_SIZE 8
634
635#define OCF_SETUP_SYNC_CONN 0x0028
636typedef struct {
637 uint16_t handle;
638 uint32_t tx_bandwith;
639 uint32_t rx_bandwith;
640 uint16_t max_latency;
641 uint16_t voice_setting;
642 uint8_t retrans_effort;
643 uint16_t pkt_type;
541dc0d4 644} QEMU_PACKED setup_sync_conn_cp;
58a26b47
AZ		 645#define SETUP_SYNC_CONN_CP_SIZE 17
646
647#define OCF_ACCEPT_SYNC_CONN_REQ 0x0029
648typedef struct {
c227f099 649 bdaddr_t bdaddr;
58a26b47
AZ		 650 uint32_t tx_bandwith;
651 uint32_t rx_bandwith;
652 uint16_t max_latency;
653 uint16_t voice_setting;
654 uint8_t retrans_effort;
655 uint16_t pkt_type;
541dc0d4 656} QEMU_PACKED accept_sync_conn_req_cp;
58a26b47
AZ		 657#define ACCEPT_SYNC_CONN_REQ_CP_SIZE 21
658
659#define OCF_REJECT_SYNC_CONN_REQ 0x002A
660typedef struct {
c227f099 661 bdaddr_t bdaddr;
58a26b47 662 uint8_t reason;
541dc0d4 663} QEMU_PACKED reject_sync_conn_req_cp;
58a26b47
AZ		 664#define REJECT_SYNC_CONN_REQ_CP_SIZE 7
665
666/* Link Policy */
667#define OGF_LINK_POLICY 0x02
668
669#define OCF_HOLD_MODE 0x0001
670typedef struct {
671 uint16_t handle;
672 uint16_t max_interval;
673 uint16_t min_interval;
541dc0d4 674} QEMU_PACKED hold_mode_cp;
58a26b47
AZ		 675#define HOLD_MODE_CP_SIZE 6
676
677#define OCF_SNIFF_MODE 0x0003
678typedef struct {
679 uint16_t handle;
680 uint16_t max_interval;
681 uint16_t min_interval;
682 uint16_t attempt;
683 uint16_t timeout;
541dc0d4 684} QEMU_PACKED sniff_mode_cp;
58a26b47
AZ		 685#define SNIFF_MODE_CP_SIZE 10
686
687#define OCF_EXIT_SNIFF_MODE 0x0004
688typedef struct {
689 uint16_t handle;
541dc0d4 690} QEMU_PACKED exit_sniff_mode_cp;
58a26b47
AZ		 691#define EXIT_SNIFF_MODE_CP_SIZE 2
692
693#define OCF_PARK_MODE 0x0005
694typedef struct {
695 uint16_t handle;
696 uint16_t max_interval;
697 uint16_t min_interval;
541dc0d4 698} QEMU_PACKED park_mode_cp;
58a26b47
AZ		 699#define PARK_MODE_CP_SIZE 6
700
701#define OCF_EXIT_PARK_MODE 0x0006
702typedef struct {
703 uint16_t handle;
541dc0d4 704} QEMU_PACKED exit_park_mode_cp;
58a26b47
AZ		 705#define EXIT_PARK_MODE_CP_SIZE 2
706
707#define OCF_QOS_SETUP 0x0007
708typedef struct {
709 uint8_t service_type; /* 1 = best effort */
710 uint32_t token_rate; /* Byte per seconds */
711 uint32_t peak_bandwidth; /* Byte per seconds */
712 uint32_t latency; /* Microseconds */
713 uint32_t delay_variation; /* Microseconds */
541dc0d4 714} QEMU_PACKED hci_qos;
58a26b47
AZ		 715#define HCI_QOS_CP_SIZE 17
716typedef struct {
717 uint16_t handle;
718 uint8_t flags; /* Reserved */
719 hci_qos qos;
541dc0d4 720} QEMU_PACKED qos_setup_cp;
58a26b47
AZ		 721#define QOS_SETUP_CP_SIZE (3 + HCI_QOS_CP_SIZE)
722
723#define OCF_ROLE_DISCOVERY 0x0009
724typedef struct {
725 uint16_t handle;
541dc0d4 726} QEMU_PACKED role_discovery_cp;
58a26b47
AZ		 727#define ROLE_DISCOVERY_CP_SIZE 2
728typedef struct {
729 uint8_t status;
730 uint16_t handle;
731 uint8_t role;
541dc0d4 732} QEMU_PACKED role_discovery_rp;
58a26b47
AZ		 733#define ROLE_DISCOVERY_RP_SIZE 4
734
735#define OCF_SWITCH_ROLE 0x000B
736typedef struct {
c227f099 737 bdaddr_t bdaddr;
58a26b47 738 uint8_t role;
541dc0d4 739} QEMU_PACKED switch_role_cp;
58a26b47
AZ		 740#define SWITCH_ROLE_CP_SIZE 7
741
742#define OCF_READ_LINK_POLICY 0x000C
743typedef struct {
744 uint16_t handle;
541dc0d4 745} QEMU_PACKED read_link_policy_cp;
58a26b47
AZ		 746#define READ_LINK_POLICY_CP_SIZE 2
747typedef struct {
748 uint8_t status;
749 uint16_t handle;
750 uint16_t policy;
541dc0d4 751} QEMU_PACKED read_link_policy_rp;
58a26b47
AZ		 752#define READ_LINK_POLICY_RP_SIZE 5
753
754#define OCF_WRITE_LINK_POLICY 0x000D
755typedef struct {
756 uint16_t handle;
757 uint16_t policy;
541dc0d4 758} QEMU_PACKED write_link_policy_cp;
58a26b47
AZ		 759#define WRITE_LINK_POLICY_CP_SIZE 4
760typedef struct {
761 uint8_t status;
762 uint16_t handle;
541dc0d4 763} QEMU_PACKED write_link_policy_rp;
58a26b47
AZ		 764#define WRITE_LINK_POLICY_RP_SIZE 3
765
766#define OCF_READ_DEFAULT_LINK_POLICY 0x000E
767
768#define OCF_WRITE_DEFAULT_LINK_POLICY 0x000F
769
770#define OCF_FLOW_SPECIFICATION 0x0010
771
772#define OCF_SNIFF_SUBRATE 0x0011
773typedef struct {
774 uint16_t handle;
775 uint16_t max_remote_latency;
776 uint16_t max_local_latency;
777 uint16_t min_remote_timeout;
778 uint16_t min_local_timeout;
541dc0d4 779} QEMU_PACKED sniff_subrate_cp;
58a26b47
AZ		 780#define SNIFF_SUBRATE_CP_SIZE 10
781
782/* Host Controller and Baseband */
783#define OGF_HOST_CTL 0x03
784
785#define OCF_SET_EVENT_MASK 0x0001
786typedef struct {
787 uint8_t mask[8];
541dc0d4 788} QEMU_PACKED set_event_mask_cp;
58a26b47
AZ		 789#define SET_EVENT_MASK_CP_SIZE 8
790
791#define OCF_RESET 0x0003
792
793#define OCF_SET_EVENT_FLT 0x0005
794typedef struct {
795 uint8_t flt_type;
796 uint8_t cond_type;
797 uint8_t condition[0];
541dc0d4 798} QEMU_PACKED set_event_flt_cp;
58a26b47
AZ		 799#define SET_EVENT_FLT_CP_SIZE 2
800
801enum bt_filter_type {
802 FLT_CLEAR_ALL = 0x00,
803 FLT_INQ_RESULT = 0x01,
804 FLT_CONN_SETUP = 0x02,
805};
806enum inq_result_cond_type {
807 INQ_RESULT_RETURN_ALL = 0x00,
808 INQ_RESULT_RETURN_CLASS = 0x01,
809 INQ_RESULT_RETURN_BDADDR = 0x02,
810};
811enum conn_setup_cond_type {
812 CONN_SETUP_ALLOW_ALL = 0x00,
813 CONN_SETUP_ALLOW_CLASS = 0x01,
814 CONN_SETUP_ALLOW_BDADDR = 0x02,
815};
816enum conn_setup_cond {
817 CONN_SETUP_AUTO_OFF = 0x01,
818 CONN_SETUP_AUTO_ON = 0x02,
819};
820
821#define OCF_FLUSH 0x0008
822typedef struct {
823 uint16_t handle;
541dc0d4 824} QEMU_PACKED flush_cp;
58a26b47
AZ		 825#define FLUSH_CP_SIZE 2
826
827typedef struct {
828 uint8_t status;
829 uint16_t handle;
541dc0d4 830} QEMU_PACKED flush_rp;
58a26b47
AZ		 831#define FLUSH_RP_SIZE 3
832
833#define OCF_READ_PIN_TYPE 0x0009
834typedef struct {
835 uint8_t status;
836 uint8_t pin_type;
541dc0d4 837} QEMU_PACKED read_pin_type_rp;
58a26b47
AZ		 838#define READ_PIN_TYPE_RP_SIZE 2
839
840#define OCF_WRITE_PIN_TYPE 0x000A
841typedef struct {
842 uint8_t pin_type;
541dc0d4 843} QEMU_PACKED write_pin_type_cp;
58a26b47
AZ		 844#define WRITE_PIN_TYPE_CP_SIZE 1
845
846#define OCF_CREATE_NEW_UNIT_KEY 0x000B
847
848#define OCF_READ_STORED_LINK_KEY 0x000D
849typedef struct {
c227f099 850 bdaddr_t bdaddr;
58a26b47 851 uint8_t read_all;
541dc0d4 852} QEMU_PACKED read_stored_link_key_cp;
58a26b47
AZ		 853#define READ_STORED_LINK_KEY_CP_SIZE 7
854typedef struct {
855 uint8_t status;
856 uint16_t max_keys;
857 uint16_t num_keys;
541dc0d4 858} QEMU_PACKED read_stored_link_key_rp;
58a26b47
AZ		 859#define READ_STORED_LINK_KEY_RP_SIZE 5
860
861#define OCF_WRITE_STORED_LINK_KEY 0x0011
862typedef struct {
863 uint8_t num_keys;
864 /* variable length part */
541dc0d4 865} QEMU_PACKED write_stored_link_key_cp;
58a26b47
AZ		 866#define WRITE_STORED_LINK_KEY_CP_SIZE 1
867typedef struct {
868 uint8_t status;
869 uint8_t num_keys;
541dc0d4 870} QEMU_PACKED write_stored_link_key_rp;
58a26b47
AZ		 871#define READ_WRITE_LINK_KEY_RP_SIZE 2
872
873#define OCF_DELETE_STORED_LINK_KEY 0x0012
874typedef struct {
c227f099 875 bdaddr_t bdaddr;
58a26b47 876 uint8_t delete_all;
541dc0d4 877} QEMU_PACKED delete_stored_link_key_cp;
58a26b47
AZ		 878#define DELETE_STORED_LINK_KEY_CP_SIZE 7
879typedef struct {
880 uint8_t status;
881 uint16_t num_keys;
541dc0d4 882} QEMU_PACKED delete_stored_link_key_rp;
58a26b47
AZ		 883#define DELETE_STORED_LINK_KEY_RP_SIZE 3
884
885#define OCF_CHANGE_LOCAL_NAME 0x0013
886typedef struct {
887 char name[248];
541dc0d4 888} QEMU_PACKED change_local_name_cp;
58a26b47
AZ		 889#define CHANGE_LOCAL_NAME_CP_SIZE 248
890
891#define OCF_READ_LOCAL_NAME 0x0014
892typedef struct {
893 uint8_t status;
894 char name[248];
541dc0d4 895} QEMU_PACKED read_local_name_rp;
58a26b47
AZ		 896#define READ_LOCAL_NAME_RP_SIZE 249
897
898#define OCF_READ_CONN_ACCEPT_TIMEOUT 0x0015
899typedef struct {
900 uint8_t status;
901 uint16_t timeout;
541dc0d4 902} QEMU_PACKED read_conn_accept_timeout_rp;
58a26b47
AZ		 903#define READ_CONN_ACCEPT_TIMEOUT_RP_SIZE 3
904
905#define OCF_WRITE_CONN_ACCEPT_TIMEOUT 0x0016
906typedef struct {
907 uint16_t timeout;
541dc0d4 908} QEMU_PACKED write_conn_accept_timeout_cp;
58a26b47
AZ		 909#define WRITE_CONN_ACCEPT_TIMEOUT_CP_SIZE 2
910
911#define OCF_READ_PAGE_TIMEOUT 0x0017
912typedef struct {
913 uint8_t status;
914 uint16_t timeout;
541dc0d4 915} QEMU_PACKED read_page_timeout_rp;
58a26b47
AZ		 916#define READ_PAGE_TIMEOUT_RP_SIZE 3
917
918#define OCF_WRITE_PAGE_TIMEOUT 0x0018
919typedef struct {
920 uint16_t timeout;
541dc0d4 921} QEMU_PACKED write_page_timeout_cp;
58a26b47
AZ		 922#define WRITE_PAGE_TIMEOUT_CP_SIZE 2
923
924#define OCF_READ_SCAN_ENABLE 0x0019
925typedef struct {
926 uint8_t status;
927 uint8_t enable;
541dc0d4 928} QEMU_PACKED read_scan_enable_rp;
58a26b47
AZ		 929#define READ_SCAN_ENABLE_RP_SIZE 2
930
931#define OCF_WRITE_SCAN_ENABLE 0x001A
932typedef struct {
933 uint8_t scan_enable;
541dc0d4 934} QEMU_PACKED write_scan_enable_cp;
58a26b47
AZ		 935#define WRITE_SCAN_ENABLE_CP_SIZE 1
936
937enum scan_enable_bits {
938 SCAN_DISABLED = 0,
939 SCAN_INQUIRY = 1 << 0,
940 SCAN_PAGE = 1 << 1,
941};
942
943#define OCF_READ_PAGE_ACTIVITY 0x001B
944typedef struct {
945 uint8_t status;
946 uint16_t interval;
947 uint16_t window;
541dc0d4 948} QEMU_PACKED read_page_activity_rp;
58a26b47
AZ		 949#define READ_PAGE_ACTIVITY_RP_SIZE 5
950
951#define OCF_WRITE_PAGE_ACTIVITY 0x001C
952typedef struct {
953 uint16_t interval;
954 uint16_t window;
541dc0d4 955} QEMU_PACKED write_page_activity_cp;
58a26b47
AZ		 956#define WRITE_PAGE_ACTIVITY_CP_SIZE 4
957
958#define OCF_READ_INQ_ACTIVITY 0x001D
959typedef struct {
960 uint8_t status;
961 uint16_t interval;
962 uint16_t window;
541dc0d4 963} QEMU_PACKED read_inq_activity_rp;
58a26b47
AZ		 964#define READ_INQ_ACTIVITY_RP_SIZE 5
965
966#define OCF_WRITE_INQ_ACTIVITY 0x001E
967typedef struct {
968 uint16_t interval;
969 uint16_t window;
541dc0d4 970} QEMU_PACKED write_inq_activity_cp;
58a26b47
AZ		 971#define WRITE_INQ_ACTIVITY_CP_SIZE 4
972
973#define OCF_READ_AUTH_ENABLE 0x001F
974
975#define OCF_WRITE_AUTH_ENABLE 0x0020
976
977#define AUTH_DISABLED 0x00
978#define AUTH_ENABLED 0x01
979
980#define OCF_READ_ENCRYPT_MODE 0x0021
981
982#define OCF_WRITE_ENCRYPT_MODE 0x0022
983
984#define ENCRYPT_DISABLED 0x00
985#define ENCRYPT_P2P 0x01
986#define ENCRYPT_BOTH 0x02
987
988#define OCF_READ_CLASS_OF_DEV 0x0023
989typedef struct {
990 uint8_t status;
991 uint8_t dev_class[3];
541dc0d4 992} QEMU_PACKED read_class_of_dev_rp;
58a26b47
AZ		 993#define READ_CLASS_OF_DEV_RP_SIZE 4
994
995#define OCF_WRITE_CLASS_OF_DEV 0x0024
996typedef struct {
997 uint8_t dev_class[3];
541dc0d4 998} QEMU_PACKED write_class_of_dev_cp;
58a26b47
AZ		 999#define WRITE_CLASS_OF_DEV_CP_SIZE 3
1000
1001#define OCF_READ_VOICE_SETTING 0x0025
1002typedef struct {
1003 uint8_t status;
1004 uint16_t voice_setting;
541dc0d4 1005} QEMU_PACKED read_voice_setting_rp;
58a26b47
AZ		 1006#define READ_VOICE_SETTING_RP_SIZE 3
1007
1008#define OCF_WRITE_VOICE_SETTING 0x0026
1009typedef struct {
1010 uint16_t voice_setting;
541dc0d4 1011} QEMU_PACKED write_voice_setting_cp;
58a26b47
AZ		 1012#define WRITE_VOICE_SETTING_CP_SIZE 2
1013
1014#define OCF_READ_AUTOMATIC_FLUSH_TIMEOUT 0x0027
1015
1016#define OCF_WRITE_AUTOMATIC_FLUSH_TIMEOUT 0x0028
1017
1018#define OCF_READ_NUM_BROADCAST_RETRANS 0x0029
1019
1020#define OCF_WRITE_NUM_BROADCAST_RETRANS 0x002A
1021
1022#define OCF_READ_HOLD_MODE_ACTIVITY 0x002B
1023
1024#define OCF_WRITE_HOLD_MODE_ACTIVITY 0x002C
1025
1026#define OCF_READ_TRANSMIT_POWER_LEVEL 0x002D
1027typedef struct {
1028 uint16_t handle;
1029 uint8_t type;
541dc0d4 1030} QEMU_PACKED read_transmit_power_level_cp;
58a26b47
AZ		 1031#define READ_TRANSMIT_POWER_LEVEL_CP_SIZE 3
1032typedef struct {
1033 uint8_t status;
1034 uint16_t handle;
1035 int8_t level;
541dc0d4 1036} QEMU_PACKED read_transmit_power_level_rp;
58a26b47
AZ		 1037#define READ_TRANSMIT_POWER_LEVEL_RP_SIZE 4
1038
1039#define OCF_HOST_BUFFER_SIZE 0x0033
1040typedef struct {
1041 uint16_t acl_mtu;
1042 uint8_t sco_mtu;
1043 uint16_t acl_max_pkt;
1044 uint16_t sco_max_pkt;
541dc0d4 1045} QEMU_PACKED host_buffer_size_cp;
58a26b47
AZ		 1046#define HOST_BUFFER_SIZE_CP_SIZE 7
1047
1048#define OCF_HOST_NUMBER_OF_COMPLETED_PACKETS 0x0035
1049
1050#define OCF_READ_LINK_SUPERVISION_TIMEOUT 0x0036
1051typedef struct {
1052 uint8_t status;
1053 uint16_t handle;
1054 uint16_t link_sup_to;
541dc0d4 1055} QEMU_PACKED read_link_supervision_timeout_rp;
58a26b47
AZ		 1056#define READ_LINK_SUPERVISION_TIMEOUT_RP_SIZE 5
1057
1058#define OCF_WRITE_LINK_SUPERVISION_TIMEOUT 0x0037
1059typedef struct {
1060 uint16_t handle;
1061 uint16_t link_sup_to;
541dc0d4 1062} QEMU_PACKED write_link_supervision_timeout_cp;
58a26b47
AZ		 1063#define WRITE_LINK_SUPERVISION_TIMEOUT_CP_SIZE 4
1064typedef struct {
1065 uint8_t status;
1066 uint16_t handle;
541dc0d4 1067} QEMU_PACKED write_link_supervision_timeout_rp;
58a26b47
AZ		 1068#define WRITE_LINK_SUPERVISION_TIMEOUT_RP_SIZE 3
1069
1070#define OCF_READ_NUM_SUPPORTED_IAC 0x0038
1071
1072#define MAX_IAC_LAP 0x40
1073#define OCF_READ_CURRENT_IAC_LAP 0x0039
1074typedef struct {
1075 uint8_t status;
1076 uint8_t num_current_iac;
1077 uint8_t lap[MAX_IAC_LAP][3];
541dc0d4 1078} QEMU_PACKED read_current_iac_lap_rp;
58a26b47
AZ		 1079#define READ_CURRENT_IAC_LAP_RP_SIZE 2+3*MAX_IAC_LAP
1080
1081#define OCF_WRITE_CURRENT_IAC_LAP 0x003A
1082typedef struct {
1083 uint8_t num_current_iac;
1084 uint8_t lap[MAX_IAC_LAP][3];
541dc0d4 1085} QEMU_PACKED write_current_iac_lap_cp;
58a26b47
AZ		 1086#define WRITE_CURRENT_IAC_LAP_CP_SIZE 1+3*MAX_IAC_LAP
1087
1088#define OCF_READ_PAGE_SCAN_PERIOD_MODE 0x003B
1089
1090#define OCF_WRITE_PAGE_SCAN_PERIOD_MODE 0x003C
1091
1092#define OCF_READ_PAGE_SCAN_MODE 0x003D
1093
1094#define OCF_WRITE_PAGE_SCAN_MODE 0x003E
1095
1096#define OCF_SET_AFH_CLASSIFICATION 0x003F
1097typedef struct {
1098 uint8_t map[10];
541dc0d4 1099} QEMU_PACKED set_afh_classification_cp;
58a26b47
AZ		 1100#define SET_AFH_CLASSIFICATION_CP_SIZE 10
1101typedef struct {
1102 uint8_t status;
541dc0d4 1103} QEMU_PACKED set_afh_classification_rp;
58a26b47
AZ		 1104#define SET_AFH_CLASSIFICATION_RP_SIZE 1
1105
1106#define OCF_READ_INQUIRY_SCAN_TYPE 0x0042
1107typedef struct {
1108 uint8_t status;
1109 uint8_t type;
541dc0d4 1110} QEMU_PACKED read_inquiry_scan_type_rp;
58a26b47
AZ		 1111#define READ_INQUIRY_SCAN_TYPE_RP_SIZE 2
1112
1113#define OCF_WRITE_INQUIRY_SCAN_TYPE 0x0043
1114typedef struct {
1115 uint8_t type;
541dc0d4 1116} QEMU_PACKED write_inquiry_scan_type_cp;
58a26b47
AZ		 1117#define WRITE_INQUIRY_SCAN_TYPE_CP_SIZE 1
1118typedef struct {
1119 uint8_t status;
541dc0d4 1120} QEMU_PACKED write_inquiry_scan_type_rp;
58a26b47
AZ		 1121#define WRITE_INQUIRY_SCAN_TYPE_RP_SIZE 1
1122
1123#define OCF_READ_INQUIRY_MODE 0x0044
1124typedef struct {
1125 uint8_t status;
1126 uint8_t mode;
541dc0d4 1127} QEMU_PACKED read_inquiry_mode_rp;
58a26b47
AZ		 1128#define READ_INQUIRY_MODE_RP_SIZE 2
1129
1130#define OCF_WRITE_INQUIRY_MODE 0x0045
1131typedef struct {
1132 uint8_t mode;
541dc0d4 1133} QEMU_PACKED write_inquiry_mode_cp;
58a26b47
AZ		 1134#define WRITE_INQUIRY_MODE_CP_SIZE 1
1135typedef struct {
1136 uint8_t status;
541dc0d4 1137} QEMU_PACKED write_inquiry_mode_rp;
58a26b47
AZ		 1138#define WRITE_INQUIRY_MODE_RP_SIZE 1
1139
1140#define OCF_READ_PAGE_SCAN_TYPE 0x0046
1141
1142#define OCF_WRITE_PAGE_SCAN_TYPE 0x0047
1143
1144#define OCF_READ_AFH_MODE 0x0048
1145typedef struct {
1146 uint8_t status;
1147 uint8_t mode;
541dc0d4 1148} QEMU_PACKED read_afh_mode_rp;
58a26b47
AZ		 1149#define READ_AFH_MODE_RP_SIZE 2
1150
1151#define OCF_WRITE_AFH_MODE 0x0049
1152typedef struct {
1153 uint8_t mode;
541dc0d4 1154} QEMU_PACKED write_afh_mode_cp;
58a26b47
AZ		 1155#define WRITE_AFH_MODE_CP_SIZE 1
1156typedef struct {
1157 uint8_t status;
541dc0d4 1158} QEMU_PACKED write_afh_mode_rp;
58a26b47
AZ		 1159#define WRITE_AFH_MODE_RP_SIZE 1
1160
1161#define OCF_READ_EXT_INQUIRY_RESPONSE 0x0051
1162typedef struct {
1163 uint8_t status;
1164 uint8_t fec;
1165 uint8_t data[240];
541dc0d4 1166} QEMU_PACKED read_ext_inquiry_response_rp;
58a26b47
AZ		 1167#define READ_EXT_INQUIRY_RESPONSE_RP_SIZE 242
1168
1169#define OCF_WRITE_EXT_INQUIRY_RESPONSE 0x0052
1170typedef struct {
1171 uint8_t fec;
1172 uint8_t data[240];
541dc0d4 1173} QEMU_PACKED write_ext_inquiry_response_cp;
58a26b47
AZ		 1174#define WRITE_EXT_INQUIRY_RESPONSE_CP_SIZE 241
1175typedef struct {
1176 uint8_t status;
541dc0d4 1177} QEMU_PACKED write_ext_inquiry_response_rp;
58a26b47
AZ		 1178#define WRITE_EXT_INQUIRY_RESPONSE_RP_SIZE 1
1179
1180/* Informational Parameters */
1181#define OGF_INFO_PARAM 0x04
1182
1183#define OCF_READ_LOCAL_VERSION 0x0001
1184typedef struct {
1185 uint8_t status;
1186 uint8_t hci_ver;
1187 uint16_t hci_rev;
1188 uint8_t lmp_ver;
1189 uint16_t manufacturer;
1190 uint16_t lmp_subver;
541dc0d4 1191} QEMU_PACKED read_local_version_rp;
58a26b47
AZ		 1192#define READ_LOCAL_VERSION_RP_SIZE 9
1193
1194#define OCF_READ_LOCAL_COMMANDS 0x0002
1195typedef struct {
1196 uint8_t status;
1197 uint8_t commands[64];
541dc0d4 1198} QEMU_PACKED read_local_commands_rp;
58a26b47
AZ		 1199#define READ_LOCAL_COMMANDS_RP_SIZE 65
1200
1201#define OCF_READ_LOCAL_FEATURES 0x0003
1202typedef struct {
1203 uint8_t status;
1204 uint8_t features[8];
541dc0d4 1205} QEMU_PACKED read_local_features_rp;
58a26b47
AZ		 1206#define READ_LOCAL_FEATURES_RP_SIZE 9
1207
1208#define OCF_READ_LOCAL_EXT_FEATURES 0x0004
1209typedef struct {
1210 uint8_t page_num;
541dc0d4 1211} QEMU_PACKED read_local_ext_features_cp;
58a26b47
AZ		 1212#define READ_LOCAL_EXT_FEATURES_CP_SIZE 1
1213typedef struct {
1214 uint8_t status;
1215 uint8_t page_num;
1216 uint8_t max_page_num;
1217 uint8_t features[8];
541dc0d4 1218} QEMU_PACKED read_local_ext_features_rp;
58a26b47
AZ		 1219#define READ_LOCAL_EXT_FEATURES_RP_SIZE 11
1220
1221#define OCF_READ_BUFFER_SIZE 0x0005
1222typedef struct {
1223 uint8_t status;
1224 uint16_t acl_mtu;
1225 uint8_t sco_mtu;
1226 uint16_t acl_max_pkt;
1227 uint16_t sco_max_pkt;
541dc0d4 1228} QEMU_PACKED read_buffer_size_rp;
58a26b47
AZ		 1229#define READ_BUFFER_SIZE_RP_SIZE 8
1230
1231#define OCF_READ_COUNTRY_CODE 0x0007
1232typedef struct {
1233 uint8_t status;
1234 uint8_t country_code;
541dc0d4 1235} QEMU_PACKED read_country_code_rp;
58a26b47
AZ		 1236#define READ_COUNTRY_CODE_RP_SIZE 2
1237
1238#define OCF_READ_BD_ADDR 0x0009
1239typedef struct {
1240 uint8_t status;
c227f099 1241 bdaddr_t bdaddr;
541dc0d4 1242} QEMU_PACKED read_bd_addr_rp;
58a26b47
AZ		 1243#define READ_BD_ADDR_RP_SIZE 7
1244
1245/* Status params */
1246#define OGF_STATUS_PARAM 0x05
1247
1248#define OCF_READ_FAILED_CONTACT_COUNTER 0x0001
1249typedef struct {
1250 uint8_t status;
1251 uint16_t handle;
1252 uint8_t counter;
541dc0d4 1253} QEMU_PACKED read_failed_contact_counter_rp;
58a26b47
AZ		 1254#define READ_FAILED_CONTACT_COUNTER_RP_SIZE 4
1255
1256#define OCF_RESET_FAILED_CONTACT_COUNTER 0x0002
1257typedef struct {
1258 uint8_t status;
1259 uint16_t handle;
541dc0d4 1260} QEMU_PACKED reset_failed_contact_counter_rp;
58a26b47
AZ		 1261#define RESET_FAILED_CONTACT_COUNTER_RP_SIZE 4
1262
1263#define OCF_READ_LINK_QUALITY 0x0003
1264typedef struct {
1265 uint16_t handle;
541dc0d4 1266} QEMU_PACKED read_link_quality_cp;
58a26b47
AZ		 1267#define READ_LINK_QUALITY_CP_SIZE 4
1268
1269typedef struct {
1270 uint8_t status;
1271 uint16_t handle;
1272 uint8_t link_quality;
541dc0d4 1273} QEMU_PACKED read_link_quality_rp;
58a26b47
AZ		 1274#define READ_LINK_QUALITY_RP_SIZE 4
1275
1276#define OCF_READ_RSSI 0x0005
1277typedef struct {
1278 uint8_t status;
1279 uint16_t handle;
1280 int8_t rssi;
541dc0d4 1281} QEMU_PACKED read_rssi_rp;
58a26b47
AZ		 1282#define READ_RSSI_RP_SIZE 4
1283
1284#define OCF_READ_AFH_MAP 0x0006
1285typedef struct {
1286 uint8_t status;
1287 uint16_t handle;
1288 uint8_t mode;
1289 uint8_t map[10];
541dc0d4 1290} QEMU_PACKED read_afh_map_rp;
58a26b47
AZ		 1291#define READ_AFH_MAP_RP_SIZE 14
1292
1293#define OCF_READ_CLOCK 0x0007
1294typedef struct {
1295 uint16_t handle;
1296 uint8_t which_clock;
541dc0d4 1297} QEMU_PACKED read_clock_cp;
58a26b47
AZ		 1298#define READ_CLOCK_CP_SIZE 3
1299typedef struct {
1300 uint8_t status;
1301 uint16_t handle;
1302 uint32_t clock;
1303 uint16_t accuracy;
541dc0d4 1304} QEMU_PACKED read_clock_rp;
58a26b47
AZ		 1305#define READ_CLOCK_RP_SIZE 9
1306
1307/* Testing commands */
1308#define OGF_TESTING_CMD 0x3e
1309
1310/* Vendor specific commands */
1311#define OGF_VENDOR_CMD 0x3f
1312
1313/* HCI Events */
1314
1315#define EVT_INQUIRY_COMPLETE 0x01
1316
1317#define EVT_INQUIRY_RESULT 0x02
1318typedef struct {
1319 uint8_t num_responses;
c227f099 1320 bdaddr_t bdaddr;
58a26b47
AZ		 1321 uint8_t pscan_rep_mode;
1322 uint8_t pscan_period_mode;
1323 uint8_t pscan_mode;
1324 uint8_t dev_class[3];
1325 uint16_t clock_offset;
541dc0d4 1326} QEMU_PACKED inquiry_info;
58a26b47
AZ		 1327#define INQUIRY_INFO_SIZE 14
1328
1329#define EVT_CONN_COMPLETE 0x03
1330typedef struct {
1331 uint8_t status;
1332 uint16_t handle;
c227f099 1333 bdaddr_t bdaddr;
58a26b47
AZ		 1334 uint8_t link_type;
1335 uint8_t encr_mode;
541dc0d4 1336} QEMU_PACKED evt_conn_complete;
58a26b47
AZ		 1337#define EVT_CONN_COMPLETE_SIZE 11
1338
1339#define EVT_CONN_REQUEST 0x04
1340typedef struct {
c227f099 1341 bdaddr_t bdaddr;
58a26b47
AZ		 1342 uint8_t dev_class[3];
1343 uint8_t link_type;
541dc0d4 1344} QEMU_PACKED evt_conn_request;
58a26b47
AZ		 1345#define EVT_CONN_REQUEST_SIZE 10
1346
1347#define EVT_DISCONN_COMPLETE 0x05
1348typedef struct {
1349 uint8_t status;
1350 uint16_t handle;
1351 uint8_t reason;
541dc0d4 1352} QEMU_PACKED evt_disconn_complete;
58a26b47
AZ		 1353#define EVT_DISCONN_COMPLETE_SIZE 4
1354
1355#define EVT_AUTH_COMPLETE 0x06
1356typedef struct {
1357 uint8_t status;
1358 uint16_t handle;
541dc0d4 1359} QEMU_PACKED evt_auth_complete;
58a26b47
AZ		 1360#define EVT_AUTH_COMPLETE_SIZE 3
1361
1362#define EVT_REMOTE_NAME_REQ_COMPLETE 0x07
1363typedef struct {
1364 uint8_t status;
c227f099 1365 bdaddr_t bdaddr;
58a26b47 1366 char name[248];
541dc0d4 1367} QEMU_PACKED evt_remote_name_req_complete;
58a26b47
AZ		 1368#define EVT_REMOTE_NAME_REQ_COMPLETE_SIZE 255
1369
1370#define EVT_ENCRYPT_CHANGE 0x08
1371typedef struct {
1372 uint8_t status;
1373 uint16_t handle;
1374 uint8_t encrypt;
541dc0d4 1375} QEMU_PACKED evt_encrypt_change;
58a26b47
AZ		 1376#define EVT_ENCRYPT_CHANGE_SIZE 5
1377
1378#define EVT_CHANGE_CONN_LINK_KEY_COMPLETE 0x09
1379typedef struct {
1380 uint8_t status;
1381 uint16_t handle;
541dc0d4 1382} QEMU_PACKED evt_change_conn_link_key_complete;
58a26b47
AZ		 1383#define EVT_CHANGE_CONN_LINK_KEY_COMPLETE_SIZE 3
1384
1385#define EVT_MASTER_LINK_KEY_COMPLETE 0x0A
1386typedef struct {
1387 uint8_t status;
1388 uint16_t handle;
1389 uint8_t key_flag;
541dc0d4 1390} QEMU_PACKED evt_master_link_key_complete;
58a26b47
AZ		 1391#define EVT_MASTER_LINK_KEY_COMPLETE_SIZE 4
1392
1393#define EVT_READ_REMOTE_FEATURES_COMPLETE 0x0B
1394typedef struct {
1395 uint8_t status;
1396 uint16_t handle;
1397 uint8_t features[8];
541dc0d4 1398} QEMU_PACKED evt_read_remote_features_complete;
58a26b47
AZ		 1399#define EVT_READ_REMOTE_FEATURES_COMPLETE_SIZE 11
1400
1401#define EVT_READ_REMOTE_VERSION_COMPLETE 0x0C
1402typedef struct {
1403 uint8_t status;
1404 uint16_t handle;
1405 uint8_t lmp_ver;
1406 uint16_t manufacturer;
1407 uint16_t lmp_subver;
541dc0d4 1408} QEMU_PACKED evt_read_remote_version_complete;
58a26b47
AZ		 1409#define EVT_READ_REMOTE_VERSION_COMPLETE_SIZE 8
1410
1411#define EVT_QOS_SETUP_COMPLETE 0x0D
1412typedef struct {
1413 uint8_t status;
1414 uint16_t handle;
1415 uint8_t flags; /* Reserved */
1416 hci_qos qos;
541dc0d4 1417} QEMU_PACKED evt_qos_setup_complete;
58a26b47
AZ		 1418#define EVT_QOS_SETUP_COMPLETE_SIZE (4 + HCI_QOS_CP_SIZE)
1419
1420#define EVT_CMD_COMPLETE 0x0E
1421typedef struct {
1422 uint8_t ncmd;
1423 uint16_t opcode;
541dc0d4 1424} QEMU_PACKED evt_cmd_complete;
58a26b47
AZ		 1425#define EVT_CMD_COMPLETE_SIZE 3
1426
1427#define EVT_CMD_STATUS 0x0F
1428typedef struct {
1429 uint8_t status;
1430 uint8_t ncmd;
1431 uint16_t opcode;
541dc0d4 1432} QEMU_PACKED evt_cmd_status;
58a26b47
AZ		 1433#define EVT_CMD_STATUS_SIZE 4
1434
1435#define EVT_HARDWARE_ERROR 0x10
1436typedef struct {
1437 uint8_t code;
541dc0d4 1438} QEMU_PACKED evt_hardware_error;
58a26b47
AZ		 1439#define EVT_HARDWARE_ERROR_SIZE 1
1440
1441#define EVT_FLUSH_OCCURRED 0x11
1442typedef struct {
1443 uint16_t handle;
541dc0d4 1444} QEMU_PACKED evt_flush_occurred;
58a26b47
AZ		 1445#define EVT_FLUSH_OCCURRED_SIZE 2
1446
1447#define EVT_ROLE_CHANGE 0x12
1448typedef struct {
1449 uint8_t status;
c227f099 1450 bdaddr_t bdaddr;
58a26b47 1451 uint8_t role;
541dc0d4 1452} QEMU_PACKED evt_role_change;
58a26b47
AZ		 1453#define EVT_ROLE_CHANGE_SIZE 8
1454
1455#define EVT_NUM_COMP_PKTS 0x13
1456typedef struct {
1457 uint8_t num_hndl;
1458 struct {
1459 uint16_t handle;
1460 uint16_t num_packets;
1461 } connection[0];
541dc0d4 1462} QEMU_PACKED evt_num_comp_pkts;
58a26b47
AZ		 1463#define EVT_NUM_COMP_PKTS_SIZE(num_hndl) (1 + 4 * (num_hndl))
1464
1465#define EVT_MODE_CHANGE 0x14
1466typedef struct {
1467 uint8_t status;
1468 uint16_t handle;
1469 uint8_t mode;
1470 uint16_t interval;
541dc0d4 1471} QEMU_PACKED evt_mode_change;
58a26b47
AZ		 1472#define EVT_MODE_CHANGE_SIZE 6
1473
1474#define EVT_RETURN_LINK_KEYS 0x15
1475typedef struct {
1476 uint8_t num_keys;
1477 /* variable length part */
541dc0d4 1478} QEMU_PACKED evt_return_link_keys;
58a26b47
AZ		 1479#define EVT_RETURN_LINK_KEYS_SIZE 1
1480
1481#define EVT_PIN_CODE_REQ 0x16
1482typedef struct {
c227f099 1483 bdaddr_t bdaddr;
541dc0d4 1484} QEMU_PACKED evt_pin_code_req;
58a26b47
AZ		 1485#define EVT_PIN_CODE_REQ_SIZE 6
1486
1487#define EVT_LINK_KEY_REQ 0x17
1488typedef struct {
c227f099 1489 bdaddr_t bdaddr;
541dc0d4 1490} QEMU_PACKED evt_link_key_req;
58a26b47
AZ		 1491#define EVT_LINK_KEY_REQ_SIZE 6
1492
1493#define EVT_LINK_KEY_NOTIFY 0x18
1494typedef struct {
c227f099 1495 bdaddr_t bdaddr;
58a26b47
AZ		 1496 uint8_t link_key[16];
1497 uint8_t key_type;
541dc0d4 1498} QEMU_PACKED evt_link_key_notify;
58a26b47
AZ		 1499#define EVT_LINK_KEY_NOTIFY_SIZE 23
1500
1501#define EVT_LOOPBACK_COMMAND 0x19
1502
1503#define EVT_DATA_BUFFER_OVERFLOW 0x1A
1504typedef struct {
1505 uint8_t link_type;
541dc0d4 1506} QEMU_PACKED evt_data_buffer_overflow;
58a26b47
AZ		 1507#define EVT_DATA_BUFFER_OVERFLOW_SIZE 1
1508
1509#define EVT_MAX_SLOTS_CHANGE 0x1B
1510typedef struct {
1511 uint16_t handle;
1512 uint8_t max_slots;
541dc0d4 1513} QEMU_PACKED evt_max_slots_change;
58a26b47
AZ		 1514#define EVT_MAX_SLOTS_CHANGE_SIZE 3
1515
1516#define EVT_READ_CLOCK_OFFSET_COMPLETE 0x1C
1517typedef struct {
1518 uint8_t status;
1519 uint16_t handle;
1520 uint16_t clock_offset;
541dc0d4 1521} QEMU_PACKED evt_read_clock_offset_complete;
58a26b47
AZ		 1522#define EVT_READ_CLOCK_OFFSET_COMPLETE_SIZE 5
1523
1524#define EVT_CONN_PTYPE_CHANGED 0x1D
1525typedef struct {
1526 uint8_t status;
1527 uint16_t handle;
1528 uint16_t ptype;
541dc0d4 1529} QEMU_PACKED evt_conn_ptype_changed;
58a26b47
AZ		 1530#define EVT_CONN_PTYPE_CHANGED_SIZE 5
1531
1532#define EVT_QOS_VIOLATION 0x1E
1533typedef struct {
1534 uint16_t handle;
541dc0d4 1535} QEMU_PACKED evt_qos_violation;
58a26b47
AZ		 1536#define EVT_QOS_VIOLATION_SIZE 2
1537
1538#define EVT_PSCAN_REP_MODE_CHANGE 0x20
1539typedef struct {
c227f099 1540 bdaddr_t bdaddr;
58a26b47 1541 uint8_t pscan_rep_mode;
541dc0d4 1542} QEMU_PACKED evt_pscan_rep_mode_change;
58a26b47
AZ		 1543#define EVT_PSCAN_REP_MODE_CHANGE_SIZE 7
1544
1545#define EVT_FLOW_SPEC_COMPLETE 0x21
1546typedef struct {
1547 uint8_t status;
1548 uint16_t handle;
1549 uint8_t flags;
1550 uint8_t direction;
1551 hci_qos qos;
541dc0d4 1552} QEMU_PACKED evt_flow_spec_complete;
58a26b47
AZ		 1553#define EVT_FLOW_SPEC_COMPLETE_SIZE (5 + HCI_QOS_CP_SIZE)
1554
1555#define EVT_INQUIRY_RESULT_WITH_RSSI 0x22
1556typedef struct {
1557 uint8_t num_responses;
c227f099 1558 bdaddr_t bdaddr;
58a26b47
AZ		 1559 uint8_t pscan_rep_mode;
1560 uint8_t pscan_period_mode;
1561 uint8_t dev_class[3];
1562 uint16_t clock_offset;
1563 int8_t rssi;
541dc0d4 1564} QEMU_PACKED inquiry_info_with_rssi;
58a26b47
AZ		 1565#define INQUIRY_INFO_WITH_RSSI_SIZE 15
1566typedef struct {
1567 uint8_t num_responses;
c227f099 1568 bdaddr_t bdaddr;
58a26b47
AZ		 1569 uint8_t pscan_rep_mode;
1570 uint8_t pscan_period_mode;
1571 uint8_t pscan_mode;
1572 uint8_t dev_class[3];
1573 uint16_t clock_offset;
1574 int8_t rssi;
541dc0d4 1575} QEMU_PACKED inquiry_info_with_rssi_and_pscan_mode;
58a26b47
AZ		 1576#define INQUIRY_INFO_WITH_RSSI_AND_PSCAN_MODE_SIZE 16
1577
1578#define EVT_READ_REMOTE_EXT_FEATURES_COMPLETE 0x23
1579typedef struct {
1580 uint8_t status;
1581 uint16_t handle;
1582 uint8_t page_num;
1583 uint8_t max_page_num;
1584 uint8_t features[8];
541dc0d4 1585} QEMU_PACKED evt_read_remote_ext_features_complete;
58a26b47
AZ		 1586#define EVT_READ_REMOTE_EXT_FEATURES_COMPLETE_SIZE 13
1587
1588#define EVT_SYNC_CONN_COMPLETE 0x2C
1589typedef struct {
1590 uint8_t status;
1591 uint16_t handle;
c227f099 1592 bdaddr_t bdaddr;
58a26b47
AZ		 1593 uint8_t link_type;
1594 uint8_t trans_interval;
1595 uint8_t retrans_window;
1596 uint16_t rx_pkt_len;
1597 uint16_t tx_pkt_len;
1598 uint8_t air_mode;
541dc0d4 1599} QEMU_PACKED evt_sync_conn_complete;
58a26b47
AZ		 1600#define EVT_SYNC_CONN_COMPLETE_SIZE 17
1601
1602#define EVT_SYNC_CONN_CHANGED 0x2D
1603typedef struct {
1604 uint8_t status;
1605 uint16_t handle;
1606 uint8_t trans_interval;
1607 uint8_t retrans_window;
1608 uint16_t rx_pkt_len;
1609 uint16_t tx_pkt_len;
541dc0d4 1610} QEMU_PACKED evt_sync_conn_changed;
58a26b47
AZ		 1611#define EVT_SYNC_CONN_CHANGED_SIZE 9
1612
1613#define EVT_SNIFF_SUBRATE 0x2E
1614typedef struct {
1615 uint8_t status;
1616 uint16_t handle;
1617 uint16_t max_remote_latency;
1618 uint16_t max_local_latency;
1619 uint16_t min_remote_timeout;
1620 uint16_t min_local_timeout;
541dc0d4 1621} QEMU_PACKED evt_sniff_subrate;
58a26b47
AZ		 1622#define EVT_SNIFF_SUBRATE_SIZE 11
1623
1624#define EVT_EXTENDED_INQUIRY_RESULT 0x2F
1625typedef struct {
c227f099 1626 bdaddr_t bdaddr;
58a26b47
AZ		 1627 uint8_t pscan_rep_mode;
1628 uint8_t pscan_period_mode;
1629 uint8_t dev_class[3];
1630 uint16_t clock_offset;
1631 int8_t rssi;
1632 uint8_t data[240];
541dc0d4 1633} QEMU_PACKED extended_inquiry_info;
58a26b47
AZ		 1634#define EXTENDED_INQUIRY_INFO_SIZE 254
1635
1636#define EVT_TESTING 0xFE
1637
1638#define EVT_VENDOR 0xFF
1639
1640/* Command opcode pack/unpack */
1641#define cmd_opcode_pack(ogf, ocf) (uint16_t)((ocf & 0x03ff)|(ogf << 10))
1642#define cmd_opcode_ogf(op) (op >> 10)
1643#define cmd_opcode_ocf(op) (op & 0x03ff)
1644
1645/* ACL handle and flags pack/unpack */
1646#define acl_handle_pack(h, f) (uint16_t)(((h) & 0x0fff)|((f) << 12))
1647#define acl_handle(h) ((h) & 0x0fff)
1648#define acl_flags(h) ((h) >> 12)
1649
1650/* HCI Packet structures */
1651#define HCI_COMMAND_HDR_SIZE 3
1652#define HCI_EVENT_HDR_SIZE 2
1653#define HCI_ACL_HDR_SIZE 4
1654#define HCI_SCO_HDR_SIZE 3
1655
1656struct hci_command_hdr {
1657 uint16_t opcode; /* OCF & OGF */
1658 uint8_t plen;
541dc0d4 1659} QEMU_PACKED;
58a26b47
AZ		 1660
1661struct hci_event_hdr {
1662 uint8_t evt;
1663 uint8_t plen;
541dc0d4 1664} QEMU_PACKED;
58a26b47
AZ		 1665
1666struct hci_acl_hdr {
1667 uint16_t handle; /* Handle & Flags(PB, BC) */
1668 uint16_t dlen;
541dc0d4 1669} QEMU_PACKED;
58a26b47
AZ		 1670
1671struct hci_sco_hdr {
1672 uint16_t handle;
1673 uint8_t dlen;
541dc0d4 1674} QEMU_PACKED;
4d2d181c
AZ		 1675
1676/* L2CAP layer defines */
1677
1678enum bt_l2cap_lm_bits {
1679 L2CAP_LM_MASTER = 1 << 0,
1680 L2CAP_LM_AUTH = 1 << 1,
1681 L2CAP_LM_ENCRYPT = 1 << 2,
1682 L2CAP_LM_TRUSTED = 1 << 3,
1683 L2CAP_LM_RELIABLE = 1 << 4,
1684 L2CAP_LM_SECURE = 1 << 5,
1685};
1686
1687enum bt_l2cap_cid_predef {
1688 L2CAP_CID_INVALID = 0x0000,
1689 L2CAP_CID_SIGNALLING= 0x0001,
1690 L2CAP_CID_GROUP = 0x0002,
1691 L2CAP_CID_ALLOC = 0x0040,
1692};
1693
1694/* L2CAP command codes */
1695enum bt_l2cap_cmd {
1696 L2CAP_COMMAND_REJ = 1,
1697 L2CAP_CONN_REQ,
1698 L2CAP_CONN_RSP,
1699 L2CAP_CONF_REQ,
1700 L2CAP_CONF_RSP,
1701 L2CAP_DISCONN_REQ,
1702 L2CAP_DISCONN_RSP,
1703 L2CAP_ECHO_REQ,
1704 L2CAP_ECHO_RSP,
1705 L2CAP_INFO_REQ,
1706 L2CAP_INFO_RSP,
1707};
1708
1709enum bt_l2cap_sar_bits {
1710 L2CAP_SAR_NO_SEG = 0,
1711 L2CAP_SAR_START,
1712 L2CAP_SAR_END,
1713 L2CAP_SAR_CONT,
1714};
1715
1716/* L2CAP structures */
1717typedef struct {
1718 uint16_t len;
1719 uint16_t cid;
1720 uint8_t data[0];
541dc0d4 1721} QEMU_PACKED l2cap_hdr;
4d2d181c
AZ		 1722#define L2CAP_HDR_SIZE 4
1723
1724typedef struct {
1725 uint8_t code;
1726 uint8_t ident;
1727 uint16_t len;
541dc0d4 1728} QEMU_PACKED l2cap_cmd_hdr;
4d2d181c
AZ		 1729#define L2CAP_CMD_HDR_SIZE 4
1730
1731typedef struct {
1732 uint16_t reason;
541dc0d4 1733} QEMU_PACKED l2cap_cmd_rej;
4d2d181c
AZ		 1734#define L2CAP_CMD_REJ_SIZE 2
1735
1736typedef struct {
1737 uint16_t dcid;
1738 uint16_t scid;
541dc0d4 1739} QEMU_PACKED l2cap_cmd_rej_cid;
4d2d181c
AZ		 1740#define L2CAP_CMD_REJ_CID_SIZE 4
1741
1742/* reject reason */
1743enum bt_l2cap_rej_reason {
1744 L2CAP_REJ_CMD_NOT_UNDERSTOOD = 0,
1745 L2CAP_REJ_SIG_TOOBIG,
1746 L2CAP_REJ_CID_INVAL,
1747};
1748
1749typedef struct {
1750 uint16_t psm;
1751 uint16_t scid;
541dc0d4 1752} QEMU_PACKED l2cap_conn_req;
4d2d181c
AZ		 1753#define L2CAP_CONN_REQ_SIZE 4
1754
1755typedef struct {
1756 uint16_t dcid;
1757 uint16_t scid;
1758 uint16_t result;
1759 uint16_t status;
541dc0d4 1760} QEMU_PACKED l2cap_conn_rsp;
4d2d181c
AZ		 1761#define L2CAP_CONN_RSP_SIZE 8
1762
1763/* connect result */
1764enum bt_l2cap_conn_res {
1765 L2CAP_CR_SUCCESS = 0,
1766 L2CAP_CR_PEND,
1767 L2CAP_CR_BAD_PSM,
1768 L2CAP_CR_SEC_BLOCK,
1769 L2CAP_CR_NO_MEM,
1770};
1771
1772/* connect status */
1773enum bt_l2cap_conn_stat {
1774 L2CAP_CS_NO_INFO = 0,
1775 L2CAP_CS_AUTHEN_PEND,
1776 L2CAP_CS_AUTHOR_PEND,
1777};
1778
1779typedef struct {
1780 uint16_t dcid;
1781 uint16_t flags;
1782 uint8_t data[0];
541dc0d4 1783} QEMU_PACKED l2cap_conf_req;
4d2d181c
AZ		 1784#define L2CAP_CONF_REQ_SIZE(datalen) (4 + (datalen))
1785
1786typedef struct {
1787 uint16_t scid;
1788 uint16_t flags;
1789 uint16_t result;
1790 uint8_t data[0];
541dc0d4 1791} QEMU_PACKED l2cap_conf_rsp;
4d2d181c
AZ		 1792#define L2CAP_CONF_RSP_SIZE(datalen) (6 + datalen)
1793
1794enum bt_l2cap_conf_res {
1795 L2CAP_CONF_SUCCESS = 0,
1796 L2CAP_CONF_UNACCEPT,
1797 L2CAP_CONF_REJECT,
1798 L2CAP_CONF_UNKNOWN,
1799};
1800
1801typedef struct {
1802 uint8_t type;
1803 uint8_t len;
1804 uint8_t val[0];
541dc0d4 1805} QEMU_PACKED l2cap_conf_opt;
4d2d181c
AZ		 1806#define L2CAP_CONF_OPT_SIZE 2
1807
1808enum bt_l2cap_conf_val {
1809 L2CAP_CONF_MTU = 1,
1810 L2CAP_CONF_FLUSH_TO,
1811 L2CAP_CONF_QOS,
1812 L2CAP_CONF_RFC,
1813 L2CAP_CONF_RFC_MODE = L2CAP_CONF_RFC,
1814};
1815
1816typedef struct {
1817 uint8_t flags;
1818 uint8_t service_type;
1819 uint32_t token_rate;
1820 uint32_t token_bucket_size;
1821 uint32_t peak_bandwidth;
1822 uint32_t latency;
1823 uint32_t delay_variation;
541dc0d4 1824} QEMU_PACKED l2cap_conf_opt_qos;
4d2d181c
AZ		 1825#define L2CAP_CONF_OPT_QOS_SIZE 22
1826
1827enum bt_l2cap_conf_opt_qos_st {
1828 L2CAP_CONF_QOS_NO_TRAFFIC = 0x00,
1829 L2CAP_CONF_QOS_BEST_EFFORT,
1830 L2CAP_CONF_QOS_GUARANTEED,
1831};
1832
1833#define L2CAP_CONF_QOS_WILDCARD 0xffffffff
1834
1835enum bt_l2cap_mode {
1836 L2CAP_MODE_BASIC = 0,
1837 L2CAP_MODE_RETRANS = 1,
1838 L2CAP_MODE_FLOWCTL = 2,
1839};
1840
1841typedef struct {
1842 uint16_t dcid;
1843 uint16_t scid;
541dc0d4 1844} QEMU_PACKED l2cap_disconn_req;
4d2d181c
AZ		 1845#define L2CAP_DISCONN_REQ_SIZE 4
1846
1847typedef struct {
1848 uint16_t dcid;
1849 uint16_t scid;
541dc0d4 1850} QEMU_PACKED l2cap_disconn_rsp;
4d2d181c
AZ		 1851#define L2CAP_DISCONN_RSP_SIZE 4
1852
1853typedef struct {
1854 uint16_t type;
541dc0d4 1855} QEMU_PACKED l2cap_info_req;
4d2d181c
AZ		 1856#define L2CAP_INFO_REQ_SIZE 2
1857
1858typedef struct {
1859 uint16_t type;
1860 uint16_t result;
1861 uint8_t data[0];
541dc0d4 1862} QEMU_PACKED l2cap_info_rsp;
4d2d181c
AZ		 1863#define L2CAP_INFO_RSP_SIZE 4
1864
1865/* info type */
1866enum bt_l2cap_info_type {
1867 L2CAP_IT_CL_MTU = 1,
1868 L2CAP_IT_FEAT_MASK,
1869};
1870
1871/* info result */
1872enum bt_l2cap_info_result {
1873 L2CAP_IR_SUCCESS = 0,
1874 L2CAP_IR_NOTSUPP,
1875};
1876
1877/* Service Discovery Protocol defines */
1878/* Note that all multibyte values in lower layer protocols (above in this file)
1879 * are little-endian while SDP is big-endian. */
1880
1881/* Protocol UUIDs */
1882enum sdp_proto_uuid {
1883 SDP_UUID = 0x0001,
1884 UDP_UUID = 0x0002,
1885 RFCOMM_UUID = 0x0003,
1886 TCP_UUID = 0x0004,
1887 TCS_BIN_UUID = 0x0005,
1888 TCS_AT_UUID = 0x0006,
1889 OBEX_UUID = 0x0008,
1890 IP_UUID = 0x0009,
1891 FTP_UUID = 0x000a,
1892 HTTP_UUID = 0x000c,
1893 WSP_UUID = 0x000e,
1894 BNEP_UUID = 0x000f,
1895 UPNP_UUID = 0x0010,
1896 HIDP_UUID = 0x0011,
1897 HCRP_CTRL_UUID = 0x0012,
1898 HCRP_DATA_UUID = 0x0014,
1899 HCRP_NOTE_UUID = 0x0016,
1900 AVCTP_UUID = 0x0017,
1901 AVDTP_UUID = 0x0019,
1902 CMTP_UUID = 0x001b,
1903 UDI_UUID = 0x001d,
1904 MCAP_CTRL_UUID = 0x001e,
1905 MCAP_DATA_UUID = 0x001f,
1906 L2CAP_UUID = 0x0100,
1907};
1908
1909/*
1910 * Service class identifiers of standard services and service groups
1911 */
1912enum service_class_id {
1913 SDP_SERVER_SVCLASS_ID = 0x1000,
1914 BROWSE_GRP_DESC_SVCLASS_ID = 0x1001,
1915 PUBLIC_BROWSE_GROUP = 0x1002,
1916 SERIAL_PORT_SVCLASS_ID = 0x1101,
1917 LAN_ACCESS_SVCLASS_ID = 0x1102,
1918 DIALUP_NET_SVCLASS_ID = 0x1103,
1919 IRMC_SYNC_SVCLASS_ID = 0x1104,
1920 OBEX_OBJPUSH_SVCLASS_ID = 0x1105,
1921 OBEX_FILETRANS_SVCLASS_ID = 0x1106,
1922 IRMC_SYNC_CMD_SVCLASS_ID = 0x1107,
1923 HEADSET_SVCLASS_ID = 0x1108,
1924 CORDLESS_TELEPHONY_SVCLASS_ID = 0x1109,
1925 AUDIO_SOURCE_SVCLASS_ID = 0x110a,
1926 AUDIO_SINK_SVCLASS_ID = 0x110b,
1927 AV_REMOTE_TARGET_SVCLASS_ID = 0x110c,
1928 ADVANCED_AUDIO_SVCLASS_ID = 0x110d,
1929 AV_REMOTE_SVCLASS_ID = 0x110e,
1930 VIDEO_CONF_SVCLASS_ID = 0x110f,
1931 INTERCOM_SVCLASS_ID = 0x1110,
1932 FAX_SVCLASS_ID = 0x1111,
1933 HEADSET_AGW_SVCLASS_ID = 0x1112,
1934 WAP_SVCLASS_ID = 0x1113,
1935 WAP_CLIENT_SVCLASS_ID = 0x1114,
1936 PANU_SVCLASS_ID = 0x1115,
1937 NAP_SVCLASS_ID = 0x1116,
1938 GN_SVCLASS_ID = 0x1117,
1939 DIRECT_PRINTING_SVCLASS_ID = 0x1118,
1940 REFERENCE_PRINTING_SVCLASS_ID = 0x1119,
1941 IMAGING_SVCLASS_ID = 0x111a,
1942 IMAGING_RESPONDER_SVCLASS_ID = 0x111b,
1943 IMAGING_ARCHIVE_SVCLASS_ID = 0x111c,
1944 IMAGING_REFOBJS_SVCLASS_ID = 0x111d,
1945 HANDSFREE_SVCLASS_ID = 0x111e,
1946 HANDSFREE_AGW_SVCLASS_ID = 0x111f,
1947 DIRECT_PRT_REFOBJS_SVCLASS_ID = 0x1120,
1948 REFLECTED_UI_SVCLASS_ID = 0x1121,
1949 BASIC_PRINTING_SVCLASS_ID = 0x1122,
1950 PRINTING_STATUS_SVCLASS_ID = 0x1123,
1951 HID_SVCLASS_ID = 0x1124,
1952 HCR_SVCLASS_ID = 0x1125,
1953 HCR_PRINT_SVCLASS_ID = 0x1126,
1954 HCR_SCAN_SVCLASS_ID = 0x1127,
1955 CIP_SVCLASS_ID = 0x1128,
1956 VIDEO_CONF_GW_SVCLASS_ID = 0x1129,
1957 UDI_MT_SVCLASS_ID = 0x112a,
1958 UDI_TA_SVCLASS_ID = 0x112b,
1959 AV_SVCLASS_ID = 0x112c,
1960 SAP_SVCLASS_ID = 0x112d,
1961 PBAP_PCE_SVCLASS_ID = 0x112e,
1962 PBAP_PSE_SVCLASS_ID = 0x112f,
1963 PBAP_SVCLASS_ID = 0x1130,
1964 PNP_INFO_SVCLASS_ID = 0x1200,
1965 GENERIC_NETWORKING_SVCLASS_ID = 0x1201,
1966 GENERIC_FILETRANS_SVCLASS_ID = 0x1202,
1967 GENERIC_AUDIO_SVCLASS_ID = 0x1203,
1968 GENERIC_TELEPHONY_SVCLASS_ID = 0x1204,
1969 UPNP_SVCLASS_ID = 0x1205,
1970 UPNP_IP_SVCLASS_ID = 0x1206,
1971 UPNP_PAN_SVCLASS_ID = 0x1300,
1972 UPNP_LAP_SVCLASS_ID = 0x1301,
1973 UPNP_L2CAP_SVCLASS_ID = 0x1302,
1974 VIDEO_SOURCE_SVCLASS_ID = 0x1303,
1975 VIDEO_SINK_SVCLASS_ID = 0x1304,
1976 VIDEO_DISTRIBUTION_SVCLASS_ID = 0x1305,
1977 MDP_SVCLASS_ID = 0x1400,
1978 MDP_SOURCE_SVCLASS_ID = 0x1401,
1979 MDP_SINK_SVCLASS_ID = 0x1402,
1980 APPLE_AGENT_SVCLASS_ID = 0x2112,
1981};
1982
1983/*
1984 * Standard profile descriptor identifiers; note these
1985 * may be identical to some of the service classes defined above
1986 */
1987#define SDP_SERVER_PROFILE_ID SDP_SERVER_SVCLASS_ID
1988#define BROWSE_GRP_DESC_PROFILE_ID BROWSE_GRP_DESC_SVCLASS_ID
1989#define SERIAL_PORT_PROFILE_ID SERIAL_PORT_SVCLASS_ID
1990#define LAN_ACCESS_PROFILE_ID LAN_ACCESS_SVCLASS_ID
1991#define DIALUP_NET_PROFILE_ID DIALUP_NET_SVCLASS_ID
1992#define IRMC_SYNC_PROFILE_ID IRMC_SYNC_SVCLASS_ID
1993#define OBEX_OBJPUSH_PROFILE_ID OBEX_OBJPUSH_SVCLASS_ID
1994#define OBEX_FILETRANS_PROFILE_ID OBEX_FILETRANS_SVCLASS_ID
1995#define IRMC_SYNC_CMD_PROFILE_ID IRMC_SYNC_CMD_SVCLASS_ID
1996#define HEADSET_PROFILE_ID HEADSET_SVCLASS_ID
1997#define CORDLESS_TELEPHONY_PROFILE_ID CORDLESS_TELEPHONY_SVCLASS_ID
1998#define AUDIO_SOURCE_PROFILE_ID AUDIO_SOURCE_SVCLASS_ID
1999#define AUDIO_SINK_PROFILE_ID AUDIO_SINK_SVCLASS_ID
2000#define AV_REMOTE_TARGET_PROFILE_ID AV_REMOTE_TARGET_SVCLASS_ID
2001#define ADVANCED_AUDIO_PROFILE_ID ADVANCED_AUDIO_SVCLASS_ID
2002#define AV_REMOTE_PROFILE_ID AV_REMOTE_SVCLASS_ID
2003#define VIDEO_CONF_PROFILE_ID VIDEO_CONF_SVCLASS_ID
2004#define INTERCOM_PROFILE_ID INTERCOM_SVCLASS_ID
2005#define FAX_PROFILE_ID FAX_SVCLASS_ID
2006#define HEADSET_AGW_PROFILE_ID HEADSET_AGW_SVCLASS_ID
2007#define WAP_PROFILE_ID WAP_SVCLASS_ID
2008#define WAP_CLIENT_PROFILE_ID WAP_CLIENT_SVCLASS_ID
2009#define PANU_PROFILE_ID PANU_SVCLASS_ID
2010#define NAP_PROFILE_ID NAP_SVCLASS_ID
2011#define GN_PROFILE_ID GN_SVCLASS_ID
2012#define DIRECT_PRINTING_PROFILE_ID DIRECT_PRINTING_SVCLASS_ID
2013#define REFERENCE_PRINTING_PROFILE_ID REFERENCE_PRINTING_SVCLASS_ID
2014#define IMAGING_PROFILE_ID IMAGING_SVCLASS_ID
2015#define IMAGING_RESPONDER_PROFILE_ID IMAGING_RESPONDER_SVCLASS_ID
2016#define IMAGING_ARCHIVE_PROFILE_ID IMAGING_ARCHIVE_SVCLASS_ID
2017#define IMAGING_REFOBJS_PROFILE_ID IMAGING_REFOBJS_SVCLASS_ID
2018#define HANDSFREE_PROFILE_ID HANDSFREE_SVCLASS_ID
2019#define HANDSFREE_AGW_PROFILE_ID HANDSFREE_AGW_SVCLASS_ID
2020#define DIRECT_PRT_REFOBJS_PROFILE_ID DIRECT_PRT_REFOBJS_SVCLASS_ID
2021#define REFLECTED_UI_PROFILE_ID REFLECTED_UI_SVCLASS_ID
2022#define BASIC_PRINTING_PROFILE_ID BASIC_PRINTING_SVCLASS_ID
2023#define PRINTING_STATUS_PROFILE_ID PRINTING_STATUS_SVCLASS_ID
2024#define HID_PROFILE_ID HID_SVCLASS_ID
2025#define HCR_PROFILE_ID HCR_SCAN_SVCLASS_ID
2026#define HCR_PRINT_PROFILE_ID HCR_PRINT_SVCLASS_ID
2027#define HCR_SCAN_PROFILE_ID HCR_SCAN_SVCLASS_ID
2028#define CIP_PROFILE_ID CIP_SVCLASS_ID
2029#define VIDEO_CONF_GW_PROFILE_ID VIDEO_CONF_GW_SVCLASS_ID
2030#define UDI_MT_PROFILE_ID UDI_MT_SVCLASS_ID
2031#define UDI_TA_PROFILE_ID UDI_TA_SVCLASS_ID
2032#define AV_PROFILE_ID AV_SVCLASS_ID
2033#define SAP_PROFILE_ID SAP_SVCLASS_ID
2034#define PBAP_PCE_PROFILE_ID PBAP_PCE_SVCLASS_ID
2035#define PBAP_PSE_PROFILE_ID PBAP_PSE_SVCLASS_ID
2036#define PBAP_PROFILE_ID PBAP_SVCLASS_ID
2037#define PNP_INFO_PROFILE_ID PNP_INFO_SVCLASS_ID
2038#define GENERIC_NETWORKING_PROFILE_ID GENERIC_NETWORKING_SVCLASS_ID
2039#define GENERIC_FILETRANS_PROFILE_ID GENERIC_FILETRANS_SVCLASS_ID
2040#define GENERIC_AUDIO_PROFILE_ID GENERIC_AUDIO_SVCLASS_ID
2041#define GENERIC_TELEPHONY_PROFILE_ID GENERIC_TELEPHONY_SVCLASS_ID
2042#define UPNP_PROFILE_ID UPNP_SVCLASS_ID
2043#define UPNP_IP_PROFILE_ID UPNP_IP_SVCLASS_ID
2044#define UPNP_PAN_PROFILE_ID UPNP_PAN_SVCLASS_ID
2045#define UPNP_LAP_PROFILE_ID UPNP_LAP_SVCLASS_ID
2046#define UPNP_L2CAP_PROFILE_ID UPNP_L2CAP_SVCLASS_ID
2047#define VIDEO_SOURCE_PROFILE_ID VIDEO_SOURCE_SVCLASS_ID
2048#define VIDEO_SINK_PROFILE_ID VIDEO_SINK_SVCLASS_ID
2049#define VIDEO_DISTRIBUTION_PROFILE_ID VIDEO_DISTRIBUTION_SVCLASS_ID
2050#define MDP_PROFILE_ID MDP_SVCLASS_ID
2051#define MDP_SOURCE_PROFILE_ID MDP_SROUCE_SVCLASS_ID
2052#define MDP_SINK_PROFILE_ID MDP_SINK_SVCLASS_ID
2053#define APPLE_AGENT_PROFILE_ID APPLE_AGENT_SVCLASS_ID
2054
2055/* Data Representation */
2056enum bt_sdp_data_type {
2057 SDP_DTYPE_NIL = 0 << 3,
2058 SDP_DTYPE_UINT = 1 << 3,
2059 SDP_DTYPE_SINT = 2 << 3,
2060 SDP_DTYPE_UUID = 3 << 3,
2061 SDP_DTYPE_STRING = 4 << 3,
2062 SDP_DTYPE_BOOL = 5 << 3,
2063 SDP_DTYPE_SEQ = 6 << 3,
2064 SDP_DTYPE_ALT = 7 << 3,
2065 SDP_DTYPE_URL = 8 << 3,
2066};
2067
2068enum bt_sdp_data_size {
2069 SDP_DSIZE_1 = 0,
2070 SDP_DSIZE_2,
2071 SDP_DSIZE_4,
2072 SDP_DSIZE_8,
2073 SDP_DSIZE_16,
2074 SDP_DSIZE_NEXT1,
2075 SDP_DSIZE_NEXT2,
2076 SDP_DSIZE_NEXT4,
2077 SDP_DSIZE_MASK = SDP_DSIZE_NEXT4,
2078};
2079
2080enum bt_sdp_cmd {
2081 SDP_ERROR_RSP = 0x01,
2082 SDP_SVC_SEARCH_REQ = 0x02,
2083 SDP_SVC_SEARCH_RSP = 0x03,
2084 SDP_SVC_ATTR_REQ = 0x04,
2085 SDP_SVC_ATTR_RSP = 0x05,
2086 SDP_SVC_SEARCH_ATTR_REQ = 0x06,
2087 SDP_SVC_SEARCH_ATTR_RSP = 0x07,
2088};
2089
2090enum bt_sdp_errorcode {
2091 SDP_INVALID_VERSION = 0x0001,
2092 SDP_INVALID_RECORD_HANDLE = 0x0002,
2093 SDP_INVALID_SYNTAX = 0x0003,
2094 SDP_INVALID_PDU_SIZE = 0x0004,
2095 SDP_INVALID_CSTATE = 0x0005,
2096};
2097
2098/*
2099 * String identifiers are based on the SDP spec stating that
2100 * "base attribute id of the primary (universal) language must be 0x0100"
2101 *
2102 * Other languages should have their own offset; e.g.:
2103 * #define XXXLangBase yyyy
2104 * #define AttrServiceName_XXX 0x0000+XXXLangBase
2105 */
2106#define SDP_PRIMARY_LANG_BASE 0x0100
2107
2108enum bt_sdp_attribute_id {
2109 SDP_ATTR_RECORD_HANDLE = 0x0000,
2110 SDP_ATTR_SVCLASS_ID_LIST = 0x0001,
2111 SDP_ATTR_RECORD_STATE = 0x0002,
2112 SDP_ATTR_SERVICE_ID = 0x0003,
2113 SDP_ATTR_PROTO_DESC_LIST = 0x0004,
2114 SDP_ATTR_BROWSE_GRP_LIST = 0x0005,
2115 SDP_ATTR_LANG_BASE_ATTR_ID_LIST = 0x0006,
2116 SDP_ATTR_SVCINFO_TTL = 0x0007,
2117 SDP_ATTR_SERVICE_AVAILABILITY = 0x0008,
2118 SDP_ATTR_PFILE_DESC_LIST = 0x0009,
2119 SDP_ATTR_DOC_URL = 0x000a,
2120 SDP_ATTR_CLNT_EXEC_URL = 0x000b,
2121 SDP_ATTR_ICON_URL = 0x000c,
2122 SDP_ATTR_ADD_PROTO_DESC_LIST = 0x000d,
2123
2124 SDP_ATTR_SVCNAME_PRIMARY = SDP_PRIMARY_LANG_BASE + 0,
2125 SDP_ATTR_SVCDESC_PRIMARY = SDP_PRIMARY_LANG_BASE + 1,
2126 SDP_ATTR_SVCPROV_PRIMARY = SDP_PRIMARY_LANG_BASE + 2,
2127
2128 SDP_ATTR_GROUP_ID = 0x0200,
2129 SDP_ATTR_IP_SUBNET = 0x0200,
2130
2131 /* SDP */
2132 SDP_ATTR_VERSION_NUM_LIST = 0x0200,
2133 SDP_ATTR_SVCDB_STATE = 0x0201,
2134
2135 SDP_ATTR_SERVICE_VERSION = 0x0300,
2136 SDP_ATTR_EXTERNAL_NETWORK = 0x0301,
2137 SDP_ATTR_SUPPORTED_DATA_STORES_LIST = 0x0301,
2138 SDP_ATTR_FAX_CLASS1_SUPPORT = 0x0302,
2139 SDP_ATTR_REMOTE_AUDIO_VOLUME_CONTROL = 0x0302,
2140 SDP_ATTR_FAX_CLASS20_SUPPORT = 0x0303,
2141 SDP_ATTR_SUPPORTED_FORMATS_LIST = 0x0303,
2142 SDP_ATTR_FAX_CLASS2_SUPPORT = 0x0304,
2143 SDP_ATTR_AUDIO_FEEDBACK_SUPPORT = 0x0305,
2144 SDP_ATTR_NETWORK_ADDRESS = 0x0306,
2145 SDP_ATTR_WAP_GATEWAY = 0x0307,
2146 SDP_ATTR_HOMEPAGE_URL = 0x0308,
2147 SDP_ATTR_WAP_STACK_TYPE = 0x0309,
2148 SDP_ATTR_SECURITY_DESC = 0x030a,
2149 SDP_ATTR_NET_ACCESS_TYPE = 0x030b,
2150 SDP_ATTR_MAX_NET_ACCESSRATE = 0x030c,
2151 SDP_ATTR_IP4_SUBNET = 0x030d,
2152 SDP_ATTR_IP6_SUBNET = 0x030e,
2153 SDP_ATTR_SUPPORTED_CAPABILITIES = 0x0310,
2154 SDP_ATTR_SUPPORTED_FEATURES = 0x0311,
2155 SDP_ATTR_SUPPORTED_FUNCTIONS = 0x0312,
2156 SDP_ATTR_TOTAL_IMAGING_DATA_CAPACITY = 0x0313,
2157 SDP_ATTR_SUPPORTED_REPOSITORIES = 0x0314,
2158
2159 /* PnP Information */
2160 SDP_ATTR_SPECIFICATION_ID = 0x0200,
2161 SDP_ATTR_VENDOR_ID = 0x0201,
2162 SDP_ATTR_PRODUCT_ID = 0x0202,
2163 SDP_ATTR_VERSION = 0x0203,
2164 SDP_ATTR_PRIMARY_RECORD = 0x0204,
2165 SDP_ATTR_VENDOR_ID_SOURCE = 0x0205,
2166
2167 /* BT HID */
2168 SDP_ATTR_DEVICE_RELEASE_NUMBER = 0x0200,
2169 SDP_ATTR_PARSER_VERSION = 0x0201,
2170 SDP_ATTR_DEVICE_SUBCLASS = 0x0202,
2171 SDP_ATTR_COUNTRY_CODE = 0x0203,
2172 SDP_ATTR_VIRTUAL_CABLE = 0x0204,
2173 SDP_ATTR_RECONNECT_INITIATE = 0x0205,
2174 SDP_ATTR_DESCRIPTOR_LIST = 0x0206,
2175 SDP_ATTR_LANG_ID_BASE_LIST = 0x0207,
2176 SDP_ATTR_SDP_DISABLE = 0x0208,
2177 SDP_ATTR_BATTERY_POWER = 0x0209,
2178 SDP_ATTR_REMOTE_WAKEUP = 0x020a,
2179 SDP_ATTR_PROFILE_VERSION = 0x020b,
2180 SDP_ATTR_SUPERVISION_TIMEOUT = 0x020c,
2181 SDP_ATTR_NORMALLY_CONNECTABLE = 0x020d,
2182 SDP_ATTR_BOOT_DEVICE = 0x020e,
2183};
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