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79aceca5
FB		 1/*
2 * PPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
c6a1c22b
FB		 20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
79aceca5 26#include "cpu.h"
c6a1c22b 27#include "exec-all.h"
79aceca5
FB		 28#include "disas.h"
29
30//#define DO_SINGLE_STEP
9fddaa0c 31//#define PPC_DEBUG_DISAS
79aceca5
FB		 32
33enum {
34#define DEF(s, n, copy_size) INDEX_op_ ## s,
35#include "opc.h"
36#undef DEF
37 NB_OPS,
38};
39
40static uint16_t *gen_opc_ptr;
41static uint32_t *gen_opparam_ptr;
42
43#include "gen-op.h"
28b6751f 44
28b6751f 45#define GEN8(func, NAME) \
9a64fbe4
FB		 46static GenOpFunc *NAME ## _table [8] = { \
47NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
48NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
49}; \
50static inline void func(int n) \
51{ \
52 NAME ## _table[n](); \
53}
54
55#define GEN16(func, NAME) \
56static GenOpFunc *NAME ## _table [16] = { \
57NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
58NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
59NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
60NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
61}; \
62static inline void func(int n) \
63{ \
64 NAME ## _table[n](); \
28b6751f
FB		 65}
66
67#define GEN32(func, NAME) \
9a64fbe4
FB		 68static GenOpFunc *NAME ## _table [32] = { \
69NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
70NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
71NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
72NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
73NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
74NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
75NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
76NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
77}; \
78static inline void func(int n) \
79{ \
80 NAME ## _table[n](); \
81}
82
83/* Condition register moves */
84GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);
85GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);
86GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
87GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
28b6751f 88
fb0eaffc
FB		 89/* Floating point condition and status register moves */
90GEN8(gen_op_load_fpscr_T0, gen_op_load_fpscr_T0_fpscr);
91GEN8(gen_op_store_T0_fpscr, gen_op_store_T0_fpscr_fpscr);
92GEN8(gen_op_clear_fpscr, gen_op_clear_fpscr_fpscr);
93static GenOpFunc1 *gen_op_store_T0_fpscri_fpscr_table[8] = {
94 &gen_op_store_T0_fpscri_fpscr0,
95 &gen_op_store_T0_fpscri_fpscr1,
96 &gen_op_store_T0_fpscri_fpscr2,
97 &gen_op_store_T0_fpscri_fpscr3,
98 &gen_op_store_T0_fpscri_fpscr4,
99 &gen_op_store_T0_fpscri_fpscr5,
100 &gen_op_store_T0_fpscri_fpscr6,
101 &gen_op_store_T0_fpscri_fpscr7,
102};
103static inline void gen_op_store_T0_fpscri(int n, uint8_t param)
104{
105 (*gen_op_store_T0_fpscri_fpscr_table[n])(param);
106}
107
9a64fbe4
FB		 108/* Segment register moves */
109GEN16(gen_op_load_sr, gen_op_load_sr);
110GEN16(gen_op_store_sr, gen_op_store_sr);
28b6751f 111
9a64fbe4
FB		 112/* General purpose registers moves */
113GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
114GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
115GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
116
117GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
118GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
119GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
28b6751f 120
fb0eaffc
FB		 121/* floating point registers moves */
122GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
123GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
124GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);
125GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);
126GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);
127GEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);
79aceca5
FB		 128
129static uint8_t spr_access[1024 / 2];
130
131/* internal defines */
132typedef struct DisasContext {
133 struct TranslationBlock *tb;
046d6672 134 uint32_t nip;
79aceca5 135 uint32_t opcode;
9a64fbe4 136 uint32_t exception;
9a64fbe4
FB		 137 /* Execution mode */
138#if !defined(CONFIG_USER_ONLY)
79aceca5 139 int supervisor;
9a64fbe4
FB		 140#endif
141 /* Routine used to access memory */
142 int mem_idx;
79aceca5
FB		 143} DisasContext;
144
145typedef struct opc_handler_t {
146 /* invalid bits */
147 uint32_t inval;
9a64fbe4
FB		 148 /* instruction type */
149 uint32_t type;
79aceca5
FB		 150 /* handler */
151 void (*handler)(DisasContext *ctx);
152} opc_handler_t;
153
9fddaa0c 154#define RET_EXCP(ctx, excp, error) \
79aceca5 155do { \
9fddaa0c
FB		 156 if ((ctx)->exception == EXCP_NONE) { \
157 gen_op_update_nip((ctx)->nip); \
158 } \
159 gen_op_raise_exception_err((excp), (error)); \
160 ctx->exception = (excp); \
79aceca5
FB		 161} while (0)
162
9fddaa0c
FB		 163#define RET_INVAL(ctx) \
164RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_INVAL)
165
166#define RET_PRIVOPC(ctx) \
167RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_OPC)
9a64fbe4 168
9fddaa0c
FB		 169#define RET_PRIVREG(ctx) \
170RET_EXCP((ctx), EXCP_PROGRAM, EXCP_INVAL | EXCP_PRIV_REG)
9a64fbe4 171
9fddaa0c
FB		 172#define RET_MTMSR(ctx) \
173RET_EXCP((ctx), EXCP_MTMSR, 0)
79aceca5
FB		 174
175#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
176static void gen_##name (DisasContext *ctx); \
177GEN_OPCODE(name, opc1, opc2, opc3, inval, type); \
178static void gen_##name (DisasContext *ctx)
179
79aceca5
FB		 180typedef struct opcode_t {
181 unsigned char opc1, opc2, opc3;
79aceca5
FB		 182 opc_handler_t handler;
183} opcode_t;
184
79aceca5
FB		 185/*** Instruction decoding ***/
186#define EXTRACT_HELPER(name, shift, nb) \
187static inline uint32_t name (uint32_t opcode) \
188{ \
189 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
190}
191
192#define EXTRACT_SHELPER(name, shift, nb) \
193static inline int32_t name (uint32_t opcode) \
194{ \
195 return s_ext16((opcode >> (shift)) & ((1 << (nb)) - 1)); \
196}
197
198/* Opcode part 1 */
199EXTRACT_HELPER(opc1, 26, 6);
200/* Opcode part 2 */
201EXTRACT_HELPER(opc2, 1, 5);
202/* Opcode part 3 */
203EXTRACT_HELPER(opc3, 6, 5);
204/* Update Cr0 flags */
205EXTRACT_HELPER(Rc, 0, 1);
206/* Destination */
207EXTRACT_HELPER(rD, 21, 5);
208/* Source */
209EXTRACT_HELPER(rS, 21, 5);
210/* First operand */
211EXTRACT_HELPER(rA, 16, 5);
212/* Second operand */
213EXTRACT_HELPER(rB, 11, 5);
214/* Third operand */
215EXTRACT_HELPER(rC, 6, 5);
216/*** Get CRn ***/
217EXTRACT_HELPER(crfD, 23, 3);
218EXTRACT_HELPER(crfS, 18, 3);
219EXTRACT_HELPER(crbD, 21, 5);
220EXTRACT_HELPER(crbA, 16, 5);
221EXTRACT_HELPER(crbB, 11, 5);
222/* SPR / TBL */
223EXTRACT_HELPER(SPR, 11, 10);
224/*** Get constants ***/
225EXTRACT_HELPER(IMM, 12, 8);
226/* 16 bits signed immediate value */
227EXTRACT_SHELPER(SIMM, 0, 16);
228/* 16 bits unsigned immediate value */
229EXTRACT_HELPER(UIMM, 0, 16);
230/* Bit count */
231EXTRACT_HELPER(NB, 11, 5);
232/* Shift count */
233EXTRACT_HELPER(SH, 11, 5);
234/* Mask start */
235EXTRACT_HELPER(MB, 6, 5);
236/* Mask end */
237EXTRACT_HELPER(ME, 1, 5);
fb0eaffc
FB		 238/* Trap operand */
239EXTRACT_HELPER(TO, 21, 5);
79aceca5
FB		 240
241EXTRACT_HELPER(CRM, 12, 8);
242EXTRACT_HELPER(FM, 17, 8);
243EXTRACT_HELPER(SR, 16, 4);
fb0eaffc
FB		 244EXTRACT_HELPER(FPIMM, 20, 4);
245
79aceca5
FB		 246/*** Jump target decoding ***/
247/* Displacement */
248EXTRACT_SHELPER(d, 0, 16);
249/* Immediate address */
250static inline uint32_t LI (uint32_t opcode)
251{
252 return (opcode >> 0) & 0x03FFFFFC;
253}
254
255static inline uint32_t BD (uint32_t opcode)
256{
257 return (opcode >> 0) & 0xFFFC;
258}
259
260EXTRACT_HELPER(BO, 21, 5);
261EXTRACT_HELPER(BI, 16, 5);
262/* Absolute/relative address */
263EXTRACT_HELPER(AA, 1, 1);
264/* Link */
265EXTRACT_HELPER(LK, 0, 1);
266
267/* Create a mask between <start> and <end> bits */
268static inline uint32_t MASK (uint32_t start, uint32_t end)
269{
270 uint32_t ret;
271
272 ret = (((uint32_t)(-1)) >> (start)) ^ (((uint32_t)(-1) >> (end)) >> 1);
273 if (start > end)
274 return ~ret;
275
276 return ret;
277}
278
933dc6eb
FB		 279#if defined(__linux__)
280#define OPCODES_SECTION \
281 __attribute__ ((section(".opcodes"), unused, aligned (8) ))
282#else
283#define OPCODES_SECTION
284#endif
285
79aceca5 286#define GEN_OPCODE(name, op1, op2, op3, invl, _typ) \
933dc6eb 287OPCODES_SECTION static opcode_t opc_##name = { \
79aceca5
FB		 288 .opc1 = op1, \
289 .opc2 = op2, \
290 .opc3 = op3, \
79aceca5
FB		 291 .handler = { \
292 .inval = invl, \
9a64fbe4 293 .type = _typ, \
79aceca5
FB		 294 .handler = &gen_##name, \
295 }, \
296}
297
298#define GEN_OPCODE_MARK(name) \
933dc6eb 299OPCODES_SECTION static opcode_t opc_##name = { \
79aceca5
FB		 300 .opc1 = 0xFF, \
301 .opc2 = 0xFF, \
302 .opc3 = 0xFF, \
79aceca5
FB		 303 .handler = { \
304 .inval = 0x00000000, \
9a64fbe4 305 .type = 0x00, \
79aceca5
FB		 306 .handler = NULL, \
307 }, \
308}
309
310/* Start opcode list */
311GEN_OPCODE_MARK(start);
312
313/* Invalid instruction */
9a64fbe4
FB		 314GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE)
315{
9fddaa0c 316 RET_INVAL(ctx);
9a64fbe4
FB		 317}
318
319/* Special opcode to stop emulation */
320GEN_HANDLER(stop, 0x06, 0x00, 0xFF, 0x03FFFFC1, PPC_COMMON)
79aceca5 321{
9fddaa0c 322 RET_EXCP(ctx, EXCP_HLT, 0);
9a64fbe4
FB		 323}
324
325/* Special opcode to call open-firmware */
326GEN_HANDLER(of_enter, 0x06, 0x01, 0xFF, 0x03FFFFC1, PPC_COMMON)
327{
9fddaa0c 328 RET_EXCP(ctx, EXCP_OFCALL, 0);
9a64fbe4
FB		 329}
330
331/* Special opcode to call RTAS */
332GEN_HANDLER(rtas_enter, 0x06, 0x02, 0xFF, 0x03FFFFC1, PPC_COMMON)
333{
334 printf("RTAS entry point !\n");
9fddaa0c 335 RET_EXCP(ctx, EXCP_RTASCALL, 0);
79aceca5
FB		 336}
337
338static opc_handler_t invalid_handler = {
339 .inval = 0xFFFFFFFF,
9a64fbe4 340 .type = PPC_NONE,
79aceca5
FB		 341 .handler = gen_invalid,
342};
343
344/*** Integer arithmetic ***/
345#define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval) \
346GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
347{ \
348 gen_op_load_gpr_T0(rA(ctx->opcode)); \
349 gen_op_load_gpr_T1(rB(ctx->opcode)); \
350 gen_op_##name(); \
351 if (Rc(ctx->opcode) != 0) \
352 gen_op_set_Rc0(); \
353 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 354}
355
356#define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval) \
357GEN_HANDLER(name, opc1, opc2, opc3, inval, PPC_INTEGER) \
358{ \
359 gen_op_load_gpr_T0(rA(ctx->opcode)); \
360 gen_op_load_gpr_T1(rB(ctx->opcode)); \
361 gen_op_##name(); \
362 if (Rc(ctx->opcode) != 0) \
363 gen_op_set_Rc0_ov(); \
364 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 365}
366
367#define __GEN_INT_ARITH1(name, opc1, opc2, opc3) \
368GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
369{ \
370 gen_op_load_gpr_T0(rA(ctx->opcode)); \
371 gen_op_##name(); \
372 if (Rc(ctx->opcode) != 0) \
373 gen_op_set_Rc0(); \
374 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 375}
376#define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3) \
377GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, PPC_INTEGER) \
378{ \
379 gen_op_load_gpr_T0(rA(ctx->opcode)); \
380 gen_op_##name(); \
381 if (Rc(ctx->opcode) != 0) \
382 gen_op_set_Rc0_ov(); \
383 gen_op_store_T0_gpr(rD(ctx->opcode)); \
79aceca5
FB		 384}
385
386/* Two operands arithmetic functions */
387#define GEN_INT_ARITH2(name, opc1, opc2, opc3) \
388__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000000) \
389__GEN_INT_ARITH2_O(name##o, opc1, opc2, opc3 | 0x10, 0x00000000)
390
391/* Two operands arithmetic functions with no overflow allowed */
392#define GEN_INT_ARITHN(name, opc1, opc2, opc3) \
393__GEN_INT_ARITH2(name, opc1, opc2, opc3, 0x00000400)
394
395/* One operand arithmetic functions */
396#define GEN_INT_ARITH1(name, opc1, opc2, opc3) \
397__GEN_INT_ARITH1(name, opc1, opc2, opc3) \
398__GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10)
399
400/* add add. addo addo. */
401GEN_INT_ARITH2 (add, 0x1F, 0x0A, 0x08);
402/* addc addc. addco addco. */
403GEN_INT_ARITH2 (addc, 0x1F, 0x0A, 0x00);
404/* adde adde. addeo addeo. */
405GEN_INT_ARITH2 (adde, 0x1F, 0x0A, 0x04);
406/* addme addme. addmeo addmeo. */
407GEN_INT_ARITH1 (addme, 0x1F, 0x0A, 0x07);
408/* addze addze. addzeo addzeo. */
409GEN_INT_ARITH1 (addze, 0x1F, 0x0A, 0x06);
410/* divw divw. divwo divwo. */
411GEN_INT_ARITH2 (divw, 0x1F, 0x0B, 0x0F);
412/* divwu divwu. divwuo divwuo. */
413GEN_INT_ARITH2 (divwu, 0x1F, 0x0B, 0x0E);
414/* mulhw mulhw. */
415GEN_INT_ARITHN (mulhw, 0x1F, 0x0B, 0x02);
416/* mulhwu mulhwu. */
417GEN_INT_ARITHN (mulhwu, 0x1F, 0x0B, 0x00);
418/* mullw mullw. mullwo mullwo. */
419GEN_INT_ARITH2 (mullw, 0x1F, 0x0B, 0x07);
420/* neg neg. nego nego. */
421GEN_INT_ARITH1 (neg, 0x1F, 0x08, 0x03);
422/* subf subf. subfo subfo. */
423GEN_INT_ARITH2 (subf, 0x1F, 0x08, 0x01);
424/* subfc subfc. subfco subfco. */
425GEN_INT_ARITH2 (subfc, 0x1F, 0x08, 0x00);
426/* subfe subfe. subfeo subfeo. */
427GEN_INT_ARITH2 (subfe, 0x1F, 0x08, 0x04);
428/* subfme subfme. subfmeo subfmeo. */
429GEN_INT_ARITH1 (subfme, 0x1F, 0x08, 0x07);
430/* subfze subfze. subfzeo subfzeo. */
431GEN_INT_ARITH1 (subfze, 0x1F, 0x08, 0x06);
432/* addi */
433GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
434{
435 int32_t simm = SIMM(ctx->opcode);
436
437 if (rA(ctx->opcode) == 0) {
438 gen_op_set_T0(simm);
439 } else {
440 gen_op_load_gpr_T0(rA(ctx->opcode));
441 gen_op_addi(simm);
442 }
443 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 444}
445/* addic */
446GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
447{
448 gen_op_load_gpr_T0(rA(ctx->opcode));
449 gen_op_addic(SIMM(ctx->opcode));
450 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 451}
452/* addic. */
453GEN_HANDLER(addic_, 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
454{
455 gen_op_load_gpr_T0(rA(ctx->opcode));
456 gen_op_addic(SIMM(ctx->opcode));
457 gen_op_set_Rc0();
458 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 459}
460/* addis */
461GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
462{
463 int32_t simm = SIMM(ctx->opcode);
464
465 if (rA(ctx->opcode) == 0) {
466 gen_op_set_T0(simm << 16);
467 } else {
468 gen_op_load_gpr_T0(rA(ctx->opcode));
469 gen_op_addi(simm << 16);
470 }
471 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 472}
473/* mulli */
474GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
475{
476 gen_op_load_gpr_T0(rA(ctx->opcode));
477 gen_op_mulli(SIMM(ctx->opcode));
478 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 479}
480/* subfic */
481GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
482{
483 gen_op_load_gpr_T0(rA(ctx->opcode));
484 gen_op_subfic(SIMM(ctx->opcode));
485 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 486}
487
488/*** Integer comparison ***/
489#define GEN_CMP(name, opc) \
490GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, PPC_INTEGER) \
491{ \
492 gen_op_load_gpr_T0(rA(ctx->opcode)); \
493 gen_op_load_gpr_T1(rB(ctx->opcode)); \
494 gen_op_##name(); \
495 gen_op_store_T0_crf(crfD(ctx->opcode)); \
79aceca5
FB		 496}
497
498/* cmp */
499GEN_CMP(cmp, 0x00);
500/* cmpi */
501GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
502{
503 gen_op_load_gpr_T0(rA(ctx->opcode));
504 gen_op_cmpi(SIMM(ctx->opcode));
505 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 506}
507/* cmpl */
508GEN_CMP(cmpl, 0x01);
509/* cmpli */
510GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
511{
512 gen_op_load_gpr_T0(rA(ctx->opcode));
513 gen_op_cmpli(UIMM(ctx->opcode));
514 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 515}
516
517/*** Integer logical ***/
518#define __GEN_LOGICAL2(name, opc2, opc3) \
519GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, PPC_INTEGER) \
520{ \
521 gen_op_load_gpr_T0(rS(ctx->opcode)); \
522 gen_op_load_gpr_T1(rB(ctx->opcode)); \
523 gen_op_##name(); \
524 if (Rc(ctx->opcode) != 0) \
525 gen_op_set_Rc0(); \
526 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 527}
528#define GEN_LOGICAL2(name, opc) \
529__GEN_LOGICAL2(name, 0x1C, opc)
530
531#define GEN_LOGICAL1(name, opc) \
532GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, PPC_INTEGER) \
533{ \
534 gen_op_load_gpr_T0(rS(ctx->opcode)); \
535 gen_op_##name(); \
536 if (Rc(ctx->opcode) != 0) \
537 gen_op_set_Rc0(); \
538 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 539}
540
541/* and & and. */
542GEN_LOGICAL2(and, 0x00);
543/* andc & andc. */
544GEN_LOGICAL2(andc, 0x01);
545/* andi. */
546GEN_HANDLER(andi_, 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
547{
548 gen_op_load_gpr_T0(rS(ctx->opcode));
549 gen_op_andi_(UIMM(ctx->opcode));
550 gen_op_set_Rc0();
551 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 552}
553/* andis. */
554GEN_HANDLER(andis_, 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
555{
556 gen_op_load_gpr_T0(rS(ctx->opcode));
557 gen_op_andi_(UIMM(ctx->opcode) << 16);
558 gen_op_set_Rc0();
559 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 560}
561
562/* cntlzw */
563GEN_LOGICAL1(cntlzw, 0x00);
564/* eqv & eqv. */
565GEN_LOGICAL2(eqv, 0x08);
566/* extsb & extsb. */
567GEN_LOGICAL1(extsb, 0x1D);
568/* extsh & extsh. */
569GEN_LOGICAL1(extsh, 0x1C);
570/* nand & nand. */
571GEN_LOGICAL2(nand, 0x0E);
572/* nor & nor. */
573GEN_LOGICAL2(nor, 0x03);
9a64fbe4 574
79aceca5 575/* or & or. */
9a64fbe4
FB		 576GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
577{
578 gen_op_load_gpr_T0(rS(ctx->opcode));
579 /* Optimisation for mr case */
580 if (rS(ctx->opcode) != rB(ctx->opcode)) {
581 gen_op_load_gpr_T1(rB(ctx->opcode));
582 gen_op_or();
583 }
584 if (Rc(ctx->opcode) != 0)
585 gen_op_set_Rc0();
586 gen_op_store_T0_gpr(rA(ctx->opcode));
587}
588
79aceca5
FB		 589/* orc & orc. */
590GEN_LOGICAL2(orc, 0x0C);
591/* xor & xor. */
9a64fbe4
FB		 592GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
593{
594 gen_op_load_gpr_T0(rS(ctx->opcode));
595 /* Optimisation for "set to zero" case */
596 if (rS(ctx->opcode) != rB(ctx->opcode)) {
597 gen_op_load_gpr_T1(rB(ctx->opcode));
598 gen_op_xor();
599 } else {
600 gen_op_set_T0(0);
601 }
602 if (Rc(ctx->opcode) != 0)
603 gen_op_set_Rc0();
604 gen_op_store_T0_gpr(rA(ctx->opcode));
605}
79aceca5
FB		 606/* ori */
607GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
608{
609 uint32_t uimm = UIMM(ctx->opcode);
610
9a64fbe4
FB		 611 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
612 /* NOP */
613 return;
79aceca5 614 }
79aceca5 615 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 616 if (uimm != 0)
79aceca5
FB		 617 gen_op_ori(uimm);
618 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 619}
620/* oris */
621GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
622{
623 uint32_t uimm = UIMM(ctx->opcode);
624
9a64fbe4
FB		 625 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
626 /* NOP */
627 return;
79aceca5 628 }
79aceca5 629 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 630 if (uimm != 0)
79aceca5
FB		 631 gen_op_ori(uimm << 16);
632 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 633}
634/* xori */
635GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
636{
9a64fbe4
FB		 637 uint32_t uimm = UIMM(ctx->opcode);
638
639 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
640 /* NOP */
641 return;
642 }
79aceca5 643 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 644 if (uimm != 0)
4b3686fa 645 gen_op_xori(uimm);
79aceca5 646 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 647}
648
649/* xoris */
650GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
651{
9a64fbe4
FB		 652 uint32_t uimm = UIMM(ctx->opcode);
653
654 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
655 /* NOP */
656 return;
657 }
79aceca5 658 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4 659 if (uimm != 0)
4b3686fa 660 gen_op_xori(uimm << 16);
79aceca5 661 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 662}
663
664/*** Integer rotate ***/
665/* rlwimi & rlwimi. */
666GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
667{
668 uint32_t mb, me;
669
670 mb = MB(ctx->opcode);
671 me = ME(ctx->opcode);
672 gen_op_load_gpr_T0(rS(ctx->opcode));
fb0eaffc 673 gen_op_load_gpr_T1(rA(ctx->opcode));
79aceca5
FB		 674 gen_op_rlwimi(SH(ctx->opcode), MASK(mb, me), ~MASK(mb, me));
675 if (Rc(ctx->opcode) != 0)
676 gen_op_set_Rc0();
677 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 678}
679/* rlwinm & rlwinm. */
680GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
681{
682 uint32_t mb, me, sh;
683
684 sh = SH(ctx->opcode);
685 mb = MB(ctx->opcode);
686 me = ME(ctx->opcode);
687 gen_op_load_gpr_T0(rS(ctx->opcode));
4b3686fa
FB		 688#if 1 // TRY
689 if (sh == 0) {
690 gen_op_andi_(MASK(mb, me));
691 goto store;
692 }
693#endif
79aceca5
FB		 694 if (mb == 0) {
695 if (me == 31) {
696 gen_op_rotlwi(sh);
697 goto store;
4b3686fa 698#if 0
79aceca5
FB		 699 } else if (me == (31 - sh)) {
700 gen_op_slwi(sh);
701 goto store;
4b3686fa 702#endif
79aceca5
FB		 703 }
704 } else if (me == 31) {
4b3686fa 705#if 0
79aceca5
FB		 706 if (sh == (32 - mb)) {
707 gen_op_srwi(mb);
708 goto store;
79aceca5 709 }
4b3686fa 710#endif
79aceca5
FB		 711 }
712 gen_op_rlwinm(sh, MASK(mb, me));
713store:
714 if (Rc(ctx->opcode) != 0)
715 gen_op_set_Rc0();
716 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 717}
718/* rlwnm & rlwnm. */
719GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
720{
721 uint32_t mb, me;
722
723 mb = MB(ctx->opcode);
724 me = ME(ctx->opcode);
725 gen_op_load_gpr_T0(rS(ctx->opcode));
726 gen_op_load_gpr_T1(rB(ctx->opcode));
727 if (mb == 0 && me == 31) {
728 gen_op_rotl();
729 } else
730 {
731 gen_op_rlwnm(MASK(mb, me));
732 }
733 if (Rc(ctx->opcode) != 0)
734 gen_op_set_Rc0();
735 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 736}
737
738/*** Integer shift ***/
739/* slw & slw. */
740__GEN_LOGICAL2(slw, 0x18, 0x00);
741/* sraw & sraw. */
742__GEN_LOGICAL2(sraw, 0x18, 0x18);
743/* srawi & srawi. */
744GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
745{
746 gen_op_load_gpr_T0(rS(ctx->opcode));
747 gen_op_srawi(SH(ctx->opcode), MASK(32 - SH(ctx->opcode), 31));
748 if (Rc(ctx->opcode) != 0)
749 gen_op_set_Rc0();
750 gen_op_store_T0_gpr(rA(ctx->opcode));
79aceca5
FB		 751}
752/* srw & srw. */
753__GEN_LOGICAL2(srw, 0x18, 0x10);
754
755/*** Floating-Point arithmetic ***/
9a64fbe4
FB		 756#define _GEN_FLOAT_ACB(name, op1, op2) \
757GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, PPC_FLOAT) \
758{ \
759 gen_op_reset_scrfx(); \
760 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
761 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
762 gen_op_load_fpr_FT2(rB(ctx->opcode)); \
763 gen_op_f##name(); \
764 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
765 if (Rc(ctx->opcode)) \
766 gen_op_set_Rc1(); \
767}
768
769#define GEN_FLOAT_ACB(name, op2) \
770_GEN_FLOAT_ACB(name, 0x3F, op2); \
771_GEN_FLOAT_ACB(name##s, 0x3B, op2);
772
773#define _GEN_FLOAT_AB(name, op1, op2, inval) \
774GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
775{ \
776 gen_op_reset_scrfx(); \
777 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
778 gen_op_load_fpr_FT1(rB(ctx->opcode)); \
779 gen_op_f##name(); \
780 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
781 if (Rc(ctx->opcode)) \
782 gen_op_set_Rc1(); \
783}
784#define GEN_FLOAT_AB(name, op2, inval) \
785_GEN_FLOAT_AB(name, 0x3F, op2, inval); \
786_GEN_FLOAT_AB(name##s, 0x3B, op2, inval);
787
788#define _GEN_FLOAT_AC(name, op1, op2, inval) \
789GEN_HANDLER(f##name, op1, op2, 0xFF, inval, PPC_FLOAT) \
790{ \
791 gen_op_reset_scrfx(); \
792 gen_op_load_fpr_FT0(rA(ctx->opcode)); \
793 gen_op_load_fpr_FT1(rC(ctx->opcode)); \
794 gen_op_f##name(); \
795 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
796 if (Rc(ctx->opcode)) \
797 gen_op_set_Rc1(); \
798}
799#define GEN_FLOAT_AC(name, op2, inval) \
800_GEN_FLOAT_AC(name, 0x3F, op2, inval); \
801_GEN_FLOAT_AC(name##s, 0x3B, op2, inval);
802
803#define GEN_FLOAT_B(name, op2, op3) \
804GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, PPC_FLOAT) \
805{ \
806 gen_op_reset_scrfx(); \
807 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
808 gen_op_f##name(); \
809 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
810 if (Rc(ctx->opcode)) \
811 gen_op_set_Rc1(); \
79aceca5
FB		 812}
813
9a64fbe4
FB		 814#define GEN_FLOAT_BS(name, op2) \
815GEN_HANDLER(f##name, 0x3F, op2, 0xFF, 0x001F07C0, PPC_FLOAT) \
816{ \
817 gen_op_reset_scrfx(); \
818 gen_op_load_fpr_FT0(rB(ctx->opcode)); \
819 gen_op_f##name(); \
820 gen_op_store_FT0_fpr(rD(ctx->opcode)); \
821 if (Rc(ctx->opcode)) \
822 gen_op_set_Rc1(); \
79aceca5
FB		 823}
824
9a64fbe4
FB		 825/* fadd - fadds */
826GEN_FLOAT_AB(add, 0x15, 0x000007C0);
79aceca5 827/* fdiv */
9a64fbe4 828GEN_FLOAT_AB(div, 0x12, 0x000007C0);
79aceca5 829/* fmul */
9a64fbe4 830GEN_FLOAT_AC(mul, 0x19, 0x0000F800);
79aceca5
FB		 831
832/* fres */
9a64fbe4 833GEN_FLOAT_BS(res, 0x18);
79aceca5
FB		 834
835/* frsqrte */
9a64fbe4 836GEN_FLOAT_BS(rsqrte, 0x1A);
79aceca5
FB		 837
838/* fsel */
9a64fbe4 839_GEN_FLOAT_ACB(sel, 0x3F, 0x17);
79aceca5 840/* fsub */
9a64fbe4 841GEN_FLOAT_AB(sub, 0x14, 0x000007C0);
79aceca5
FB		 842/* Optional: */
843/* fsqrt */
9a64fbe4 844GEN_FLOAT_BS(sqrt, 0x16);
79aceca5 845
9a64fbe4 846GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_OPT)
79aceca5 847{
9a64fbe4
FB		 848 gen_op_reset_scrfx();
849 gen_op_load_fpr_FT0(rB(ctx->opcode));
850 gen_op_fsqrts();
851 gen_op_store_FT0_fpr(rD(ctx->opcode));
852 if (Rc(ctx->opcode))
853 gen_op_set_Rc1();
79aceca5
FB		 854}
855
856/*** Floating-Point multiply-and-add ***/
857/* fmadd */
9a64fbe4 858GEN_FLOAT_ACB(madd, 0x1D);
79aceca5 859/* fmsub */
9a64fbe4 860GEN_FLOAT_ACB(msub, 0x1C);
79aceca5 861/* fnmadd */
9a64fbe4 862GEN_FLOAT_ACB(nmadd, 0x1F);
79aceca5 863/* fnmsub */
9a64fbe4 864GEN_FLOAT_ACB(nmsub, 0x1E);
79aceca5
FB		 865
866/*** Floating-Point round & convert ***/
867/* fctiw */
9a64fbe4 868GEN_FLOAT_B(ctiw, 0x0E, 0x00);
79aceca5 869/* fctiwz */
9a64fbe4 870GEN_FLOAT_B(ctiwz, 0x0F, 0x00);
79aceca5 871/* frsp */
9a64fbe4 872GEN_FLOAT_B(rsp, 0x0C, 0x00);
79aceca5
FB		 873
874/*** Floating-Point compare ***/
875/* fcmpo */
876GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT)
877{
9a64fbe4
FB		 878 gen_op_reset_scrfx();
879 gen_op_load_fpr_FT0(rA(ctx->opcode));
880 gen_op_load_fpr_FT1(rB(ctx->opcode));
881 gen_op_fcmpo();
882 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 883}
884
885/* fcmpu */
886GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT)
887{
9a64fbe4
FB		 888 gen_op_reset_scrfx();
889 gen_op_load_fpr_FT0(rA(ctx->opcode));
890 gen_op_load_fpr_FT1(rB(ctx->opcode));
891 gen_op_fcmpu();
892 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 893}
894
9a64fbe4
FB		 895/*** Floating-point move ***/
896/* fabs */
897GEN_FLOAT_B(abs, 0x08, 0x08);
898
899/* fmr - fmr. */
900GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT)
901{
902 gen_op_reset_scrfx();
903 gen_op_load_fpr_FT0(rB(ctx->opcode));
904 gen_op_store_FT0_fpr(rD(ctx->opcode));
905 if (Rc(ctx->opcode))
906 gen_op_set_Rc1();
907}
908
909/* fnabs */
910GEN_FLOAT_B(nabs, 0x08, 0x04);
911/* fneg */
912GEN_FLOAT_B(neg, 0x08, 0x01);
913
79aceca5
FB		 914/*** Floating-Point status & ctrl register ***/
915/* mcrfs */
916GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT)
917{
fb0eaffc
FB		 918 gen_op_load_fpscr_T0(crfS(ctx->opcode));
919 gen_op_store_T0_crf(crfD(ctx->opcode));
920 gen_op_clear_fpscr(crfS(ctx->opcode));
79aceca5
FB		 921}
922
923/* mffs */
924GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT)
925{
28b6751f 926 gen_op_load_fpscr();
fb0eaffc
FB		 927 gen_op_store_FT0_fpr(rD(ctx->opcode));
928 if (Rc(ctx->opcode))
929 gen_op_set_Rc1();
79aceca5
FB		 930}
931
932/* mtfsb0 */
933GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT)
934{
fb0eaffc
FB		 935 uint8_t crb;
936
937 crb = crbD(ctx->opcode) >> 2;
938 gen_op_load_fpscr_T0(crb);
939 gen_op_andi_(~(1 << (crbD(ctx->opcode) & 0x03)));
940 gen_op_store_T0_fpscr(crb);
941 if (Rc(ctx->opcode))
942 gen_op_set_Rc1();
79aceca5
FB		 943}
944
945/* mtfsb1 */
946GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT)
947{
fb0eaffc
FB		 948 uint8_t crb;
949
950 crb = crbD(ctx->opcode) >> 2;
951 gen_op_load_fpscr_T0(crb);
952 gen_op_ori(1 << (crbD(ctx->opcode) & 0x03));
953 gen_op_store_T0_fpscr(crb);
954 if (Rc(ctx->opcode))
955 gen_op_set_Rc1();
79aceca5
FB		 956}
957
958/* mtfsf */
959GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x02010000, PPC_FLOAT)
960{
fb0eaffc 961 gen_op_load_fpr_FT0(rB(ctx->opcode));
28b6751f 962 gen_op_store_fpscr(FM(ctx->opcode));
fb0eaffc
FB		 963 if (Rc(ctx->opcode))
964 gen_op_set_Rc1();
79aceca5
FB		 965}
966
967/* mtfsfi */
968GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
969{
fb0eaffc
FB		 970 gen_op_store_T0_fpscri(crbD(ctx->opcode) >> 2, FPIMM(ctx->opcode));
971 if (Rc(ctx->opcode))
972 gen_op_set_Rc1();
79aceca5
FB		 973}
974
975/*** Integer load ***/
9a64fbe4
FB		 976#if defined(CONFIG_USER_ONLY)
977#define op_ldst(name) gen_op_##name##_raw()
978#define OP_LD_TABLE(width)
979#define OP_ST_TABLE(width)
980#else
981#define op_ldst(name) (*gen_op_##name[ctx->mem_idx])()
982#define OP_LD_TABLE(width) \
983static GenOpFunc *gen_op_l##width[] = { \
984 &gen_op_l##width##_user, \
985 &gen_op_l##width##_kernel, \
986}
987#define OP_ST_TABLE(width) \
988static GenOpFunc *gen_op_st##width[] = { \
989 &gen_op_st##width##_user, \
990 &gen_op_st##width##_kernel, \
991}
992#endif
993
994#define GEN_LD(width, opc) \
79aceca5
FB		 995GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
996{ \
997 uint32_t simm = SIMM(ctx->opcode); \
998 if (rA(ctx->opcode) == 0) { \
9a64fbe4 999 gen_op_set_T0(simm); \
79aceca5
FB		 1000 } else { \
1001 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1002 if (simm != 0) \
1003 gen_op_addi(simm); \
79aceca5 1004 } \
9a64fbe4 1005 op_ldst(l##width); \
79aceca5 1006 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1007}
1008
9a64fbe4 1009#define GEN_LDU(width, opc) \
79aceca5
FB		 1010GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1011{ \
9a64fbe4 1012 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1013 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1014 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1015 RET_INVAL(ctx); \
1016 return; \
9a64fbe4 1017 } \
79aceca5 1018 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1019 if (simm != 0) \
1020 gen_op_addi(simm); \
1021 op_ldst(l##width); \
79aceca5
FB		 1022 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1023 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1024}
1025
9a64fbe4 1026#define GEN_LDUX(width, opc) \
79aceca5
FB		 1027GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1028{ \
1029 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1030 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1031 RET_INVAL(ctx); \
1032 return; \
9a64fbe4 1033 } \
79aceca5
FB		 1034 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1035 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1036 gen_op_add(); \
1037 op_ldst(l##width); \
79aceca5
FB		 1038 gen_op_store_T1_gpr(rD(ctx->opcode)); \
1039 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1040}
1041
9a64fbe4 1042#define GEN_LDX(width, opc2, opc3) \
79aceca5
FB		 1043GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1044{ \
1045 if (rA(ctx->opcode) == 0) { \
1046 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1047 } else { \
1048 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1049 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1050 gen_op_add(); \
79aceca5 1051 } \
9a64fbe4 1052 op_ldst(l##width); \
79aceca5 1053 gen_op_store_T1_gpr(rD(ctx->opcode)); \
79aceca5
FB		 1054}
1055
9a64fbe4
FB		 1056#define GEN_LDS(width, op) \
1057OP_LD_TABLE(width); \
1058GEN_LD(width, op | 0x20); \
1059GEN_LDU(width, op | 0x21); \
1060GEN_LDUX(width, op | 0x01); \
1061GEN_LDX(width, 0x17, op | 0x00)
79aceca5
FB		 1062
1063/* lbz lbzu lbzux lbzx */
9a64fbe4 1064GEN_LDS(bz, 0x02);
79aceca5 1065/* lha lhau lhaux lhax */
9a64fbe4 1066GEN_LDS(ha, 0x0A);
79aceca5 1067/* lhz lhzu lhzux lhzx */
9a64fbe4 1068GEN_LDS(hz, 0x08);
79aceca5 1069/* lwz lwzu lwzux lwzx */
9a64fbe4 1070GEN_LDS(wz, 0x00);
79aceca5
FB		 1071
1072/*** Integer store ***/
9a64fbe4 1073#define GEN_ST(width, opc) \
79aceca5
FB		 1074GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1075{ \
1076 uint32_t simm = SIMM(ctx->opcode); \
1077 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1078 gen_op_set_T0(simm); \
79aceca5
FB		 1079 } else { \
1080 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1081 if (simm != 0) \
1082 gen_op_addi(simm); \
79aceca5 1083 } \
9a64fbe4
FB		 1084 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1085 op_ldst(st##width); \
79aceca5
FB		 1086}
1087
9a64fbe4 1088#define GEN_STU(width, opc) \
79aceca5
FB		 1089GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
1090{ \
9a64fbe4
FB		 1091 uint32_t simm = SIMM(ctx->opcode); \
1092 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1093 RET_INVAL(ctx); \
1094 return; \
9a64fbe4 1095 } \
79aceca5 1096 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1097 if (simm != 0) \
1098 gen_op_addi(simm); \
79aceca5 1099 gen_op_load_gpr_T1(rS(ctx->opcode)); \
9a64fbe4 1100 op_ldst(st##width); \
79aceca5 1101 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1102}
1103
9a64fbe4 1104#define GEN_STUX(width, opc) \
79aceca5
FB		 1105GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
1106{ \
9a64fbe4 1107 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1108 RET_INVAL(ctx); \
1109 return; \
9a64fbe4 1110 } \
79aceca5
FB		 1111 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1112 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1113 gen_op_add(); \
1114 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1115 op_ldst(st##width); \
79aceca5 1116 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1117}
1118
9a64fbe4 1119#define GEN_STX(width, opc2, opc3) \
79aceca5
FB		 1120GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
1121{ \
1122 if (rA(ctx->opcode) == 0) { \
1123 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1124 } else { \
1125 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1126 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1127 gen_op_add(); \
79aceca5 1128 } \
9a64fbe4
FB		 1129 gen_op_load_gpr_T1(rS(ctx->opcode)); \
1130 op_ldst(st##width); \
79aceca5
FB		 1131}
1132
9a64fbe4
FB		 1133#define GEN_STS(width, op) \
1134OP_ST_TABLE(width); \
1135GEN_ST(width, op | 0x20); \
1136GEN_STU(width, op | 0x21); \
1137GEN_STUX(width, op | 0x01); \
1138GEN_STX(width, 0x17, op | 0x00)
79aceca5
FB		 1139
1140/* stb stbu stbux stbx */
9a64fbe4 1141GEN_STS(b, 0x06);
79aceca5 1142/* sth sthu sthux sthx */
9a64fbe4 1143GEN_STS(h, 0x0C);
79aceca5 1144/* stw stwu stwux stwx */
9a64fbe4 1145GEN_STS(w, 0x04);
79aceca5
FB		 1146
1147/*** Integer load and store with byte reverse ***/
1148/* lhbrx */
9a64fbe4
FB		 1149OP_LD_TABLE(hbr);
1150GEN_LDX(hbr, 0x16, 0x18);
79aceca5 1151/* lwbrx */
9a64fbe4
FB		 1152OP_LD_TABLE(wbr);
1153GEN_LDX(wbr, 0x16, 0x10);
79aceca5 1154/* sthbrx */
9a64fbe4
FB		 1155OP_ST_TABLE(hbr);
1156GEN_STX(hbr, 0x16, 0x1C);
79aceca5 1157/* stwbrx */
9a64fbe4
FB		 1158OP_ST_TABLE(wbr);
1159GEN_STX(wbr, 0x16, 0x14);
79aceca5
FB		 1160
1161/*** Integer load and store multiple ***/
9a64fbe4
FB		 1162#if defined(CONFIG_USER_ONLY)
1163#define op_ldstm(name, reg) gen_op_##name##_raw(reg)
1164#else
1165#define op_ldstm(name, reg) (*gen_op_##name[ctx->mem_idx])(reg)
1166static GenOpFunc1 *gen_op_lmw[] = {
1167 &gen_op_lmw_user,
1168 &gen_op_lmw_kernel,
1169};
1170static GenOpFunc1 *gen_op_stmw[] = {
1171 &gen_op_stmw_user,
1172 &gen_op_stmw_kernel,
1173};
1174#endif
1175
79aceca5
FB		 1176/* lmw */
1177GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1178{
9a64fbe4
FB		 1179 int simm = SIMM(ctx->opcode);
1180
79aceca5 1181 if (rA(ctx->opcode) == 0) {
9a64fbe4 1182 gen_op_set_T0(simm);
79aceca5
FB		 1183 } else {
1184 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1185 if (simm != 0)
1186 gen_op_addi(simm);
79aceca5 1187 }
9a64fbe4 1188 op_ldstm(lmw, rD(ctx->opcode));
79aceca5
FB		 1189}
1190
1191/* stmw */
1192GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1193{
9a64fbe4
FB		 1194 int simm = SIMM(ctx->opcode);
1195
79aceca5 1196 if (rA(ctx->opcode) == 0) {
9a64fbe4 1197 gen_op_set_T0(simm);
79aceca5
FB		 1198 } else {
1199 gen_op_load_gpr_T0(rA(ctx->opcode));
9a64fbe4
FB		 1200 if (simm != 0)
1201 gen_op_addi(simm);
79aceca5 1202 }
9a64fbe4 1203 op_ldstm(stmw, rS(ctx->opcode));
79aceca5
FB		 1204}
1205
1206/*** Integer load and store strings ***/
9a64fbe4
FB		 1207#if defined(CONFIG_USER_ONLY)
1208#define op_ldsts(name, start) gen_op_##name##_raw(start)
1209#define op_ldstsx(name, rd, ra, rb) gen_op_##name##_raw(rd, ra, rb)
1210#else
1211#define op_ldsts(name, start) (*gen_op_##name[ctx->mem_idx])(start)
1212#define op_ldstsx(name, rd, ra, rb) (*gen_op_##name[ctx->mem_idx])(rd, ra, rb)
1213static GenOpFunc1 *gen_op_lswi[] = {
1214 &gen_op_lswi_user,
1215 &gen_op_lswi_kernel,
1216};
1217static GenOpFunc3 *gen_op_lswx[] = {
1218 &gen_op_lswx_user,
1219 &gen_op_lswx_kernel,
1220};
1221static GenOpFunc1 *gen_op_stsw[] = {
1222 &gen_op_stsw_user,
1223 &gen_op_stsw_kernel,
1224};
1225#endif
1226
79aceca5 1227/* lswi */
9a64fbe4
FB		 1228/* PPC32 specification says we must generate an exception if
1229 * rA is in the range of registers to be loaded.
1230 * In an other hand, IBM says this is valid, but rA won't be loaded.
1231 * For now, I'll follow the spec...
1232 */
79aceca5
FB		 1233GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_INTEGER)
1234{
1235 int nb = NB(ctx->opcode);
1236 int start = rD(ctx->opcode);
9a64fbe4 1237 int ra = rA(ctx->opcode);
79aceca5
FB		 1238 int nr;
1239
1240 if (nb == 0)
1241 nb = 32;
1242 nr = nb / 4;
297d8e62
FB		 1243 if (((start + nr) > 32 && start <= ra && (start + nr - 32) > ra) ||
1244 ((start + nr) <= 32 && start <= ra && (start + nr) > ra)) {
9fddaa0c
FB		 1245 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_LSWX);
1246 return;
297d8e62 1247 }
9a64fbe4 1248 if (ra == 0) {
79aceca5
FB		 1249 gen_op_set_T0(0);
1250 } else {
9a64fbe4 1251 gen_op_load_gpr_T0(ra);
79aceca5 1252 }
9a64fbe4
FB		 1253 gen_op_set_T1(nb);
1254 op_ldsts(lswi, start);
79aceca5
FB		 1255}
1256
1257/* lswx */
1258GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_INTEGER)
1259{
9a64fbe4
FB		 1260 int ra = rA(ctx->opcode);
1261 int rb = rB(ctx->opcode);
1262
1263 if (ra == 0) {
1264 gen_op_load_gpr_T0(rb);
1265 ra = rb;
79aceca5 1266 } else {
9a64fbe4
FB		 1267 gen_op_load_gpr_T0(ra);
1268 gen_op_load_gpr_T1(rb);
1269 gen_op_add();
79aceca5 1270 }
9a64fbe4
FB		 1271 gen_op_load_xer_bc();
1272 op_ldstsx(lswx, rD(ctx->opcode), ra, rb);
79aceca5
FB		 1273}
1274
1275/* stswi */
1276GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_INTEGER)
1277{
4b3686fa
FB		 1278 int nb = NB(ctx->opcode);
1279
79aceca5
FB		 1280 if (rA(ctx->opcode) == 0) {
1281 gen_op_set_T0(0);
1282 } else {
1283 gen_op_load_gpr_T0(rA(ctx->opcode));
1284 }
4b3686fa
FB		 1285 if (nb == 0)
1286 nb = 32;
1287 gen_op_set_T1(nb);
9a64fbe4 1288 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1289}
1290
1291/* stswx */
1292GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_INTEGER)
1293{
9a64fbe4
FB		 1294 int ra = rA(ctx->opcode);
1295
1296 if (ra == 0) {
1297 gen_op_load_gpr_T0(rB(ctx->opcode));
1298 ra = rB(ctx->opcode);
79aceca5 1299 } else {
9a64fbe4
FB		 1300 gen_op_load_gpr_T0(ra);
1301 gen_op_load_gpr_T1(rB(ctx->opcode));
1302 gen_op_add();
79aceca5 1303 }
9a64fbe4
FB		 1304 gen_op_load_xer_bc();
1305 op_ldsts(stsw, rS(ctx->opcode));
79aceca5
FB		 1306}
1307
1308/*** Memory synchronisation ***/
1309/* eieio */
1310GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FF0801, PPC_MEM)
1311{
79aceca5
FB		 1312}
1313
1314/* isync */
1315GEN_HANDLER(isync, 0x13, 0x16, 0xFF, 0x03FF0801, PPC_MEM)
1316{
79aceca5
FB		 1317}
1318
1319/* lwarx */
9a64fbe4 1320#if defined(CONFIG_USER_ONLY)
985a19d6 1321#define op_lwarx() gen_op_lwarx_raw()
9a64fbe4
FB		 1322#define op_stwcx() gen_op_stwcx_raw()
1323#else
985a19d6
FB		 1324#define op_lwarx() (*gen_op_lwarx[ctx->mem_idx])()
1325static GenOpFunc *gen_op_lwarx[] = {
1326 &gen_op_lwarx_user,
1327 &gen_op_lwarx_kernel,
1328};
9a64fbe4
FB		 1329#define op_stwcx() (*gen_op_stwcx[ctx->mem_idx])()
1330static GenOpFunc *gen_op_stwcx[] = {
1331 &gen_op_stwcx_user,
1332 &gen_op_stwcx_kernel,
1333};
1334#endif
1335
1336GEN_HANDLER(lwarx, 0x1F, 0x14, 0xFF, 0x00000001, PPC_RES)
79aceca5 1337{
79aceca5
FB		 1338 if (rA(ctx->opcode) == 0) {
1339 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1340 } else {
1341 gen_op_load_gpr_T0(rA(ctx->opcode));
1342 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1343 gen_op_add();
79aceca5 1344 }
985a19d6 1345 op_lwarx();
79aceca5 1346 gen_op_store_T1_gpr(rD(ctx->opcode));
79aceca5
FB		 1347}
1348
1349/* stwcx. */
9a64fbe4 1350GEN_HANDLER(stwcx_, 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
79aceca5 1351{
79aceca5
FB		 1352 if (rA(ctx->opcode) == 0) {
1353 gen_op_load_gpr_T0(rB(ctx->opcode));
79aceca5
FB		 1354 } else {
1355 gen_op_load_gpr_T0(rA(ctx->opcode));
1356 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 1357 gen_op_add();
79aceca5 1358 }
9a64fbe4
FB		 1359 gen_op_load_gpr_T1(rS(ctx->opcode));
1360 op_stwcx();
79aceca5
FB		 1361}
1362
1363/* sync */
1364GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x03FF0801, PPC_MEM)
1365{
79aceca5
FB		 1366}
1367
1368/*** Floating-point load ***/
9a64fbe4
FB		 1369#define GEN_LDF(width, opc) \
1370GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5
FB		 1371{ \
1372 uint32_t simm = SIMM(ctx->opcode); \
1373 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1374 gen_op_set_T0(simm); \
79aceca5
FB		 1375 } else { \
1376 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1377 if (simm != 0) \
1378 gen_op_addi(simm); \
79aceca5 1379 } \
9a64fbe4
FB		 1380 op_ldst(l##width); \
1381 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1382}
1383
9a64fbe4
FB		 1384#define GEN_LDUF(width, opc) \
1385GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5 1386{ \
9a64fbe4 1387 uint32_t simm = SIMM(ctx->opcode); \
79aceca5 1388 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1389 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1390 RET_INVAL(ctx); \
1391 return; \
9a64fbe4 1392 } \
79aceca5 1393 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1394 if (simm != 0) \
1395 gen_op_addi(simm); \
1396 op_ldst(l##width); \
1397 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1398 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1399}
1400
9a64fbe4
FB		 1401#define GEN_LDUXF(width, opc) \
1402GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1403{ \
1404 if (rA(ctx->opcode) == 0 || \
9a64fbe4 1405 rA(ctx->opcode) == rD(ctx->opcode)) { \
9fddaa0c
FB		 1406 RET_INVAL(ctx); \
1407 return; \
9a64fbe4 1408 } \
79aceca5
FB		 1409 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1410 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1411 gen_op_add(); \
1412 op_ldst(l##width); \
1413 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5 1414 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1415}
1416
9a64fbe4
FB		 1417#define GEN_LDXF(width, opc2, opc3) \
1418GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1419{ \
1420 if (rA(ctx->opcode) == 0) { \
1421 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1422 } else { \
1423 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1424 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1425 gen_op_add(); \
79aceca5 1426 } \
9a64fbe4
FB		 1427 op_ldst(l##width); \
1428 gen_op_store_FT1_fpr(rD(ctx->opcode)); \
79aceca5
FB		 1429}
1430
9a64fbe4
FB		 1431#define GEN_LDFS(width, op) \
1432OP_LD_TABLE(width); \
1433GEN_LDF(width, op | 0x20); \
1434GEN_LDUF(width, op | 0x21); \
1435GEN_LDUXF(width, op | 0x01); \
1436GEN_LDXF(width, 0x17, op | 0x00)
79aceca5
FB		 1437
1438/* lfd lfdu lfdux lfdx */
9a64fbe4 1439GEN_LDFS(fd, 0x12);
79aceca5 1440/* lfs lfsu lfsux lfsx */
9a64fbe4 1441GEN_LDFS(fs, 0x10);
79aceca5
FB		 1442
1443/*** Floating-point store ***/
1444#define GEN_STF(width, opc) \
9a64fbe4 1445GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5
FB		 1446{ \
1447 uint32_t simm = SIMM(ctx->opcode); \
1448 if (rA(ctx->opcode) == 0) { \
9a64fbe4 1449 gen_op_set_T0(simm); \
79aceca5
FB		 1450 } else { \
1451 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1452 if (simm != 0) \
1453 gen_op_addi(simm); \
79aceca5 1454 } \
9a64fbe4
FB		 1455 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1456 op_ldst(st##width); \
79aceca5
FB		 1457}
1458
9a64fbe4
FB		 1459#define GEN_STUF(width, opc) \
1460GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_INTEGER) \
79aceca5 1461{ \
9a64fbe4
FB		 1462 uint32_t simm = SIMM(ctx->opcode); \
1463 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1464 RET_INVAL(ctx); \
1465 return; \
9a64fbe4 1466 } \
79aceca5 1467 gen_op_load_gpr_T0(rA(ctx->opcode)); \
9a64fbe4
FB		 1468 if (simm != 0) \
1469 gen_op_addi(simm); \
1470 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1471 op_ldst(st##width); \
79aceca5 1472 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1473}
1474
9a64fbe4
FB		 1475#define GEN_STUXF(width, opc) \
1476GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, PPC_INTEGER) \
79aceca5 1477{ \
9a64fbe4 1478 if (rA(ctx->opcode) == 0) { \
9fddaa0c
FB		 1479 RET_INVAL(ctx); \
1480 return; \
9a64fbe4 1481 } \
79aceca5
FB		 1482 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1483 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4
FB		 1484 gen_op_add(); \
1485 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1486 op_ldst(st##width); \
79aceca5 1487 gen_op_store_T0_gpr(rA(ctx->opcode)); \
79aceca5
FB		 1488}
1489
9a64fbe4
FB		 1490#define GEN_STXF(width, opc2, opc3) \
1491GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, PPC_INTEGER) \
79aceca5
FB		 1492{ \
1493 if (rA(ctx->opcode) == 0) { \
1494 gen_op_load_gpr_T0(rB(ctx->opcode)); \
79aceca5
FB		 1495 } else { \
1496 gen_op_load_gpr_T0(rA(ctx->opcode)); \
1497 gen_op_load_gpr_T1(rB(ctx->opcode)); \
9a64fbe4 1498 gen_op_add(); \
79aceca5 1499 } \
9a64fbe4
FB		 1500 gen_op_load_fpr_FT1(rS(ctx->opcode)); \
1501 op_ldst(st##width); \
79aceca5
FB		 1502}
1503
9a64fbe4
FB		 1504#define GEN_STFS(width, op) \
1505OP_ST_TABLE(width); \
1506GEN_STF(width, op | 0x20); \
1507GEN_STUF(width, op | 0x21); \
1508GEN_STUXF(width, op | 0x01); \
1509GEN_STXF(width, 0x17, op | 0x00)
79aceca5
FB		 1510
1511/* stfd stfdu stfdux stfdx */
9a64fbe4 1512GEN_STFS(fd, 0x16);
79aceca5 1513/* stfs stfsu stfsux stfsx */
9a64fbe4 1514GEN_STFS(fs, 0x14);
79aceca5
FB		 1515
1516/* Optional: */
1517/* stfiwx */
1518GEN_HANDLER(stfiwx, 0x1F, 0x17, 0x1E, 0x00000001, PPC_FLOAT)
1519{
9fddaa0c 1520 RET_INVAL(ctx);
79aceca5
FB		 1521}
1522
1523/*** Branch ***/
79aceca5
FB		 1524
1525/* b ba bl bla */
1526GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1527{
38a64f9d
FB		 1528 uint32_t li, target;
1529
1530 /* sign extend LI */
1531 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
79aceca5
FB		 1532
1533 if (AA(ctx->opcode) == 0)
046d6672 1534 target = ctx->nip + li - 4;
79aceca5 1535 else
9a64fbe4 1536 target = li;
9a64fbe4 1537 if (LK(ctx->opcode)) {
046d6672 1538 gen_op_setlr(ctx->nip);
9a64fbe4 1539 }
e98a6e40 1540 gen_op_b((long)ctx->tb, target);
9a64fbe4 1541 ctx->exception = EXCP_BRANCH;
79aceca5
FB		 1542}
1543
e98a6e40
FB		 1544#define BCOND_IM 0
1545#define BCOND_LR 1
1546#define BCOND_CTR 2
1547
1548static inline void gen_bcond(DisasContext *ctx, int type)
1549{
1550 uint32_t target = 0;
1551 uint32_t bo = BO(ctx->opcode);
1552 uint32_t bi = BI(ctx->opcode);
1553 uint32_t mask;
1554 uint32_t li;
1555
e98a6e40
FB		 1556 if ((bo & 0x4) == 0)
1557 gen_op_dec_ctr();
1558 switch(type) {
1559 case BCOND_IM:
1560 li = s_ext16(BD(ctx->opcode));
1561 if (AA(ctx->opcode) == 0) {
046d6672 1562 target = ctx->nip + li - 4;
e98a6e40
FB		 1563 } else {
1564 target = li;
1565 }
1566 break;
1567 case BCOND_CTR:
1568 gen_op_movl_T1_ctr();
1569 break;
1570 default:
1571 case BCOND_LR:
1572 gen_op_movl_T1_lr();
1573 break;
1574 }
1575 if (LK(ctx->opcode)) {
046d6672 1576 gen_op_setlr(ctx->nip);
e98a6e40
FB		 1577 }
1578 if (bo & 0x10) {
1579 /* No CR condition */
1580 switch (bo & 0x6) {
1581 case 0:
1582 gen_op_test_ctr();
1583 break;
1584 case 2:
1585 gen_op_test_ctrz();
1586 break;
1587 default:
1588 case 4:
1589 case 6:
1590 if (type == BCOND_IM) {
1591 gen_op_b((long)ctx->tb, target);
1592 } else {
1593 gen_op_b_T1();
e98a6e40
FB		 1594 }
1595 goto no_test;
1596 }
1597 } else {
1598 mask = 1 << (3 - (bi & 0x03));
1599 gen_op_load_crf_T0(bi >> 2);
1600 if (bo & 0x8) {
1601 switch (bo & 0x6) {
1602 case 0:
1603 gen_op_test_ctr_true(mask);
1604 break;
1605 case 2:
1606 gen_op_test_ctrz_true(mask);
1607 break;
1608 default:
1609 case 4:
1610 case 6:
1611 gen_op_test_true(mask);
1612 break;
1613 }
1614 } else {
1615 switch (bo & 0x6) {
1616 case 0:
1617 gen_op_test_ctr_false(mask);
1618 break;
1619 case 2:
1620 gen_op_test_ctrz_false(mask);
1621 break;
1622 default:
1623 case 4:
1624 case 6:
1625 gen_op_test_false(mask);
1626 break;
1627 }
1628 }
1629 }
1630 if (type == BCOND_IM) {
046d6672 1631 gen_op_btest((long)ctx->tb, target, ctx->nip);
e98a6e40 1632 } else {
046d6672 1633 gen_op_btest_T1(ctx->nip);
e98a6e40
FB		 1634 }
1635 no_test:
1636 ctx->exception = EXCP_BRANCH;
1637}
1638
1639GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1640{
1641 gen_bcond(ctx, BCOND_IM);
1642}
1643
1644GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW)
1645{
1646 gen_bcond(ctx, BCOND_CTR);
1647}
1648
1649GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW)
1650{
1651 gen_bcond(ctx, BCOND_LR);
1652}
79aceca5
FB		 1653
1654/*** Condition register logical ***/
1655#define GEN_CRLOGIC(op, opc) \
1656GEN_HANDLER(cr##op, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) \
1657{ \
1658 gen_op_load_crf_T0(crbA(ctx->opcode) >> 2); \
1659 gen_op_getbit_T0(3 - (crbA(ctx->opcode) & 0x03)); \
1660 gen_op_load_crf_T1(crbB(ctx->opcode) >> 2); \
1661 gen_op_getbit_T1(3 - (crbB(ctx->opcode) & 0x03)); \
1662 gen_op_##op(); \
1663 gen_op_load_crf_T1(crbD(ctx->opcode) >> 2); \
1664 gen_op_setcrfbit(~(1 << (3 - (crbD(ctx->opcode) & 0x03))), \
1665 3 - (crbD(ctx->opcode) & 0x03)); \
1666 gen_op_store_T1_crf(crbD(ctx->opcode) >> 2); \
79aceca5
FB		 1667}
1668
1669/* crand */
1670GEN_CRLOGIC(and, 0x08)
1671/* crandc */
1672GEN_CRLOGIC(andc, 0x04)
1673/* creqv */
1674GEN_CRLOGIC(eqv, 0x09)
1675/* crnand */
1676GEN_CRLOGIC(nand, 0x07)
1677/* crnor */
1678GEN_CRLOGIC(nor, 0x01)
1679/* cror */
1680GEN_CRLOGIC(or, 0x0E)
1681/* crorc */
1682GEN_CRLOGIC(orc, 0x0D)
1683/* crxor */
1684GEN_CRLOGIC(xor, 0x06)
1685/* mcrf */
1686GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER)
1687{
1688 gen_op_load_crf_T0(crfS(ctx->opcode));
1689 gen_op_store_T0_crf(crfD(ctx->opcode));
79aceca5
FB		 1690}
1691
1692/*** System linkage ***/
1693/* rfi (supervisor only) */
1694GEN_HANDLER(rfi, 0x13, 0x12, 0xFF, 0x03FF8001, PPC_FLOW)
1695{
9a64fbe4 1696#if defined(CONFIG_USER_ONLY)
9fddaa0c 1697 RET_PRIVOPC(ctx);
9a64fbe4
FB		 1698#else
1699 /* Restore CPU state */
1700 if (!ctx->supervisor) {
9fddaa0c
FB		 1701 RET_PRIVOPC(ctx);
1702 return;
9a64fbe4
FB		 1703 }
1704 gen_op_rfi();
9fddaa0c 1705 RET_EXCP(ctx, EXCP_RFI, 0);
9a64fbe4 1706#endif
79aceca5
FB		 1707}
1708
1709/* sc */
1710GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFFFFD, PPC_FLOW)
1711{
9a64fbe4 1712#if defined(CONFIG_USER_ONLY)
9fddaa0c 1713 RET_EXCP(ctx, EXCP_SYSCALL_USER, 0);
9a64fbe4 1714#else
9fddaa0c 1715 RET_EXCP(ctx, EXCP_SYSCALL, 0);
9a64fbe4 1716#endif
79aceca5
FB		 1717}
1718
1719/*** Trap ***/
1720/* tw */
1721GEN_HANDLER(tw, 0x1F, 0x04, 0xFF, 0x00000001, PPC_FLOW)
1722{
9a64fbe4
FB		 1723 gen_op_load_gpr_T0(rA(ctx->opcode));
1724 gen_op_load_gpr_T1(rB(ctx->opcode));
1725 gen_op_tw(TO(ctx->opcode));
79aceca5
FB		 1726}
1727
1728/* twi */
1729GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
1730{
9a64fbe4
FB		 1731 gen_op_load_gpr_T0(rA(ctx->opcode));
1732#if 0
1733 printf("%s: param=0x%04x T0=0x%04x\n", __func__,
1734 SIMM(ctx->opcode), TO(ctx->opcode));
1735#endif
1736 gen_op_twi(SIMM(ctx->opcode), TO(ctx->opcode));
79aceca5
FB		 1737}
1738
1739/*** Processor control ***/
1740static inline int check_spr_access (int spr, int rw, int supervisor)
1741{
1742 uint32_t rights = spr_access[spr >> 1] >> (4 * (spr & 1));
1743
9a64fbe4
FB		 1744#if 0
1745 if (spr != LR && spr != CTR) {
1746 if (loglevel > 0) {
1747 fprintf(logfile, "%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1748 SPR_ENCODE(spr), supervisor, rw, rights,
1749 (rights >> ((2 * supervisor) + rw)) & 1);
1750 } else {
1751 printf("%s reg=%d s=%d rw=%d r=0x%02x 0x%02x\n", __func__,
1752 SPR_ENCODE(spr), supervisor, rw, rights,
1753 (rights >> ((2 * supervisor) + rw)) & 1);
1754 }
1755 }
1756#endif
1757 if (rights == 0)
1758 return -1;
79aceca5
FB		 1759 rights = rights >> (2 * supervisor);
1760 rights = rights >> rw;
1761
1762 return rights & 1;
1763}
1764
1765/* mcrxr */
1766GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC)
1767{
1768 gen_op_load_xer_cr();
1769 gen_op_store_T0_crf(crfD(ctx->opcode));
1770 gen_op_clear_xer_cr();
79aceca5
FB		 1771}
1772
1773/* mfcr */
1774GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x001FF801, PPC_MISC)
1775{
1776 gen_op_load_cr();
1777 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1778}
1779
1780/* mfmsr */
1781GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
1782{
9a64fbe4 1783#if defined(CONFIG_USER_ONLY)
9fddaa0c 1784 RET_PRIVREG(ctx);
9a64fbe4
FB		 1785#else
1786 if (!ctx->supervisor) {
9fddaa0c
FB		 1787 RET_PRIVREG(ctx);
1788 return;
9a64fbe4 1789 }
79aceca5
FB		 1790 gen_op_load_msr();
1791 gen_op_store_T0_gpr(rD(ctx->opcode));
9a64fbe4 1792#endif
79aceca5
FB		 1793}
1794
1795/* mfspr */
1796GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC)
1797{
1798 uint32_t sprn = SPR(ctx->opcode);
1799
9a64fbe4
FB		 1800#if defined(CONFIG_USER_ONLY)
1801 switch (check_spr_access(sprn, 0, 0))
1802#else
1803 switch (check_spr_access(sprn, 0, ctx->supervisor))
1804#endif
1805 {
1806 case -1:
9fddaa0c
FB		 1807 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
1808 return;
9a64fbe4 1809 case 0:
9fddaa0c
FB		 1810 RET_PRIVREG(ctx);
1811 return;
9a64fbe4
FB		 1812 default:
1813 break;
79aceca5 1814 }
9a64fbe4
FB		 1815 switch (sprn) {
1816 case XER:
79aceca5
FB		 1817 gen_op_load_xer();
1818 break;
9a64fbe4
FB		 1819 case LR:
1820 gen_op_load_lr();
1821 break;
1822 case CTR:
1823 gen_op_load_ctr();
1824 break;
1825 case IBAT0U:
1826 gen_op_load_ibat(0, 0);
1827 break;
1828 case IBAT1U:
1829 gen_op_load_ibat(0, 1);
1830 break;
1831 case IBAT2U:
1832 gen_op_load_ibat(0, 2);
1833 break;
1834 case IBAT3U:
1835 gen_op_load_ibat(0, 3);
1836 break;
1837 case IBAT4U:
1838 gen_op_load_ibat(0, 4);
1839 break;
1840 case IBAT5U:
1841 gen_op_load_ibat(0, 5);
1842 break;
1843 case IBAT6U:
1844 gen_op_load_ibat(0, 6);
1845 break;
1846 case IBAT7U:
1847 gen_op_load_ibat(0, 7);
1848 break;
1849 case IBAT0L:
1850 gen_op_load_ibat(1, 0);
1851 break;
1852 case IBAT1L:
1853 gen_op_load_ibat(1, 1);
1854 break;
1855 case IBAT2L:
1856 gen_op_load_ibat(1, 2);
1857 break;
1858 case IBAT3L:
1859 gen_op_load_ibat(1, 3);
1860 break;
1861 case IBAT4L:
1862 gen_op_load_ibat(1, 4);
1863 break;
1864 case IBAT5L:
1865 gen_op_load_ibat(1, 5);
1866 break;
1867 case IBAT6L:
1868 gen_op_load_ibat(1, 6);
1869 break;
1870 case IBAT7L:
1871 gen_op_load_ibat(1, 7);
1872 break;
1873 case DBAT0U:
1874 gen_op_load_dbat(0, 0);
1875 break;
1876 case DBAT1U:
1877 gen_op_load_dbat(0, 1);
1878 break;
1879 case DBAT2U:
1880 gen_op_load_dbat(0, 2);
1881 break;
1882 case DBAT3U:
1883 gen_op_load_dbat(0, 3);
1884 break;
1885 case DBAT4U:
1886 gen_op_load_dbat(0, 4);
1887 break;
1888 case DBAT5U:
1889 gen_op_load_dbat(0, 5);
1890 break;
1891 case DBAT6U:
1892 gen_op_load_dbat(0, 6);
1893 break;
1894 case DBAT7U:
1895 gen_op_load_dbat(0, 7);
1896 break;
1897 case DBAT0L:
1898 gen_op_load_dbat(1, 0);
1899 break;
1900 case DBAT1L:
1901 gen_op_load_dbat(1, 1);
1902 break;
1903 case DBAT2L:
1904 gen_op_load_dbat(1, 2);
1905 break;
1906 case DBAT3L:
1907 gen_op_load_dbat(1, 3);
1908 break;
1909 case DBAT4L:
1910 gen_op_load_dbat(1, 4);
1911 break;
1912 case DBAT5L:
1913 gen_op_load_dbat(1, 5);
1914 break;
1915 case DBAT6L:
1916 gen_op_load_dbat(1, 6);
1917 break;
1918 case DBAT7L:
1919 gen_op_load_dbat(1, 7);
1920 break;
1921 case SDR1:
1922 gen_op_load_sdr1();
1923 break;
1924 case V_TBL:
9fddaa0c 1925 gen_op_load_tbl();
79aceca5 1926 break;
9a64fbe4 1927 case V_TBU:
9fddaa0c 1928 gen_op_load_tbu();
9a64fbe4
FB		 1929 break;
1930 case DECR:
9fddaa0c 1931 gen_op_load_decr();
79aceca5
FB		 1932 break;
1933 default:
1934 gen_op_load_spr(sprn);
1935 break;
1936 }
9a64fbe4 1937 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1938}
1939
1940/* mftb */
1941GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MISC)
1942{
1943 uint32_t sprn = SPR(ctx->opcode);
1944
79aceca5 1945 /* We need to update the time base before reading it */
9a64fbe4
FB		 1946 switch (sprn) {
1947 case V_TBL:
9fddaa0c 1948 gen_op_load_tbl();
79aceca5 1949 break;
9a64fbe4 1950 case V_TBU:
9fddaa0c 1951 gen_op_load_tbu();
79aceca5
FB		 1952 break;
1953 default:
9fddaa0c
FB		 1954 RET_INVAL(ctx);
1955 return;
79aceca5 1956 }
9a64fbe4 1957 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 1958}
1959
1960/* mtcrf */
1961GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00100801, PPC_MISC)
1962{
1963 gen_op_load_gpr_T0(rS(ctx->opcode));
1964 gen_op_store_cr(CRM(ctx->opcode));
79aceca5
FB		 1965}
1966
1967/* mtmsr */
1968GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
1969{
9a64fbe4 1970#if defined(CONFIG_USER_ONLY)
9fddaa0c 1971 RET_PRIVREG(ctx);
9a64fbe4
FB		 1972#else
1973 if (!ctx->supervisor) {
9fddaa0c
FB		 1974 RET_PRIVREG(ctx);
1975 return;
9a64fbe4 1976 }
79aceca5
FB		 1977 gen_op_load_gpr_T0(rS(ctx->opcode));
1978 gen_op_store_msr();
1979 /* Must stop the translation as machine state (may have) changed */
9fddaa0c 1980 RET_MTMSR(ctx);
9a64fbe4 1981#endif
79aceca5
FB		 1982}
1983
1984/* mtspr */
1985GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
1986{
1987 uint32_t sprn = SPR(ctx->opcode);
1988
9a64fbe4
FB		 1989#if 0
1990 if (loglevel > 0) {
1991 fprintf(logfile, "MTSPR %d src=%d (%d)\n", SPR_ENCODE(sprn),
1992 rS(ctx->opcode), sprn);
1993 }
1994#endif
1995#if defined(CONFIG_USER_ONLY)
1996 switch (check_spr_access(sprn, 1, 0))
1997#else
1998 switch (check_spr_access(sprn, 1, ctx->supervisor))
1999#endif
2000 {
2001 case -1:
9fddaa0c 2002 RET_EXCP(ctx, EXCP_PROGRAM, EXCP_INVAL | EXCP_INVAL_SPR);
9a64fbe4
FB		 2003 break;
2004 case 0:
9fddaa0c 2005 RET_PRIVREG(ctx);
9a64fbe4
FB		 2006 break;
2007 default:
2008 break;
2009 }
79aceca5 2010 gen_op_load_gpr_T0(rS(ctx->opcode));
9a64fbe4
FB		 2011 switch (sprn) {
2012 case XER:
79aceca5 2013 gen_op_store_xer();
9a64fbe4
FB		 2014 break;
2015 case LR:
9a64fbe4
FB		 2016 gen_op_store_lr();
2017 break;
2018 case CTR:
2019 gen_op_store_ctr();
2020 break;
2021 case IBAT0U:
2022 gen_op_store_ibat(0, 0);
4b3686fa 2023 RET_MTMSR(ctx);
9a64fbe4
FB		 2024 break;
2025 case IBAT1U:
2026 gen_op_store_ibat(0, 1);
4b3686fa 2027 RET_MTMSR(ctx);
9a64fbe4
FB		 2028 break;
2029 case IBAT2U:
2030 gen_op_store_ibat(0, 2);
4b3686fa 2031 RET_MTMSR(ctx);
9a64fbe4
FB		 2032 break;
2033 case IBAT3U:
2034 gen_op_store_ibat(0, 3);
4b3686fa 2035 RET_MTMSR(ctx);
9a64fbe4
FB		 2036 break;
2037 case IBAT4U:
2038 gen_op_store_ibat(0, 4);
4b3686fa 2039 RET_MTMSR(ctx);
9a64fbe4
FB		 2040 break;
2041 case IBAT5U:
2042 gen_op_store_ibat(0, 5);
4b3686fa 2043 RET_MTMSR(ctx);
9a64fbe4
FB		 2044 break;
2045 case IBAT6U:
2046 gen_op_store_ibat(0, 6);
4b3686fa 2047 RET_MTMSR(ctx);
9a64fbe4
FB		 2048 break;
2049 case IBAT7U:
2050 gen_op_store_ibat(0, 7);
4b3686fa 2051 RET_MTMSR(ctx);
9a64fbe4
FB		 2052 break;
2053 case IBAT0L:
2054 gen_op_store_ibat(1, 0);
4b3686fa 2055 RET_MTMSR(ctx);
9a64fbe4
FB		 2056 break;
2057 case IBAT1L:
2058 gen_op_store_ibat(1, 1);
4b3686fa 2059 RET_MTMSR(ctx);
9a64fbe4
FB		 2060 break;
2061 case IBAT2L:
2062 gen_op_store_ibat(1, 2);
4b3686fa 2063 RET_MTMSR(ctx);
9a64fbe4
FB		 2064 break;
2065 case IBAT3L:
2066 gen_op_store_ibat(1, 3);
4b3686fa 2067 RET_MTMSR(ctx);
9a64fbe4
FB		 2068 break;
2069 case IBAT4L:
2070 gen_op_store_ibat(1, 4);
4b3686fa 2071 RET_MTMSR(ctx);
9a64fbe4
FB		 2072 break;
2073 case IBAT5L:
2074 gen_op_store_ibat(1, 5);
4b3686fa 2075 RET_MTMSR(ctx);
9a64fbe4
FB		 2076 break;
2077 case IBAT6L:
2078 gen_op_store_ibat(1, 6);
4b3686fa 2079 RET_MTMSR(ctx);
9a64fbe4
FB		 2080 break;
2081 case IBAT7L:
2082 gen_op_store_ibat(1, 7);
4b3686fa 2083 RET_MTMSR(ctx);
9a64fbe4
FB		 2084 break;
2085 case DBAT0U:
2086 gen_op_store_dbat(0, 0);
4b3686fa 2087 RET_MTMSR(ctx);
9a64fbe4
FB		 2088 break;
2089 case DBAT1U:
2090 gen_op_store_dbat(0, 1);
4b3686fa 2091 RET_MTMSR(ctx);
9a64fbe4
FB		 2092 break;
2093 case DBAT2U:
2094 gen_op_store_dbat(0, 2);
4b3686fa 2095 RET_MTMSR(ctx);
9a64fbe4
FB		 2096 break;
2097 case DBAT3U:
2098 gen_op_store_dbat(0, 3);
4b3686fa 2099 RET_MTMSR(ctx);
9a64fbe4
FB		 2100 break;
2101 case DBAT4U:
2102 gen_op_store_dbat(0, 4);
4b3686fa 2103 RET_MTMSR(ctx);
9a64fbe4
FB		 2104 break;
2105 case DBAT5U:
2106 gen_op_store_dbat(0, 5);
4b3686fa 2107 RET_MTMSR(ctx);
9a64fbe4
FB		 2108 break;
2109 case DBAT6U:
2110 gen_op_store_dbat(0, 6);
4b3686fa 2111 RET_MTMSR(ctx);
9a64fbe4
FB		 2112 break;
2113 case DBAT7U:
2114 gen_op_store_dbat(0, 7);
4b3686fa 2115 RET_MTMSR(ctx);
9a64fbe4
FB		 2116 break;
2117 case DBAT0L:
2118 gen_op_store_dbat(1, 0);
4b3686fa 2119 RET_MTMSR(ctx);
9a64fbe4
FB		 2120 break;
2121 case DBAT1L:
2122 gen_op_store_dbat(1, 1);
4b3686fa 2123 RET_MTMSR(ctx);
9a64fbe4
FB		 2124 break;
2125 case DBAT2L:
2126 gen_op_store_dbat(1, 2);
4b3686fa 2127 RET_MTMSR(ctx);
9a64fbe4
FB		 2128 break;
2129 case DBAT3L:
2130 gen_op_store_dbat(1, 3);
4b3686fa 2131 RET_MTMSR(ctx);
9a64fbe4
FB		 2132 break;
2133 case DBAT4L:
2134 gen_op_store_dbat(1, 4);
4b3686fa 2135 RET_MTMSR(ctx);
9a64fbe4
FB		 2136 break;
2137 case DBAT5L:
2138 gen_op_store_dbat(1, 5);
4b3686fa 2139 RET_MTMSR(ctx);
9a64fbe4
FB		 2140 break;
2141 case DBAT6L:
2142 gen_op_store_dbat(1, 6);
4b3686fa 2143 RET_MTMSR(ctx);
9a64fbe4
FB		 2144 break;
2145 case DBAT7L:
2146 gen_op_store_dbat(1, 7);
4b3686fa 2147 RET_MTMSR(ctx);
9a64fbe4
FB		 2148 break;
2149 case SDR1:
2150 gen_op_store_sdr1();
4b3686fa 2151 RET_MTMSR(ctx);
9a64fbe4
FB		 2152 break;
2153 case O_TBL:
9fddaa0c 2154 gen_op_store_tbl();
9a64fbe4
FB		 2155 break;
2156 case O_TBU:
9fddaa0c 2157 gen_op_store_tbu();
9a64fbe4
FB		 2158 break;
2159 case DECR:
2160 gen_op_store_decr();
9a64fbe4 2161 break;
4b3686fa
FB		 2162#if 0
2163 case HID0:
2164 gen_op_store_hid0();
2165 break;
2166#endif
9a64fbe4 2167 default:
79aceca5 2168 gen_op_store_spr(sprn);
9a64fbe4 2169 break;
79aceca5 2170 }
79aceca5
FB		 2171}
2172
2173/*** Cache management ***/
2174/* For now, all those will be implemented as nop:
2175 * this is valid, regarding the PowerPC specs...
9a64fbe4 2176 * We just have to flush tb while invalidating instruction cache lines...
79aceca5
FB		 2177 */
2178/* dcbf */
9a64fbe4 2179GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03E00001, PPC_CACHE)
79aceca5 2180{
a541f297
FB		 2181 if (rA(ctx->opcode) == 0) {
2182 gen_op_load_gpr_T0(rB(ctx->opcode));
2183 } else {
2184 gen_op_load_gpr_T0(rA(ctx->opcode));
2185 gen_op_load_gpr_T1(rB(ctx->opcode));
2186 gen_op_add();
2187 }
2188 op_ldst(lbz);
79aceca5
FB		 2189}
2190
2191/* dcbi (Supervisor only) */
9a64fbe4 2192GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
79aceca5 2193{
a541f297 2194#if defined(CONFIG_USER_ONLY)
9fddaa0c 2195 RET_PRIVOPC(ctx);
a541f297
FB		 2196#else
2197 if (!ctx->supervisor) {
9fddaa0c
FB		 2198 RET_PRIVOPC(ctx);
2199 return;
9a64fbe4 2200 }
a541f297
FB		 2201 if (rA(ctx->opcode) == 0) {
2202 gen_op_load_gpr_T0(rB(ctx->opcode));
2203 } else {
2204 gen_op_load_gpr_T0(rA(ctx->opcode));
2205 gen_op_load_gpr_T1(rB(ctx->opcode));
2206 gen_op_add();
2207 }
2208 op_ldst(lbz);
2209 op_ldst(stb);
2210#endif
79aceca5
FB		 2211}
2212
2213/* dcdst */
9a64fbe4 2214GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE)
79aceca5 2215{
a541f297
FB		 2216 if (rA(ctx->opcode) == 0) {
2217 gen_op_load_gpr_T0(rB(ctx->opcode));
2218 } else {
2219 gen_op_load_gpr_T0(rA(ctx->opcode));
2220 gen_op_load_gpr_T1(rB(ctx->opcode));
2221 gen_op_add();
2222 }
2223 op_ldst(lbz);
79aceca5
FB		 2224}
2225
2226/* dcbt */
9a64fbe4 2227GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x03E00001, PPC_CACHE)
79aceca5 2228{
79aceca5
FB		 2229}
2230
2231/* dcbtst */
9a64fbe4 2232GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE)
79aceca5 2233{
79aceca5
FB		 2234}
2235
2236/* dcbz */
9a64fbe4
FB		 2237#if defined(CONFIG_USER_ONLY)
2238#define op_dcbz() gen_op_dcbz_raw()
2239#else
2240#define op_dcbz() (*gen_op_dcbz[ctx->mem_idx])()
2241static GenOpFunc *gen_op_dcbz[] = {
2242 &gen_op_dcbz_user,
2243 &gen_op_dcbz_kernel,
2244};
2245#endif
2246
2247GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE)
79aceca5 2248{
fb0eaffc
FB		 2249 if (rA(ctx->opcode) == 0) {
2250 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2251 } else {
2252 gen_op_load_gpr_T0(rA(ctx->opcode));
2253 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2254 gen_op_add();
fb0eaffc 2255 }
9a64fbe4 2256 op_dcbz();
4b3686fa 2257 gen_op_check_reservation();
79aceca5
FB		 2258}
2259
2260/* icbi */
9a64fbe4 2261GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE)
79aceca5 2262{
fb0eaffc
FB		 2263 if (rA(ctx->opcode) == 0) {
2264 gen_op_load_gpr_T0(rB(ctx->opcode));
fb0eaffc
FB		 2265 } else {
2266 gen_op_load_gpr_T0(rA(ctx->opcode));
2267 gen_op_load_gpr_T1(rB(ctx->opcode));
9a64fbe4 2268 gen_op_add();
fb0eaffc 2269 }
9a64fbe4 2270 gen_op_icbi();
79aceca5
FB		 2271}
2272
2273/* Optional: */
2274/* dcba */
9a64fbe4 2275GEN_HANDLER(dcba, 0x1F, 0x16, 0x07, 0x03E00001, PPC_CACHE_OPT)
79aceca5 2276{
79aceca5
FB		 2277}
2278
2279/*** Segment register manipulation ***/
2280/* Supervisor only: */
2281/* mfsr */
2282GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
2283{
9a64fbe4 2284#if defined(CONFIG_USER_ONLY)
9fddaa0c 2285 RET_PRIVREG(ctx);
9a64fbe4
FB		 2286#else
2287 if (!ctx->supervisor) {
9fddaa0c
FB		 2288 RET_PRIVREG(ctx);
2289 return;
9a64fbe4
FB		 2290 }
2291 gen_op_load_sr(SR(ctx->opcode));
2292 gen_op_store_T0_gpr(rD(ctx->opcode));
2293#endif
79aceca5
FB		 2294}
2295
2296/* mfsrin */
9a64fbe4 2297GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
79aceca5 2298{
9a64fbe4 2299#if defined(CONFIG_USER_ONLY)
9fddaa0c 2300 RET_PRIVREG(ctx);
9a64fbe4
FB		 2301#else
2302 if (!ctx->supervisor) {
9fddaa0c
FB		 2303 RET_PRIVREG(ctx);
2304 return;
9a64fbe4
FB		 2305 }
2306 gen_op_load_gpr_T1(rB(ctx->opcode));
2307 gen_op_load_srin();
2308 gen_op_store_T0_gpr(rD(ctx->opcode));
2309#endif
79aceca5
FB		 2310}
2311
2312/* mtsr */
e63c59cb 2313GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
79aceca5 2314{
9a64fbe4 2315#if defined(CONFIG_USER_ONLY)
9fddaa0c 2316 RET_PRIVREG(ctx);
9a64fbe4
FB		 2317#else
2318 if (!ctx->supervisor) {
9fddaa0c
FB		 2319 RET_PRIVREG(ctx);
2320 return;
9a64fbe4
FB		 2321 }
2322 gen_op_load_gpr_T0(rS(ctx->opcode));
2323 gen_op_store_sr(SR(ctx->opcode));
9a64fbe4 2324#endif
79aceca5
FB		 2325}
2326
2327/* mtsrin */
9a64fbe4 2328GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
79aceca5 2329{
9a64fbe4 2330#if defined(CONFIG_USER_ONLY)
9fddaa0c 2331 RET_PRIVREG(ctx);
9a64fbe4
FB		 2332#else
2333 if (!ctx->supervisor) {
9fddaa0c
FB		 2334 RET_PRIVREG(ctx);
2335 return;
9a64fbe4
FB		 2336 }
2337 gen_op_load_gpr_T0(rS(ctx->opcode));
2338 gen_op_load_gpr_T1(rB(ctx->opcode));
2339 gen_op_store_srin();
9a64fbe4 2340#endif
79aceca5
FB		 2341}
2342
2343/*** Lookaside buffer management ***/
2344/* Optional & supervisor only: */
2345/* tlbia */
9a64fbe4 2346GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_OPT)
79aceca5 2347{
9a64fbe4 2348#if defined(CONFIG_USER_ONLY)
9fddaa0c 2349 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2350#else
2351 if (!ctx->supervisor) {
9fddaa0c
FB		 2352 if (loglevel)
2353 fprintf(logfile, "%s: ! supervisor\n", __func__);
2354 RET_PRIVOPC(ctx);
2355 return;
9a64fbe4
FB		 2356 }
2357 gen_op_tlbia();
4b3686fa 2358 RET_MTMSR(ctx);
9a64fbe4 2359#endif
79aceca5
FB		 2360}
2361
2362/* tlbie */
9a64fbe4 2363GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM)
79aceca5 2364{
9a64fbe4 2365#if defined(CONFIG_USER_ONLY)
9fddaa0c 2366 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2367#else
2368 if (!ctx->supervisor) {
9fddaa0c
FB		 2369 RET_PRIVOPC(ctx);
2370 return;
9a64fbe4
FB		 2371 }
2372 gen_op_load_gpr_T0(rB(ctx->opcode));
2373 gen_op_tlbie();
4b3686fa 2374 RET_MTMSR(ctx);
9a64fbe4 2375#endif
79aceca5
FB		 2376}
2377
2378/* tlbsync */
e63c59cb 2379GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM)
79aceca5 2380{
9a64fbe4 2381#if defined(CONFIG_USER_ONLY)
9fddaa0c 2382 RET_PRIVOPC(ctx);
9a64fbe4
FB		 2383#else
2384 if (!ctx->supervisor) {
9fddaa0c
FB		 2385 RET_PRIVOPC(ctx);
2386 return;
9a64fbe4
FB		 2387 }
2388 /* This has no effect: it should ensure that all previous
2389 * tlbie have completed
2390 */
4b3686fa 2391 RET_MTMSR(ctx);
9a64fbe4 2392#endif
79aceca5
FB		 2393}
2394
2395/*** External control ***/
2396/* Optional: */
2397/* eciwx */
9a64fbe4
FB		 2398#if defined(CONFIG_USER_ONLY)
2399#define op_eciwx() gen_op_eciwx_raw()
2400#define op_ecowx() gen_op_ecowx_raw()
2401#else
2402#define op_eciwx() (*gen_op_eciwx[ctx->mem_idx])()
2403#define op_ecowx() (*gen_op_ecowx[ctx->mem_idx])()
2404static GenOpFunc *gen_op_eciwx[] = {
2405 &gen_op_eciwx_user,
2406 &gen_op_eciwx_kernel,
2407};
2408static GenOpFunc *gen_op_ecowx[] = {
2409 &gen_op_ecowx_user,
2410 &gen_op_ecowx_kernel,
2411};
2412#endif
2413
79aceca5
FB		 2414GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
2415{
9a64fbe4
FB		 2416 /* Should check EAR[E] & alignment ! */
2417 if (rA(ctx->opcode) == 0) {
2418 gen_op_load_gpr_T0(rB(ctx->opcode));
2419 } else {
2420 gen_op_load_gpr_T0(rA(ctx->opcode));
2421 gen_op_load_gpr_T1(rB(ctx->opcode));
2422 gen_op_add();
2423 }
2424 op_eciwx();
2425 gen_op_store_T0_gpr(rD(ctx->opcode));
79aceca5
FB		 2426}
2427
2428/* ecowx */
2429GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
2430{
9a64fbe4
FB		 2431 /* Should check EAR[E] & alignment ! */
2432 if (rA(ctx->opcode) == 0) {
2433 gen_op_load_gpr_T0(rB(ctx->opcode));
2434 } else {
2435 gen_op_load_gpr_T0(rA(ctx->opcode));
2436 gen_op_load_gpr_T1(rB(ctx->opcode));
2437 gen_op_add();
2438 }
2439 gen_op_load_gpr_T2(rS(ctx->opcode));
2440 op_ecowx();
79aceca5
FB		 2441}
2442
2443/* End opcode list */
2444GEN_OPCODE_MARK(end);
2445
2446/*****************************************************************************/
9a64fbe4 2447#include <stdlib.h>
79aceca5 2448#include <string.h>
9a64fbe4
FB		 2449
2450int fflush (FILE *stream);
79aceca5
FB		 2451
2452/* Main ppc opcodes table:
2453 * at init, all opcodes are invalids
2454 */
2455static opc_handler_t *ppc_opcodes[0x40];
2456
2457/* Opcode types */
2458enum {
2459 PPC_DIRECT = 0, /* Opcode routine */
2460 PPC_INDIRECT = 1, /* Indirect opcode table */
2461};
2462
2463static inline int is_indirect_opcode (void *handler)
2464{
2465 return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2466}
2467
2468static inline opc_handler_t **ind_table(void *handler)
2469{
2470 return (opc_handler_t **)((unsigned long)handler & ~3);
2471}
2472
9a64fbe4 2473/* Instruction table creation */
79aceca5
FB		 2474/* Opcodes tables creation */
2475static void fill_new_table (opc_handler_t **table, int len)
2476{
2477 int i;
2478
2479 for (i = 0; i < len; i++)
2480 table[i] = &invalid_handler;
2481}
2482
2483static int create_new_table (opc_handler_t **table, unsigned char idx)
2484{
2485 opc_handler_t **tmp;
2486
2487 tmp = malloc(0x20 * sizeof(opc_handler_t));
2488 if (tmp == NULL)
2489 return -1;
2490 fill_new_table(tmp, 0x20);
2491 table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2492
2493 return 0;
2494}
2495
2496static int insert_in_table (opc_handler_t **table, unsigned char idx,
2497 opc_handler_t *handler)
2498{
2499 if (table[idx] != &invalid_handler)
2500 return -1;
2501 table[idx] = handler;
2502
2503 return 0;
2504}
2505
9a64fbe4
FB		 2506static int register_direct_insn (opc_handler_t **ppc_opcodes,
2507 unsigned char idx, opc_handler_t *handler)
79aceca5
FB		 2508{
2509 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
9a64fbe4 2510 printf("*** ERROR: opcode %02x already assigned in main "
79aceca5
FB		 2511 "opcode table\n", idx);
2512 return -1;
2513 }
2514
2515 return 0;
2516}
2517
2518static int register_ind_in_table (opc_handler_t **table,
2519 unsigned char idx1, unsigned char idx2,
2520 opc_handler_t *handler)
2521{
2522 if (table[idx1] == &invalid_handler) {
2523 if (create_new_table(table, idx1) < 0) {
9a64fbe4 2524 printf("*** ERROR: unable to create indirect table "
79aceca5
FB		 2525 "idx=%02x\n", idx1);
2526 return -1;
2527 }
2528 } else {
2529 if (!is_indirect_opcode(table[idx1])) {
9a64fbe4 2530 printf("*** ERROR: idx %02x already assigned to a direct "
79aceca5
FB		 2531 "opcode\n", idx1);
2532 return -1;
2533 }
2534 }
2535 if (handler != NULL &&
2536 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
9a64fbe4 2537 printf("*** ERROR: opcode %02x already assigned in "
79aceca5
FB		 2538 "opcode table %02x\n", idx2, idx1);
2539 return -1;
2540 }
2541
2542 return 0;
2543}
2544
9a64fbe4
FB		 2545static int register_ind_insn (opc_handler_t **ppc_opcodes,
2546 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2547 opc_handler_t *handler)
2548{
2549 int ret;
2550
2551 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2552
2553 return ret;
2554}
2555
9a64fbe4
FB		 2556static int register_dblind_insn (opc_handler_t **ppc_opcodes,
2557 unsigned char idx1, unsigned char idx2,
79aceca5
FB		 2558 unsigned char idx3, opc_handler_t *handler)
2559{
2560 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
9a64fbe4 2561 printf("*** ERROR: unable to join indirect table idx "
79aceca5
FB		 2562 "[%02x-%02x]\n", idx1, idx2);
2563 return -1;
2564 }
2565 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2566 handler) < 0) {
9a64fbe4 2567 printf("*** ERROR: unable to insert opcode "
79aceca5
FB		 2568 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2569 return -1;
2570 }
2571
2572 return 0;
2573}
2574
9a64fbe4 2575static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
79aceca5
FB		 2576{
2577 if (insn->opc2 != 0xFF) {
2578 if (insn->opc3 != 0xFF) {
9a64fbe4
FB		 2579 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2580 insn->opc3, &insn->handler) < 0)
79aceca5
FB		 2581 return -1;
2582 } else {
9a64fbe4
FB		 2583 if (register_ind_insn(ppc_opcodes, insn->opc1,
2584 insn->opc2, &insn->handler) < 0)
79aceca5
FB		 2585 return -1;
2586 }
2587 } else {
9a64fbe4 2588 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
79aceca5
FB		 2589 return -1;
2590 }
2591
2592 return 0;
2593}
2594
2595static int test_opcode_table (opc_handler_t **table, int len)
2596{
2597 int i, count, tmp;
2598
2599 for (i = 0, count = 0; i < len; i++) {
2600 /* Consistency fixup */
2601 if (table[i] == NULL)
2602 table[i] = &invalid_handler;
2603 if (table[i] != &invalid_handler) {
2604 if (is_indirect_opcode(table[i])) {
2605 tmp = test_opcode_table(ind_table(table[i]), 0x20);
2606 if (tmp == 0) {
2607 free(table[i]);
2608 table[i] = &invalid_handler;
2609 } else {
2610 count++;
2611 }
2612 } else {
2613 count++;
2614 }
2615 }
2616 }
2617
2618 return count;
2619}
2620
9a64fbe4 2621static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
79aceca5
FB		 2622{
2623 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
9a64fbe4 2624 printf("*** WARNING: no opcode defined !\n");
79aceca5
FB		 2625}
2626
9a64fbe4 2627#define SPR_RIGHTS(rw, priv) (1 << ((2 * (priv)) + (rw)))
79aceca5
FB		 2628#define SPR_UR SPR_RIGHTS(0, 0)
2629#define SPR_UW SPR_RIGHTS(1, 0)
2630#define SPR_SR SPR_RIGHTS(0, 1)
2631#define SPR_SW SPR_RIGHTS(1, 1)
2632
2633#define spr_set_rights(spr, rights) \
2634do { \
2635 spr_access[(spr) >> 1] |= ((rights) << (4 * ((spr) & 1))); \
2636} while (0)
2637
9a64fbe4 2638static void init_spr_rights (uint32_t pvr)
79aceca5
FB		 2639{
2640 /* XER (SPR 1) */
9a64fbe4 2641 spr_set_rights(XER, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2642 /* LR (SPR 8) */
9a64fbe4 2643 spr_set_rights(LR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2644 /* CTR (SPR 9) */
9a64fbe4 2645 spr_set_rights(CTR, SPR_UR | SPR_UW | SPR_SR | SPR_SW);
79aceca5 2646 /* TBL (SPR 268) */
9a64fbe4 2647 spr_set_rights(V_TBL, SPR_UR | SPR_SR);
79aceca5 2648 /* TBU (SPR 269) */
9a64fbe4 2649 spr_set_rights(V_TBU, SPR_UR | SPR_SR);
79aceca5 2650 /* DSISR (SPR 18) */
9a64fbe4 2651 spr_set_rights(DSISR, SPR_SR | SPR_SW);
79aceca5 2652 /* DAR (SPR 19) */
9a64fbe4 2653 spr_set_rights(DAR, SPR_SR | SPR_SW);
79aceca5 2654 /* DEC (SPR 22) */
9a64fbe4 2655 spr_set_rights(DECR, SPR_SR | SPR_SW);
79aceca5 2656 /* SDR1 (SPR 25) */
9a64fbe4
FB		 2657 spr_set_rights(SDR1, SPR_SR | SPR_SW);
2658 /* SRR0 (SPR 26) */
2659 spr_set_rights(SRR0, SPR_SR | SPR_SW);
2660 /* SRR1 (SPR 27) */
2661 spr_set_rights(SRR1, SPR_SR | SPR_SW);
79aceca5 2662 /* SPRG0 (SPR 272) */
9a64fbe4 2663 spr_set_rights(SPRG0, SPR_SR | SPR_SW);
79aceca5 2664 /* SPRG1 (SPR 273) */
9a64fbe4 2665 spr_set_rights(SPRG1, SPR_SR | SPR_SW);
79aceca5 2666 /* SPRG2 (SPR 274) */
9a64fbe4 2667 spr_set_rights(SPRG2, SPR_SR | SPR_SW);
79aceca5 2668 /* SPRG3 (SPR 275) */
9a64fbe4 2669 spr_set_rights(SPRG3, SPR_SR | SPR_SW);
79aceca5 2670 /* ASR (SPR 280) */
9a64fbe4 2671 spr_set_rights(ASR, SPR_SR | SPR_SW);
79aceca5 2672 /* EAR (SPR 282) */
9a64fbe4
FB		 2673 spr_set_rights(EAR, SPR_SR | SPR_SW);
2674 /* TBL (SPR 284) */
2675 spr_set_rights(O_TBL, SPR_SW);
2676 /* TBU (SPR 285) */
2677 spr_set_rights(O_TBU, SPR_SW);
2678 /* PVR (SPR 287) */
2679 spr_set_rights(PVR, SPR_SR);
79aceca5 2680 /* IBAT0U (SPR 528) */
9a64fbe4 2681 spr_set_rights(IBAT0U, SPR_SR | SPR_SW);
79aceca5 2682 /* IBAT0L (SPR 529) */
9a64fbe4 2683 spr_set_rights(IBAT0L, SPR_SR | SPR_SW);
79aceca5 2684 /* IBAT1U (SPR 530) */
9a64fbe4 2685 spr_set_rights(IBAT1U, SPR_SR | SPR_SW);
79aceca5 2686 /* IBAT1L (SPR 531) */
9a64fbe4 2687 spr_set_rights(IBAT1L, SPR_SR | SPR_SW);
79aceca5 2688 /* IBAT2U (SPR 532) */
9a64fbe4 2689 spr_set_rights(IBAT2U, SPR_SR | SPR_SW);
79aceca5 2690 /* IBAT2L (SPR 533) */
9a64fbe4 2691 spr_set_rights(IBAT2L, SPR_SR | SPR_SW);
79aceca5 2692 /* IBAT3U (SPR 534) */
9a64fbe4 2693 spr_set_rights(IBAT3U, SPR_SR | SPR_SW);
79aceca5 2694 /* IBAT3L (SPR 535) */
9a64fbe4 2695 spr_set_rights(IBAT3L, SPR_SR | SPR_SW);
79aceca5 2696 /* DBAT0U (SPR 536) */
9a64fbe4 2697 spr_set_rights(DBAT0U, SPR_SR | SPR_SW);
79aceca5 2698 /* DBAT0L (SPR 537) */
9a64fbe4 2699 spr_set_rights(DBAT0L, SPR_SR | SPR_SW);
79aceca5 2700 /* DBAT1U (SPR 538) */
9a64fbe4 2701 spr_set_rights(DBAT1U, SPR_SR | SPR_SW);
79aceca5 2702 /* DBAT1L (SPR 539) */
9a64fbe4 2703 spr_set_rights(DBAT1L, SPR_SR | SPR_SW);
79aceca5 2704 /* DBAT2U (SPR 540) */
9a64fbe4 2705 spr_set_rights(DBAT2U, SPR_SR | SPR_SW);
79aceca5 2706 /* DBAT2L (SPR 541) */
9a64fbe4 2707 spr_set_rights(DBAT2L, SPR_SR | SPR_SW);
79aceca5 2708 /* DBAT3U (SPR 542) */
9a64fbe4 2709 spr_set_rights(DBAT3U, SPR_SR | SPR_SW);
79aceca5 2710 /* DBAT3L (SPR 543) */
9a64fbe4 2711 spr_set_rights(DBAT3L, SPR_SR | SPR_SW);
79aceca5 2712 /* FPECR (SPR 1022) */
9a64fbe4 2713 spr_set_rights(FPECR, SPR_SR | SPR_SW);
4b3686fa
FB		 2714 /* Special registers for PPC 604 */
2715 if ((pvr & 0xFFFF0000) == 0x00040000) {
2716 /* IABR */
2717 spr_set_rights(IABR , SPR_SR | SPR_SW);
2718 /* DABR (SPR 1013) */
2719 spr_set_rights(DABR, SPR_SR | SPR_SW);
2720 /* HID0 */
2721 spr_set_rights(HID0, SPR_SR | SPR_SW);
2722 /* PIR */
9a64fbe4 2723 spr_set_rights(PIR, SPR_SR | SPR_SW);
4b3686fa
FB		 2724 /* PMC1 */
2725 spr_set_rights(PMC1, SPR_SR | SPR_SW);
2726 /* PMC2 */
2727 spr_set_rights(PMC2, SPR_SR | SPR_SW);
2728 /* MMCR0 */
2729 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
2730 /* SIA */
2731 spr_set_rights(SIA, SPR_SR | SPR_SW);
2732 /* SDA */
2733 spr_set_rights(SDA, SPR_SR | SPR_SW);
2734 }
9a64fbe4
FB		 2735 /* Special registers for MPC740/745/750/755 (aka G3) & IBM 750 */
2736 if ((pvr & 0xFFFF0000) == 0x00080000 ||
2737 (pvr & 0xFFFF0000) == 0x70000000) {
2738 /* HID0 */
4b3686fa 2739 spr_set_rights(HID0, SPR_SR | SPR_SW);
9a64fbe4 2740 /* HID1 */
4b3686fa 2741 spr_set_rights(HID1, SPR_SR | SPR_SW);
9a64fbe4 2742 /* IABR */
4b3686fa 2743 spr_set_rights(IABR, SPR_SR | SPR_SW);
9a64fbe4 2744 /* ICTC */
4b3686fa 2745 spr_set_rights(ICTC, SPR_SR | SPR_SW);
9a64fbe4 2746 /* L2CR */
4b3686fa 2747 spr_set_rights(L2CR, SPR_SR | SPR_SW);
9a64fbe4 2748 /* MMCR0 */
4b3686fa 2749 spr_set_rights(MMCR0, SPR_SR | SPR_SW);
9a64fbe4 2750 /* MMCR1 */
4b3686fa 2751 spr_set_rights(MMCR1, SPR_SR | SPR_SW);
9a64fbe4 2752 /* PMC1 */
4b3686fa 2753 spr_set_rights(PMC1, SPR_SR | SPR_SW);
9a64fbe4 2754 /* PMC2 */
4b3686fa 2755 spr_set_rights(PMC2, SPR_SR | SPR_SW);
9a64fbe4 2756 /* PMC3 */
4b3686fa 2757 spr_set_rights(PMC3, SPR_SR | SPR_SW);
9a64fbe4 2758 /* PMC4 */
4b3686fa 2759 spr_set_rights(PMC4, SPR_SR | SPR_SW);
9a64fbe4 2760 /* SIA */
4b3686fa
FB		 2761 spr_set_rights(SIA, SPR_SR | SPR_SW);
2762 /* SDA */
2763 spr_set_rights(SDA, SPR_SR | SPR_SW);
9a64fbe4 2764 /* THRM1 */
4b3686fa 2765 spr_set_rights(THRM1, SPR_SR | SPR_SW);
9a64fbe4 2766 /* THRM2 */
4b3686fa 2767 spr_set_rights(THRM2, SPR_SR | SPR_SW);
9a64fbe4 2768 /* THRM3 */
4b3686fa 2769 spr_set_rights(THRM3, SPR_SR | SPR_SW);
9a64fbe4 2770 /* UMMCR0 */
4b3686fa 2771 spr_set_rights(UMMCR0, SPR_UR | SPR_UW);
9a64fbe4 2772 /* UMMCR1 */
4b3686fa 2773 spr_set_rights(UMMCR1, SPR_UR | SPR_UW);
9a64fbe4 2774 /* UPMC1 */
4b3686fa 2775 spr_set_rights(UPMC1, SPR_UR | SPR_UW);
9a64fbe4 2776 /* UPMC2 */
4b3686fa 2777 spr_set_rights(UPMC2, SPR_UR | SPR_UW);
9a64fbe4 2778 /* UPMC3 */
4b3686fa 2779 spr_set_rights(UPMC3, SPR_UR | SPR_UW);
9a64fbe4 2780 /* UPMC4 */
4b3686fa 2781 spr_set_rights(UPMC4, SPR_UR | SPR_UW);
9a64fbe4 2782 /* USIA */
4b3686fa 2783 spr_set_rights(USIA, SPR_UR | SPR_UW);
9a64fbe4
FB		 2784 }
2785 /* MPC755 has special registers */
2786 if (pvr == 0x00083100) {
2787 /* SPRG4 */
2788 spr_set_rights(SPRG4, SPR_SR | SPR_SW);
2789 /* SPRG5 */
2790 spr_set_rights(SPRG5, SPR_SR | SPR_SW);
2791 /* SPRG6 */
2792 spr_set_rights(SPRG6, SPR_SR | SPR_SW);
2793 /* SPRG7 */
2794 spr_set_rights(SPRG7, SPR_SR | SPR_SW);
2795 /* IBAT4U */
2796 spr_set_rights(IBAT4U, SPR_SR | SPR_SW);
2797 /* IBAT4L */
2798 spr_set_rights(IBAT4L, SPR_SR | SPR_SW);
2799 /* IBAT5U */
2800 spr_set_rights(IBAT5U, SPR_SR | SPR_SW);
2801 /* IBAT5L */
2802 spr_set_rights(IBAT5L, SPR_SR | SPR_SW);
2803 /* IBAT6U */
2804 spr_set_rights(IBAT6U, SPR_SR | SPR_SW);
2805 /* IBAT6L */
2806 spr_set_rights(IBAT6L, SPR_SR | SPR_SW);
2807 /* IBAT7U */
2808 spr_set_rights(IBAT7U, SPR_SR | SPR_SW);
2809 /* IBAT7L */
2810 spr_set_rights(IBAT7L, SPR_SR | SPR_SW);
2811 /* DBAT4U */
2812 spr_set_rights(DBAT4U, SPR_SR | SPR_SW);
2813 /* DBAT4L */
2814 spr_set_rights(DBAT4L, SPR_SR | SPR_SW);
2815 /* DBAT5U */
2816 spr_set_rights(DBAT5U, SPR_SR | SPR_SW);
2817 /* DBAT5L */
2818 spr_set_rights(DBAT5L, SPR_SR | SPR_SW);
2819 /* DBAT6U */
2820 spr_set_rights(DBAT6U, SPR_SR | SPR_SW);
2821 /* DBAT6L */
2822 spr_set_rights(DBAT6L, SPR_SR | SPR_SW);
2823 /* DBAT7U */
2824 spr_set_rights(DBAT7U, SPR_SR | SPR_SW);
2825 /* DBAT7L */
2826 spr_set_rights(DBAT7L, SPR_SR | SPR_SW);
2827 /* DMISS */
4b3686fa 2828 spr_set_rights(DMISS, SPR_SR | SPR_SW);
9a64fbe4 2829 /* DCMP */
4b3686fa 2830 spr_set_rights(DCMP, SPR_SR | SPR_SW);
9a64fbe4 2831 /* DHASH1 */
4b3686fa 2832 spr_set_rights(DHASH1, SPR_SR | SPR_SW);
9a64fbe4 2833 /* DHASH2 */
4b3686fa 2834 spr_set_rights(DHASH2, SPR_SR | SPR_SW);
9a64fbe4 2835 /* IMISS */
4b3686fa 2836 spr_set_rights(IMISS, SPR_SR | SPR_SW);
9a64fbe4 2837 /* ICMP */
4b3686fa 2838 spr_set_rights(ICMP, SPR_SR | SPR_SW);
9a64fbe4 2839 /* RPA */
4b3686fa 2840 spr_set_rights(RPA, SPR_SR | SPR_SW);
9a64fbe4 2841 /* HID2 */
4b3686fa 2842 spr_set_rights(HID2, SPR_SR | SPR_SW);
9a64fbe4 2843 /* L2PM */
4b3686fa 2844 spr_set_rights(L2PM, SPR_SR | SPR_SW);
9a64fbe4 2845 }
79aceca5
FB		 2846}
2847
9a64fbe4
FB		 2848/*****************************************************************************/
2849/* PPC "main stream" common instructions (no optional ones) */
79aceca5
FB		 2850
2851typedef struct ppc_proc_t {
2852 int flags;
2853 void *specific;
2854} ppc_proc_t;
2855
2856typedef struct ppc_def_t {
2857 unsigned long pvr;
2858 unsigned long pvr_mask;
2859 ppc_proc_t *proc;
2860} ppc_def_t;
2861
2862static ppc_proc_t ppc_proc_common = {
2863 .flags = PPC_COMMON,
2864 .specific = NULL,
2865};
2866
9a64fbe4
FB		 2867static ppc_proc_t ppc_proc_G3 = {
2868 .flags = PPC_750,
2869 .specific = NULL,
2870};
2871
79aceca5
FB		 2872static ppc_def_t ppc_defs[] =
2873{
9a64fbe4
FB		 2874 /* MPC740/745/750/755 (G3) */
2875 {
2876 .pvr = 0x00080000,
2877 .pvr_mask = 0xFFFF0000,
2878 .proc = &ppc_proc_G3,
2879 },
2880 /* IBM 750FX (G3 embedded) */
2881 {
2882 .pvr = 0x70000000,
2883 .pvr_mask = 0xFFFF0000,
2884 .proc = &ppc_proc_G3,
2885 },
2886 /* Fallback (generic PPC) */
79aceca5
FB		 2887 {
2888 .pvr = 0x00000000,
2889 .pvr_mask = 0x00000000,
2890 .proc = &ppc_proc_common,
2891 },
2892};
2893
9a64fbe4 2894static int create_ppc_proc (opc_handler_t **ppc_opcodes, unsigned long pvr)
79aceca5
FB		 2895{
2896 opcode_t *opc;
2897 int i, flags;
2898
2899 fill_new_table(ppc_opcodes, 0x40);
2900 for (i = 0; ; i++) {
2901 if ((ppc_defs[i].pvr & ppc_defs[i].pvr_mask) ==
2902 (pvr & ppc_defs[i].pvr_mask)) {
2903 flags = ppc_defs[i].proc->flags;
2904 break;
2905 }
2906 }
2907
2908 for (opc = &opc_start + 1; opc != &opc_end; opc++) {
9a64fbe4
FB		 2909 if ((opc->handler.type & flags) != 0)
2910 if (register_insn(ppc_opcodes, opc) < 0) {
2911 printf("*** ERROR initializing PPC instruction "
79aceca5
FB		 2912 "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2913 opc->opc3);
2914 return -1;
2915 }
2916 }
9a64fbe4 2917 fix_opcode_tables(ppc_opcodes);
79aceca5
FB		 2918
2919 return 0;
2920}
2921
9a64fbe4 2922
79aceca5 2923/*****************************************************************************/
9a64fbe4 2924/* Misc PPC helpers */
79aceca5
FB		 2925
2926void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags)
2927{
2928 int i;
2929
9a64fbe4
FB		 2930 fprintf(f, "nip=0x%08x LR=0x%08x CTR=0x%08x XER=0x%08x "
2931 "MSR=0x%08x\n", env->nip, env->lr, env->ctr,
a541f297 2932 _load_xer(env), _load_msr(env));
79aceca5
FB		 2933 for (i = 0; i < 32; i++) {
2934 if ((i & 7) == 0)
9a64fbe4
FB		 2935 fprintf(f, "GPR%02d:", i);
2936 fprintf(f, " %08x", env->gpr[i]);
79aceca5 2937 if ((i & 7) == 7)
9a64fbe4 2938 fprintf(f, "\n");
79aceca5 2939 }
9a64fbe4 2940 fprintf(f, "CR: 0x");
79aceca5 2941 for (i = 0; i < 8; i++)
9a64fbe4
FB		 2942 fprintf(f, "%01x", env->crf[i]);
2943 fprintf(f, " [");
79aceca5
FB		 2944 for (i = 0; i < 8; i++) {
2945 char a = '-';
79aceca5
FB		 2946 if (env->crf[i] & 0x08)
2947 a = 'L';
2948 else if (env->crf[i] & 0x04)
2949 a = 'G';
2950 else if (env->crf[i] & 0x02)
2951 a = 'E';
9a64fbe4 2952 fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
79aceca5 2953 }
9a64fbe4 2954 fprintf(f, " ] ");
9fddaa0c
FB		 2955 fprintf(f, "TB: 0x%08x %08x\n", cpu_ppc_load_tbu(env),
2956 cpu_ppc_load_tbl(env));
79aceca5
FB		 2957 for (i = 0; i < 16; i++) {
2958 if ((i & 3) == 0)
9a64fbe4
FB		 2959 fprintf(f, "FPR%02d:", i);
2960 fprintf(f, " %016llx", *((uint64_t *)&env->fpr[i]));
79aceca5 2961 if ((i & 3) == 3)
9a64fbe4 2962 fprintf(f, "\n");
79aceca5 2963 }
9fddaa0c
FB		 2964 fprintf(f, "SRR0 0x%08x SRR1 0x%08x DECR=0x%08x\n",
2965 env->spr[SRR0], env->spr[SRR1], cpu_ppc_load_decr(env));
9a64fbe4
FB		 2966 fprintf(f, "reservation 0x%08x\n", env->reserve);
2967 fflush(f);
79aceca5
FB		 2968}
2969
9a64fbe4
FB		 2970#if !defined(CONFIG_USER_ONLY) && defined (USE_OPENFIRMWARE)
2971int setup_machine (CPUPPCState *env, uint32_t mid);
2972#endif
2973
79aceca5
FB		 2974CPUPPCState *cpu_ppc_init(void)
2975{
2976 CPUPPCState *env;
2977
2978 cpu_exec_init();
2979
4b3686fa 2980 env = qemu_mallocz(sizeof(CPUPPCState));
79aceca5
FB		 2981 if (!env)
2982 return NULL;
9a64fbe4
FB		 2983#if !defined(CONFIG_USER_ONLY) && defined (USE_OPEN_FIRMWARE)
2984 setup_machine(env, 0);
2985#else
2986// env->spr[PVR] = 0; /* Basic PPC */
2987 env->spr[PVR] = 0x00080100; /* G3 CPU */
2988// env->spr[PVR] = 0x00083100; /* MPC755 (G3 embedded) */
2989// env->spr[PVR] = 0x00070100; /* IBM 750FX */
2990#endif
ad081323 2991 tlb_flush(env, 1);
9a64fbe4
FB		 2992#if defined (DO_SINGLE_STEP)
2993 /* Single step trace mode */
2994 msr_se = 1;
2995#endif
4b3686fa
FB		 2996 msr_fp = 1; /* Allow floating point exceptions */
2997 msr_me = 1; /* Allow machine check exceptions */
9a64fbe4
FB		 2998#if defined(CONFIG_USER_ONLY)
2999 msr_pr = 1;
4b3686fa
FB		 3000 cpu_ppc_register(env, 0x00080000);
3001#else
3002 env->nip = 0xFFFFFFFC;
9a64fbe4 3003#endif
a541f297 3004 env->access_type = ACCESS_INT;
7496f526 3005 cpu_single_env = env;
79aceca5
FB		 3006 return env;
3007}
3008
4b3686fa
FB		 3009int cpu_ppc_register (CPUPPCState *env, uint32_t pvr)
3010{
3011 env->spr[PVR] = pvr;
3012 if (create_ppc_proc(ppc_opcodes, env->spr[PVR]) < 0)
3013 return -1;
3014 init_spr_rights(env->spr[PVR]);
3015
3016 return 0;
3017}
3018
79aceca5
FB		 3019void cpu_ppc_close(CPUPPCState *env)
3020{
3021 /* Should also remove all opcode tables... */
3022 free(env);
3023}
3024
9a64fbe4 3025/*****************************************************************************/
9a64fbe4
FB		 3026int print_insn_powerpc (FILE *out, unsigned long insn, unsigned memaddr,
3027 int dialect);
3028
79aceca5
FB		 3029int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
3030 int search_pc)
3031{
9fddaa0c 3032 DisasContext ctx, *ctxp = &ctx;
79aceca5
FB		 3033 opc_handler_t **table, *handler;
3034 uint32_t pc_start;
3035 uint16_t *gen_opc_end;
3036 int j, lj = -1;
79aceca5
FB		 3037
3038 pc_start = tb->pc;
3039 gen_opc_ptr = gen_opc_buf;
3040 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3041 gen_opparam_ptr = gen_opparam_buf;
046d6672 3042 ctx.nip = pc_start;
79aceca5 3043 ctx.tb = tb;
9a64fbe4
FB		 3044 ctx.exception = EXCP_NONE;
3045#if defined(CONFIG_USER_ONLY)
3046 ctx.mem_idx = 0;
3047#else
3048 ctx.supervisor = 1 - msr_pr;
3049 ctx.mem_idx = (1 - msr_pr);
3050#endif
3051#if defined (DO_SINGLE_STEP)
3052 /* Single step trace mode */
3053 msr_se = 1;
3054#endif
a541f297 3055 env->access_type = ACCESS_CODE;
9a64fbe4
FB		 3056 /* Set env in case of segfault during code fetch */
3057 while (ctx.exception == EXCP_NONE && gen_opc_ptr < gen_opc_end) {
79aceca5
FB		 3058 if (search_pc) {
3059 if (loglevel > 0)
3060 fprintf(logfile, "Search PC...\n");
3061 j = gen_opc_ptr - gen_opc_buf;
3062 if (lj < j) {
3063 lj++;
3064 while (lj < j)
3065 gen_opc_instr_start[lj++] = 0;
046d6672 3066 gen_opc_pc[lj] = ctx.nip;
79aceca5
FB		 3067 gen_opc_instr_start[lj] = 1;
3068 }
3069 }
9fddaa0c
FB		 3070#if defined PPC_DEBUG_DISAS
3071 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 3072 fprintf(logfile, "----------------\n");
046d6672 3073 fprintf(logfile, "nip=%08x super=%d ir=%d\n",
9a64fbe4
FB		 3074 ctx.nip, 1 - msr_pr, msr_ir);
3075 }
3076#endif
046d6672 3077 ctx.opcode = ldl_code((void *)ctx.nip);
9fddaa0c
FB		 3078#if defined PPC_DEBUG_DISAS
3079 if (loglevel & CPU_LOG_TB_IN_ASM) {
9a64fbe4
FB		 3080 fprintf(logfile, "translate opcode %08x (%02x %02x %02x)\n",
3081 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
3082 opc3(ctx.opcode));
79aceca5
FB		 3083 }
3084#endif
046d6672 3085 ctx.nip += 4;
79aceca5
FB		 3086 table = ppc_opcodes;
3087 handler = table[opc1(ctx.opcode)];
3088 if (is_indirect_opcode(handler)) {
3089 table = ind_table(handler);
3090 handler = table[opc2(ctx.opcode)];
3091 if (is_indirect_opcode(handler)) {
3092 table = ind_table(handler);
3093 handler = table[opc3(ctx.opcode)];
3094 }
3095 }
3096 /* Is opcode *REALLY* valid ? */
79aceca5 3097 if (handler->handler == &gen_invalid) {
4b3686fa 3098 if (loglevel > 0) {
79aceca5 3099 fprintf(logfile, "invalid/unsupported opcode: "
4b3686fa 3100 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
9a64fbe4 3101 opc1(ctx.opcode), opc2(ctx.opcode),
4b3686fa
FB		 3102 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3103 } else {
3104 printf("invalid/unsupported opcode: "
3105 "%02x - %02x - %02x (%08x) 0x%08x %d\n",
3106 opc1(ctx.opcode), opc2(ctx.opcode),
3107 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, msr_ir);
3108 }
79aceca5 3109 } else {
4b3686fa
FB		 3110 if ((ctx.opcode & handler->inval) != 0) {
3111 if (loglevel > 0) {
79aceca5 3112 fprintf(logfile, "invalid bits: %08x for opcode: "
046d6672 3113 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
79aceca5
FB		 3114 ctx.opcode & handler->inval, opc1(ctx.opcode),
3115 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 3116 ctx.opcode, ctx.nip - 4);
9a64fbe4
FB		 3117 } else {
3118 printf("invalid bits: %08x for opcode: "
046d6672 3119 "%02x -%02x - %02x (0x%08x) (0x%08x)\n",
9a64fbe4
FB		 3120 ctx.opcode & handler->inval, opc1(ctx.opcode),
3121 opc2(ctx.opcode), opc3(ctx.opcode),
046d6672 3122 ctx.opcode, ctx.nip - 4);
9a64fbe4 3123 }
4b3686fa
FB		 3124 RET_INVAL(ctxp);
3125 break;
79aceca5 3126 }
79aceca5 3127 }
4b3686fa 3128 (*(handler->handler))(&ctx);
9a64fbe4
FB		 3129 /* Check trace mode exceptions */
3130 if ((msr_be && ctx.exception == EXCP_BRANCH) ||
3131 /* Check in single step trace mode
3132 * we need to stop except if:
3133 * - rfi, trap or syscall
3134 * - first instruction of an exception handler
3135 */
046d6672
FB		 3136 (msr_se && (ctx.nip < 0x100 ||
3137 ctx.nip > 0xF00 ||
3138 (ctx.nip & 0xFC) != 0x04) &&
9a64fbe4
FB		 3139 ctx.exception != EXCP_SYSCALL && ctx.exception != EXCP_RFI &&
3140 ctx.exception != EXCP_TRAP)) {
9fddaa0c 3141 RET_EXCP(ctxp, EXCP_TRACE, 0);
9a64fbe4 3142 }
a541f297 3143 /* if we reach a page boundary, stop generation */
046d6672 3144 if ((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) {
9fddaa0c 3145 RET_EXCP(ctxp, EXCP_BRANCH, 0);
79aceca5 3146 }
9a64fbe4 3147 }
9fddaa0c
FB		 3148 if (ctx.exception == EXCP_NONE) {
3149 gen_op_b((unsigned long)ctx.tb, ctx.nip);
3150 } else if (ctx.exception != EXCP_BRANCH) {
3151 gen_op_set_T0(0);
9a64fbe4
FB		 3152 }
3153#if 1
79aceca5
FB		 3154 /* TO BE FIXED: T0 hasn't got a proper value, which makes tb_add_jump
3155 * do bad business and then qemu crashes !
3156 */
3157 gen_op_set_T0(0);
9a64fbe4 3158#endif
79aceca5
FB		 3159 /* Generate the return instruction */
3160 gen_op_exit_tb();
3161 *gen_opc_ptr = INDEX_op_end;
9a64fbe4
FB		 3162 if (search_pc) {
3163 j = gen_opc_ptr - gen_opc_buf;
3164 lj++;
3165 while (lj <= j)
3166 gen_opc_instr_start[lj++] = 0;
79aceca5 3167 tb->size = 0;
985a19d6 3168#if 0
9a64fbe4
FB		 3169 if (loglevel > 0) {
3170 page_dump(logfile);
3171 }
985a19d6 3172#endif
9a64fbe4 3173 } else {
046d6672 3174 tb->size = ctx.nip - pc_start;
9a64fbe4 3175 }
79aceca5 3176#ifdef DEBUG_DISAS
9fddaa0c 3177 if (loglevel & CPU_LOG_TB_CPU) {
9a64fbe4
FB		 3178 fprintf(logfile, "---------------- excp: %04x\n", ctx.exception);
3179 cpu_ppc_dump_state(env, logfile, 0);
9fddaa0c
FB		 3180 }
3181 if (loglevel & CPU_LOG_TB_IN_ASM) {
79aceca5 3182 fprintf(logfile, "IN: %s\n", lookup_symbol((void *)pc_start));
046d6672 3183 disas(logfile, (void *)pc_start, ctx.nip - pc_start, 0, 0);
79aceca5 3184 fprintf(logfile, "\n");
9fddaa0c
FB		 3185 }
3186 if (loglevel & CPU_LOG_TB_OP) {
79aceca5
FB		 3187 fprintf(logfile, "OP:\n");
3188 dump_ops(gen_opc_buf, gen_opparam_buf);
3189 fprintf(logfile, "\n");
3190 }
3191#endif
4b3686fa 3192 env->access_type = ACCESS_INT;
79aceca5
FB		 3193
3194 return 0;
3195}
3196
9a64fbe4 3197int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3198{
3199 return gen_intermediate_code_internal(env, tb, 0);
3200}
3201
9a64fbe4 3202int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
79aceca5
FB		 3203{
3204 return gen_intermediate_code_internal(env, tb, 1);
3205}
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