[qemu.git] / hw / pxa.h

/*
 * Intel XScale PXA255/270 processor support.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <[email protected]>
 *
 * This code is licenced under the GNU GPL v2.
 */
#ifndef PXA_H
# define PXA_H			"pxa.h"

/* Interrupt numbers */
# define PXA2XX_PIC_SSP3	0
# define PXA2XX_PIC_USBH2	2
# define PXA2XX_PIC_USBH1	3
# define PXA2XX_PIC_KEYPAD	4
# define PXA2XX_PIC_PWRI2C	6
# define PXA25X_PIC_HWUART	7
# define PXA27X_PIC_OST_4_11	7
# define PXA2XX_PIC_GPIO_0	8
# define PXA2XX_PIC_GPIO_1	9
# define PXA2XX_PIC_GPIO_X	10
# define PXA2XX_PIC_I2S 	13
# define PXA26X_PIC_ASSP	15
# define PXA25X_PIC_NSSP	16
# define PXA27X_PIC_SSP2	16
# define PXA2XX_PIC_LCD		17
# define PXA2XX_PIC_I2C		18
# define PXA2XX_PIC_ICP		19
# define PXA2XX_PIC_STUART	20
# define PXA2XX_PIC_BTUART	21
# define PXA2XX_PIC_FFUART	22
# define PXA2XX_PIC_MMC		23
# define PXA2XX_PIC_SSP		24
# define PXA2XX_PIC_DMA		25
# define PXA2XX_PIC_OST_0	26
# define PXA2XX_PIC_RTC1HZ	30
# define PXA2XX_PIC_RTCALARM	31

/* DMA requests */
# define PXA2XX_RX_RQ_I2S	2
# define PXA2XX_TX_RQ_I2S	3
# define PXA2XX_RX_RQ_BTUART	4
# define PXA2XX_TX_RQ_BTUART	5
# define PXA2XX_RX_RQ_FFUART	6
# define PXA2XX_TX_RQ_FFUART	7
# define PXA2XX_RX_RQ_SSP1	13
# define PXA2XX_TX_RQ_SSP1	14
# define PXA2XX_RX_RQ_SSP2	15
# define PXA2XX_TX_RQ_SSP2	16
# define PXA2XX_RX_RQ_ICP	17
# define PXA2XX_TX_RQ_ICP	18
# define PXA2XX_RX_RQ_STUART	19
# define PXA2XX_TX_RQ_STUART	20
# define PXA2XX_RX_RQ_MMCI	21
# define PXA2XX_TX_RQ_MMCI	22
# define PXA2XX_USB_RQ(x)	((x) + 24)
# define PXA2XX_RX_RQ_SSP3	66
# define PXA2XX_TX_RQ_SSP3	67

# define PXA2XX_SDRAM_BASE	0xa0000000
# define PXA2XX_INTERNAL_BASE	0x5c000000
# define PXA2XX_INTERNAL_SIZE	0x40000

/* pxa2xx_pic.c */
qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);

/* pxa2xx_timer.c */
void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);

/* pxa2xx_gpio.c */
struct pxa2xx_gpio_info_s;
struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
                CPUState *env, qemu_irq *pic, int lines);
qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s);
void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
                int line, qemu_irq handler);
void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler);

/* pxa2xx_dma.c */
struct pxa2xx_dma_state_s;
struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
                qemu_irq irq);
struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
                qemu_irq irq);
void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);

/* pxa2xx_lcd.c */
struct pxa2xx_lcdc_s;
struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
                qemu_irq irq, DisplayState *ds);
void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);

/* pxa2xx_mmci.c */
struct pxa2xx_mmci_s;
struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
                BlockDriverState *bd, qemu_irq irq, void *dma);
void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly,
                qemu_irq coverswitch);

/* pxa2xx_pcmcia.c */
struct pxa2xx_pcmcia_s;
struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
int pxa2xx_pcmcia_attach(void *opaque, struct pcmcia_card_s *card);
int pxa2xx_pcmcia_dettach(void *opaque);
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);

/* pxa2xx_keypad.c */
struct  keymap {
    int column;
    int row;
};
struct pxa2xx_keypad_s;
struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base,
                qemu_irq irq);
void pxa27x_register_keypad(struct pxa2xx_keypad_s *kp, struct keymap *map,
                int size);

/* pxa2xx.c */
struct pxa2xx_ssp_s;
void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
                uint32_t (*readfn)(void *opaque),
                void (*writefn)(void *opaque, uint32_t value), void *opaque);

struct pxa2xx_i2c_s;
struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
                qemu_irq irq, uint32_t page_size);
i2c_bus *pxa2xx_i2c_bus(struct pxa2xx_i2c_s *s);

struct pxa2xx_i2s_s;
struct pxa2xx_fir_s;

struct pxa2xx_state_s {
    CPUState *env;
    qemu_irq *pic;
    qemu_irq reset;
    struct pxa2xx_dma_state_s *dma;
    struct pxa2xx_gpio_info_s *gpio;
    struct pxa2xx_lcdc_s *lcd;
    struct pxa2xx_ssp_s **ssp;
    struct pxa2xx_i2c_s *i2c[2];
    struct pxa2xx_mmci_s *mmc;
    struct pxa2xx_pcmcia_s *pcmcia[2];
    struct pxa2xx_i2s_s *i2s;
    struct pxa2xx_fir_s *fir;
    struct pxa2xx_keypad_s *kp;

    /* Power management */
    target_phys_addr_t pm_base;
    uint32_t pm_regs[0x40];

    /* Clock management */
    target_phys_addr_t cm_base;
    uint32_t cm_regs[4];
    uint32_t clkcfg;

    /* Memory management */
    target_phys_addr_t mm_base;
    uint32_t mm_regs[0x1a];

    /* Performance monitoring */
    uint32_t pmnc;

    /* Real-Time clock */
    target_phys_addr_t rtc_base;
    uint32_t rttr;
    uint32_t rtsr;
    uint32_t rtar;
    uint32_t rdar1;
    uint32_t rdar2;
    uint32_t ryar1;
    uint32_t ryar2;
    uint32_t swar1;
    uint32_t swar2;
    uint32_t piar;
    uint32_t last_rcnr;
    uint32_t last_rdcr;
    uint32_t last_rycr;
    uint32_t last_swcr;
    uint32_t last_rtcpicr;
    int64_t last_hz;
    int64_t last_sw;
    int64_t last_pi;
    QEMUTimer *rtc_hz;
    QEMUTimer *rtc_rdal1;
    QEMUTimer *rtc_rdal2;
    QEMUTimer *rtc_swal1;
    QEMUTimer *rtc_swal2;
    QEMUTimer *rtc_pi;
};

struct pxa2xx_i2s_s {
    target_phys_addr_t base;
    qemu_irq irq;
    struct pxa2xx_dma_state_s *dma;
    void (*data_req)(void *, int, int);

    uint32_t control[2];
    uint32_t status;
    uint32_t mask;
    uint32_t clk;

    int enable;
    int rx_len;
    int tx_len;
    void (*codec_out)(void *, uint32_t);
    uint32_t (*codec_in)(void *);
    void *opaque;

    int fifo_len;
    uint32_t fifo[16];
};

# define PA_FMT			"0x%08lx"
# define REG_FMT		"0x" TARGET_FMT_plx

struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, DisplayState *ds,
                const char *revision);
struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, DisplayState *ds);

/* usb-ohci.c */
void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
                       qemu_irq irq);

#endif	/* PXA_H */
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 processor support.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <[email protected]>
	6	*
3efda49d	7	* This code is licenced under the GNU GPL v2.
c1713132 AZ	8	*/
	9	#ifndef PXA_H
	10	# define PXA_H "pxa.h"
	11
	12	/* Interrupt numbers */
	13	# define PXA2XX_PIC_SSP3 0
	14	# define PXA2XX_PIC_USBH2 2
	15	# define PXA2XX_PIC_USBH1 3
31b87f2e	16	# define PXA2XX_PIC_KEYPAD 4
c1713132 AZ	17	# define PXA2XX_PIC_PWRI2C 6
	18	# define PXA25X_PIC_HWUART 7
	19	# define PXA27X_PIC_OST_4_11 7
	20	# define PXA2XX_PIC_GPIO_0 8
	21	# define PXA2XX_PIC_GPIO_1 9
	22	# define PXA2XX_PIC_GPIO_X 10
	23	# define PXA2XX_PIC_I2S 13
	24	# define PXA26X_PIC_ASSP 15
	25	# define PXA25X_PIC_NSSP 16
	26	# define PXA27X_PIC_SSP2 16
	27	# define PXA2XX_PIC_LCD 17
	28	# define PXA2XX_PIC_I2C 18
	29	# define PXA2XX_PIC_ICP 19
	30	# define PXA2XX_PIC_STUART 20
	31	# define PXA2XX_PIC_BTUART 21
	32	# define PXA2XX_PIC_FFUART 22
	33	# define PXA2XX_PIC_MMC 23
	34	# define PXA2XX_PIC_SSP 24
	35	# define PXA2XX_PIC_DMA 25
	36	# define PXA2XX_PIC_OST_0 26
	37	# define PXA2XX_PIC_RTC1HZ 30
	38	# define PXA2XX_PIC_RTCALARM 31
	39
	40	/* DMA requests */
	41	# define PXA2XX_RX_RQ_I2S 2
	42	# define PXA2XX_TX_RQ_I2S 3
	43	# define PXA2XX_RX_RQ_BTUART 4
	44	# define PXA2XX_TX_RQ_BTUART 5
	45	# define PXA2XX_RX_RQ_FFUART 6
	46	# define PXA2XX_TX_RQ_FFUART 7
	47	# define PXA2XX_RX_RQ_SSP1 13
	48	# define PXA2XX_TX_RQ_SSP1 14
	49	# define PXA2XX_RX_RQ_SSP2 15
	50	# define PXA2XX_TX_RQ_SSP2 16
	51	# define PXA2XX_RX_RQ_ICP 17
	52	# define PXA2XX_TX_RQ_ICP 18
	53	# define PXA2XX_RX_RQ_STUART 19
	54	# define PXA2XX_TX_RQ_STUART 20
	55	# define PXA2XX_RX_RQ_MMCI 21
	56	# define PXA2XX_TX_RQ_MMCI 22
	57	# define PXA2XX_USB_RQ(x) ((x) + 24)
	58	# define PXA2XX_RX_RQ_SSP3 66
	59	# define PXA2XX_TX_RQ_SSP3 67
	60
d95b2f8d AZ	61	# define PXA2XX_SDRAM_BASE 0xa0000000
d95b2f8d AZ	62	# define PXA2XX_INTERNAL_BASE 0x5c000000
a07dec22	63	# define PXA2XX_INTERNAL_SIZE 0x40000
c1713132 AZ	64
c1713132 AZ	65	/* pxa2xx_pic.c */
c1713132 AZ	66	qemu_irq pxa2xx_pic_init(target_phys_addr_t base, CPUState env);
c1713132 AZ	67
a171fe39	68	/* pxa2xx_timer.c */
3f582262 AZ	69	void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
3f582262 AZ	70	void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
a171fe39	71
c1713132 AZ	72	/* pxa2xx_gpio.c */
	73	struct pxa2xx_gpio_info_s;
	74	struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
	75	CPUState env, qemu_irq pic, int lines);
38641a52 AZ	76	qemu_irq pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s s);
	77	void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s,
	78	int line, qemu_irq handler);
	79	void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler);
c1713132 AZ	80
	81	/* pxa2xx_dma.c */
	82	struct pxa2xx_dma_state_s;
	83	struct pxa2xx_dma_state_s *pxa255_dma_init(target_phys_addr_t base,
	84	qemu_irq irq);
	85	struct pxa2xx_dma_state_s *pxa27x_dma_init(target_phys_addr_t base,
	86	qemu_irq irq);
	87	void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);
	88
a171fe39 AZ	89	/* pxa2xx_lcd.c */
	90	struct pxa2xx_lcdc_s;
	91	struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
	92	qemu_irq irq, DisplayState *ds);
38641a52	93	void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler);
a171fe39 AZ	94	void pxa2xx_lcdc_oritentation(void *opaque, int angle);
	95
	96	/* pxa2xx_mmci.c */
	97	struct pxa2xx_mmci_s;
	98	struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
87ecb68b	99	BlockDriverState bd, qemu_irq irq, void dma);
02ce600c AZ	100	void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly,
02ce600c AZ	101	qemu_irq coverswitch);
a171fe39 AZ	102
	103	/* pxa2xx_pcmcia.c */
	104	struct pxa2xx_pcmcia_s;
	105	struct pxa2xx_pcmcia_s *pxa2xx_pcmcia_init(target_phys_addr_t base);
	106	int pxa2xx_pcmcia_attach(void opaque, struct pcmcia_card_s card);
	107	int pxa2xx_pcmcia_dettach(void *opaque);
	108	void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
	109
31b87f2e AZ	110	/* pxa2xx_keypad.c */
	111	struct keymap {
	112	int column;
	113	int row;
	114	};
	115	struct pxa2xx_keypad_s;
	116	struct pxa2xx_keypad_s *pxa27x_keypad_init(target_phys_addr_t base,
	117	qemu_irq irq);
	118	void pxa27x_register_keypad(struct pxa2xx_keypad_s kp, struct keymap map,
	119	int size);
	120
c1713132 AZ	121	/* pxa2xx.c */
	122	struct pxa2xx_ssp_s;
	123	void pxa2xx_ssp_attach(struct pxa2xx_ssp_s *port,
	124	uint32_t (readfn)(void opaque),
	125	void (writefn)(void opaque, uint32_t value), void *opaque);
	126
3f582262 AZ	127	struct pxa2xx_i2c_s;
3f582262 AZ	128	struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
2a163929	129	qemu_irq irq, uint32_t page_size);
3f582262 AZ	130	i2c_bus pxa2xx_i2c_bus(struct pxa2xx_i2c_s s);
3f582262 AZ	131
c1713132 AZ	132	struct pxa2xx_i2s_s;
	133	struct pxa2xx_fir_s;
	134
	135	struct pxa2xx_state_s {
	136	CPUState *env;
	137	qemu_irq *pic;
38641a52	138	qemu_irq reset;
c1713132 AZ	139	struct pxa2xx_dma_state_s *dma;
c1713132 AZ	140	struct pxa2xx_gpio_info_s *gpio;
a171fe39	141	struct pxa2xx_lcdc_s *lcd;
c1713132	142	struct pxa2xx_ssp_s **ssp;
3f582262	143	struct pxa2xx_i2c_s *i2c[2];
a171fe39 AZ	144	struct pxa2xx_mmci_s *mmc;
a171fe39 AZ	145	struct pxa2xx_pcmcia_s *pcmcia[2];
c1713132 AZ	146	struct pxa2xx_i2s_s *i2s;
c1713132 AZ	147	struct pxa2xx_fir_s *fir;
31b87f2e	148	struct pxa2xx_keypad_s *kp;
c1713132 AZ	149
	150	/* Power management */
	151	target_phys_addr_t pm_base;
	152	uint32_t pm_regs[0x40];
	153
	154	/* Clock management */
	155	target_phys_addr_t cm_base;
	156	uint32_t cm_regs[4];
	157	uint32_t clkcfg;
	158
	159	/* Memory management */
	160	target_phys_addr_t mm_base;
	161	uint32_t mm_regs[0x1a];
	162
	163	/* Performance monitoring */
	164	uint32_t pmnc;
	165
	166	/* Real-Time clock */
	167	target_phys_addr_t rtc_base;
	168	uint32_t rttr;
	169	uint32_t rtsr;
	170	uint32_t rtar;
	171	uint32_t rdar1;
	172	uint32_t rdar2;
	173	uint32_t ryar1;
	174	uint32_t ryar2;
	175	uint32_t swar1;
	176	uint32_t swar2;
	177	uint32_t piar;
	178	uint32_t last_rcnr;
	179	uint32_t last_rdcr;
	180	uint32_t last_rycr;
	181	uint32_t last_swcr;
	182	uint32_t last_rtcpicr;
	183	int64_t last_hz;
	184	int64_t last_sw;
	185	int64_t last_pi;
	186	QEMUTimer *rtc_hz;
	187	QEMUTimer *rtc_rdal1;
	188	QEMUTimer *rtc_rdal2;
	189	QEMUTimer *rtc_swal1;
	190	QEMUTimer *rtc_swal2;
	191	QEMUTimer *rtc_pi;
	192	};
	193
	194	struct pxa2xx_i2s_s {
	195	target_phys_addr_t base;
	196	qemu_irq irq;
	197	struct pxa2xx_dma_state_s *dma;
	198	void (data_req)(void , int, int);
	199
	200	uint32_t control[2];
	201	uint32_t status;
	202	uint32_t mask;
	203	uint32_t clk;
	204
	205	int enable;
	206	int rx_len;
	207	int tx_len;
	208	void (codec_out)(void , uint32_t);
	209	uint32_t (codec_in)(void );
	210	void *opaque;
	211
	212	int fifo_len;
213	uint32_t fifo[16];
214	};
215
216	# define PA_FMT "0x%08lx"
444ce241	217	# define REG_FMT "0x" TARGET_FMT_plx
c1713132	218
d95b2f8d AZ	219	struct pxa2xx_state_s pxa270_init(unsigned int sdram_size, DisplayState ds,
	220	const char *revision);
	221	struct pxa2xx_state_s pxa255_init(unsigned int sdram_size, DisplayState ds);
c1713132	222
87ecb68b PB	223	/* usb-ohci.c */
	224	void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
	225	qemu_irq irq);
	226
c1713132	227	#endif /* PXA_H */