[qemu.git] / hw / slavio_intctl.c

/*
 * QEMU Sparc SLAVIO interrupt controller emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sun4m.h"
#include "monitor.h"

//#define DEBUG_IRQ_COUNT
//#define DEBUG_IRQ

#ifdef DEBUG_IRQ
#define DPRINTF(fmt, ...)                                       \
    do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
#else
#define DPRINTF(fmt, ...)
#endif

/*
 * Registers of interrupt controller in sun4m.
 *
 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * There is a system master controller and one for each cpu.
 *
 */

#define MAX_CPUS 16
#define MAX_PILS 16

struct SLAVIO_CPUINTCTLState;

typedef struct SLAVIO_INTCTLState {
    uint32_t intregm_pending;
    uint32_t intregm_disabled;
    uint32_t target_cpu;
#ifdef DEBUG_IRQ_COUNT
    uint64_t irq_count[32];
#endif
    qemu_irq *cpu_irqs[MAX_CPUS];
    const uint32_t *intbit_to_level;
    uint32_t cputimer_lbit, cputimer_mbit;
    uint32_t pil_out[MAX_CPUS];
    struct SLAVIO_CPUINTCTLState *slaves[MAX_CPUS];
} SLAVIO_INTCTLState;

typedef struct SLAVIO_CPUINTCTLState {
    uint32_t intreg_pending;
    SLAVIO_INTCTLState *master;
    uint32_t cpu;
} SLAVIO_CPUINTCTLState;

#define INTCTL_MAXADDR 0xf
#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
#define INTCTLM_SIZE 0x14
#define MASTER_IRQ_MASK ~0x0fa2007f
#define MASTER_DISABLE 0x80000000
#define CPU_SOFTIRQ_MASK 0xfffe0000
#define CPU_IRQ_INT15_IN 0x0004000
#define CPU_IRQ_INT15_MASK 0x80000000

static void slavio_check_interrupts(SLAVIO_INTCTLState *s);

// per-cpu interrupt controller
static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_CPUINTCTLState *s = opaque;
    uint32_t saddr, ret;

    saddr = addr >> 2;
    switch (saddr) {
    case 0:
        ret = s->intreg_pending;
        break;
    default:
        ret = 0;
        break;
    }
    DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);

    return ret;
}

static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
                                     uint32_t val)
{
    SLAVIO_CPUINTCTLState *s = opaque;
    uint32_t saddr;

    saddr = addr >> 2;
    DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
    switch (saddr) {
    case 1: // clear pending softints
        if (val & CPU_IRQ_INT15_IN)
            val |= CPU_IRQ_INT15_MASK;
        val &= CPU_SOFTIRQ_MASK;
        s->intreg_pending &= ~val;
        slavio_check_interrupts(s->master);
        DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
                s->intreg_pending);
        break;
    case 2: // set softint
        val &= CPU_SOFTIRQ_MASK;
        s->intreg_pending |= val;
        slavio_check_interrupts(s->master);
        DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
                s->intreg_pending);
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
    NULL,
    NULL,
    slavio_intctl_mem_readl,
};

static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
    NULL,
    NULL,
    slavio_intctl_mem_writel,
};

// master system interrupt controller
static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr, ret;

    saddr = addr >> 2;
    switch (saddr) {
    case 0:
        ret = s->intregm_pending & ~MASTER_DISABLE;
        break;
    case 1:
        ret = s->intregm_disabled & MASTER_IRQ_MASK;
        break;
    case 4:
        ret = s->target_cpu;
        break;
    default:
        ret = 0;
        break;
    }
    DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);

    return ret;
}

static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
                                      uint32_t val)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;

    saddr = addr >> 2;
    DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
    switch (saddr) {
    case 2: // clear (enable)
        // Force clear unused bits
        val &= MASTER_IRQ_MASK;
        s->intregm_disabled &= ~val;
        DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
                s->intregm_disabled);
        slavio_check_interrupts(s);
        break;
    case 3: // set (disable, clear pending)
        // Force clear unused bits
        val &= MASTER_IRQ_MASK;
        s->intregm_disabled |= val;
        s->intregm_pending &= ~val;
        slavio_check_interrupts(s);
        DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
                s->intregm_disabled);
        break;
    case 4:
        s->target_cpu = val & (MAX_CPUS - 1);
        slavio_check_interrupts(s);
        DPRINTF("Set master irq cpu %d\n", s->target_cpu);
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
    NULL,
    NULL,
    slavio_intctlm_mem_readl,
};

static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
    NULL,
    NULL,
    slavio_intctlm_mem_writel,
};

void slavio_pic_info(Monitor *mon, void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    for (i = 0; i < MAX_CPUS; i++) {
        monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
                       s->slaves[i]->intreg_pending);
    }
    monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
                   s->intregm_pending, s->intregm_disabled);
}

void slavio_irq_info(Monitor *mon, void *opaque)
{
#ifndef DEBUG_IRQ_COUNT
    monitor_printf(mon, "irq statistic code not compiled.\n");
#else
    SLAVIO_INTCTLState *s = opaque;
    int i;
    int64_t count;

    monitor_printf(mon, "IRQ statistics:\n");
    for (i = 0; i < 32; i++) {
        count = s->irq_count[i];
        if (count > 0)
            monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
    }
#endif
}

static void slavio_check_interrupts(SLAVIO_INTCTLState *s)
{
    uint32_t pending = s->intregm_pending, pil_pending;
    unsigned int i, j;

    pending &= ~s->intregm_disabled;

    DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
    for (i = 0; i < MAX_CPUS; i++) {
        pil_pending = 0;
        if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
            (i == s->target_cpu)) {
            for (j = 0; j < 32; j++) {
                if (pending & (1 << j))
                    pil_pending |= 1 << s->intbit_to_level[j];
            }
        }
        pil_pending |= (s->slaves[i]->intreg_pending & CPU_SOFTIRQ_MASK) >> 16;

        for (j = 0; j < MAX_PILS; j++) {
            if (pil_pending & (1 << j)) {
                if (!(s->pil_out[i] & (1 << j)))
                    qemu_irq_raise(s->cpu_irqs[i][j]);
            } else {
                if (s->pil_out[i] & (1 << j))
                    qemu_irq_lower(s->cpu_irqs[i][j]);
            }
        }
        s->pil_out[i] = pil_pending;
    }
}

/*
 * "irq" here is the bit number in the system interrupt register to
 * separate serial and keyboard interrupts sharing a level.
 */
static void slavio_set_irq(void *opaque, int irq, int level)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t mask = 1 << irq;
    uint32_t pil = s->intbit_to_level[irq];

    DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
            level);
    if (pil > 0) {
        if (level) {
#ifdef DEBUG_IRQ_COUNT
            s->irq_count[pil]++;
#endif
            s->intregm_pending |= mask;
            s->slaves[s->target_cpu]->intreg_pending |= 1 << pil;
        } else {
            s->intregm_pending &= ~mask;
            s->slaves[s->target_cpu]->intreg_pending &= ~(1 << pil);
        }
        slavio_check_interrupts(s);
    }
}

static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
{
    SLAVIO_INTCTLState *s = opaque;

    DPRINTF("Set cpu %d local timer level %d\n", cpu, level);

    if (level) {
        s->intregm_pending |= s->cputimer_mbit;
        s->slaves[cpu]->intreg_pending |= s->cputimer_lbit;
    } else {
        s->intregm_pending &= ~s->cputimer_mbit;
        s->slaves[cpu]->intreg_pending &= ~s->cputimer_lbit;
    }

    slavio_check_interrupts(s);
}

static void slavio_intctl_save(QEMUFile *f, void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    for (i = 0; i < MAX_CPUS; i++) {
        qemu_put_be32s(f, &s->slaves[i]->intreg_pending);
    }
    qemu_put_be32s(f, &s->intregm_pending);
    qemu_put_be32s(f, &s->intregm_disabled);
    qemu_put_be32s(f, &s->target_cpu);
}

static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    if (version_id != 1)
        return -EINVAL;

    for (i = 0; i < MAX_CPUS; i++) {
        qemu_get_be32s(f, &s->slaves[i]->intreg_pending);
    }
    qemu_get_be32s(f, &s->intregm_pending);
    qemu_get_be32s(f, &s->intregm_disabled);
    qemu_get_be32s(f, &s->target_cpu);
    slavio_check_interrupts(s);
    return 0;
}

static void slavio_intctl_reset(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    for (i = 0; i < MAX_CPUS; i++) {
        s->slaves[i]->intreg_pending = 0;
    }
    s->intregm_disabled = ~MASTER_IRQ_MASK;
    s->intregm_pending = 0;
    s->target_cpu = 0;
    slavio_check_interrupts(s);
}

void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
                         const uint32_t *intbit_to_level,
                         qemu_irq **irq, qemu_irq **cpu_irq,
                         qemu_irq **parent_irq, unsigned int cputimer)
{
    int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
    SLAVIO_INTCTLState *s;
    SLAVIO_CPUINTCTLState *slave;

    s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));

    s->intbit_to_level = intbit_to_level;
    for (i = 0; i < MAX_CPUS; i++) {
        slave = qemu_mallocz(sizeof(SLAVIO_CPUINTCTLState));

        slave->cpu = i;
        slave->master = s;

        slavio_intctl_io_memory = cpu_register_io_memory(0,
                                                         slavio_intctl_mem_read,
                                                         slavio_intctl_mem_write,
                                                         slave);
        cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
                                     slavio_intctl_io_memory);

        s->slaves[i] = slave;
        s->cpu_irqs[i] = parent_irq[i];
    }

    slavio_intctlm_io_memory = cpu_register_io_memory(0,
                                                      slavio_intctlm_mem_read,
                                                      slavio_intctlm_mem_write,
                                                      s);
    cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);

    register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
                    slavio_intctl_load, s);
    qemu_register_reset(slavio_intctl_reset, s);
    *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);

    *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
    s->cputimer_mbit = 1 << cputimer;
    s->cputimer_lbit = 1 << intbit_to_level[cputimer];
    slavio_intctl_reset(s);
    return s;
}
Commit	Line	Data
e80cfcfc FB	1	/*
e80cfcfc FB	2	* QEMU Sparc SLAVIO interrupt controller emulation
5fafdf24	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
e80cfcfc FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
87ecb68b PB	25	#include "sun4m.h"
376253ec	26	#include "monitor.h"
87ecb68b	27
e80cfcfc	28	//#define DEBUG_IRQ_COUNT
66321a11 FB	29	//#define DEBUG_IRQ
	30
	31	#ifdef DEBUG_IRQ
001faf32 BS	32	#define DPRINTF(fmt, ...) \
001faf32 BS	33	do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
66321a11	34	#else
001faf32	35	#define DPRINTF(fmt, ...)
66321a11	36	#endif
e80cfcfc FB	37
	38	/*
	39	* Registers of interrupt controller in sun4m.
	40	*
	41	* This is the interrupt controller part of chip STP2001 (Slave I/O), also
	42	* produced as NCR89C105. See
	43	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	44	*
	45	* There is a system master controller and one for each cpu.
5fafdf24	46	*
e80cfcfc FB	47	*/
	48
	49	#define MAX_CPUS 16
b3a23197	50	#define MAX_PILS 16
e80cfcfc	51
a8f48dcc BS	52	struct SLAVIO_CPUINTCTLState;
a8f48dcc BS	53
e80cfcfc	54	typedef struct SLAVIO_INTCTLState {
e80cfcfc FB	55	uint32_t intregm_pending;
	56	uint32_t intregm_disabled;
	57	uint32_t target_cpu;
	58	#ifdef DEBUG_IRQ_COUNT
	59	uint64_t irq_count[32];
	60	#endif
b3a23197	61	qemu_irq *cpu_irqs[MAX_CPUS];
e0353fe2	62	const uint32_t *intbit_to_level;
e3a79bca	63	uint32_t cputimer_lbit, cputimer_mbit;
b3a23197	64	uint32_t pil_out[MAX_CPUS];
a8f48dcc	65	struct SLAVIO_CPUINTCTLState *slaves[MAX_CPUS];
e80cfcfc FB	66	} SLAVIO_INTCTLState;
e80cfcfc FB	67
a8f48dcc BS	68	typedef struct SLAVIO_CPUINTCTLState {
	69	uint32_t intreg_pending;
	70	SLAVIO_INTCTLState *master;
	71	uint32_t cpu;
	72	} SLAVIO_CPUINTCTLState;
	73
e80cfcfc	74	#define INTCTL_MAXADDR 0xf
5aca8c3b	75	#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
a8f48dcc	76	#define INTCTLM_SIZE 0x14
80be36b8	77	#define MASTER_IRQ_MASK ~0x0fa2007f
9a87ce9b	78	#define MASTER_DISABLE 0x80000000
6341fdcb	79	#define CPU_SOFTIRQ_MASK 0xfffe0000
9a87ce9b BS	80	#define CPU_IRQ_INT15_IN 0x0004000
	81	#define CPU_IRQ_INT15_MASK 0x80000000
	82
a8f48dcc	83	static void slavio_check_interrupts(SLAVIO_INTCTLState *s);
e80cfcfc FB	84
	85	// per-cpu interrupt controller
	86	static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
	87	{
a8f48dcc	88	SLAVIO_CPUINTCTLState *s = opaque;
dd4131b3	89	uint32_t saddr, ret;
e80cfcfc	90
a8f48dcc	91	saddr = addr >> 2;
e80cfcfc FB	92	switch (saddr) {
e80cfcfc FB	93	case 0:
a8f48dcc	94	ret = s->intreg_pending;
dd4131b3	95	break;
e80cfcfc	96	default:
dd4131b3 BS	97	ret = 0;
dd4131b3 BS	98	break;
e80cfcfc	99	}
3c4cf535	100	DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
dd4131b3 BS	101
dd4131b3 BS	102	return ret;
e80cfcfc FB	103	}
e80cfcfc FB	104
77f193da BS	105	static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
77f193da BS	106	uint32_t val)
e80cfcfc	107	{
a8f48dcc	108	SLAVIO_CPUINTCTLState *s = opaque;
e80cfcfc	109	uint32_t saddr;
e80cfcfc	110
a8f48dcc	111	saddr = addr >> 2;
3c4cf535	112	DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
e80cfcfc FB	113	switch (saddr) {
e80cfcfc FB	114	case 1: // clear pending softints
9a87ce9b BS	115	if (val & CPU_IRQ_INT15_IN)
9a87ce9b BS	116	val \|= CPU_IRQ_INT15_MASK;
6341fdcb	117	val &= CPU_SOFTIRQ_MASK;
a8f48dcc BS	118	s->intreg_pending &= ~val;
	119	slavio_check_interrupts(s->master);
	120	DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
	121	s->intreg_pending);
f930d07e	122	break;
e80cfcfc	123	case 2: // set softint
6341fdcb	124	val &= CPU_SOFTIRQ_MASK;
a8f48dcc BS	125	s->intreg_pending \|= val;
	126	slavio_check_interrupts(s->master);
	127	DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
	128	s->intreg_pending);
f930d07e	129	break;
e80cfcfc	130	default:
f930d07e	131	break;
e80cfcfc FB	132	}
	133	}
	134
	135	static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
7c560456 BS	136	NULL,
7c560456 BS	137	NULL,
e80cfcfc FB	138	slavio_intctl_mem_readl,
	139	};
	140
	141	static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
7c560456 BS	142	NULL,
7c560456 BS	143	NULL,
e80cfcfc FB	144	slavio_intctl_mem_writel,
	145	};
	146
	147	// master system interrupt controller
	148	static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
	149	{
	150	SLAVIO_INTCTLState *s = opaque;
dd4131b3	151	uint32_t saddr, ret;
e80cfcfc	152
a8f48dcc	153	saddr = addr >> 2;
e80cfcfc FB	154	switch (saddr) {
e80cfcfc FB	155	case 0:
9a87ce9b	156	ret = s->intregm_pending & ~MASTER_DISABLE;
dd4131b3	157	break;
e80cfcfc	158	case 1:
80be36b8	159	ret = s->intregm_disabled & MASTER_IRQ_MASK;
dd4131b3	160	break;
e80cfcfc	161	case 4:
dd4131b3 BS	162	ret = s->target_cpu;
dd4131b3 BS	163	break;
e80cfcfc	164	default:
dd4131b3 BS	165	ret = 0;
dd4131b3 BS	166	break;
e80cfcfc	167	}
1569fc29	168	DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
dd4131b3 BS	169
dd4131b3 BS	170	return ret;
e80cfcfc FB	171	}
e80cfcfc FB	172
77f193da BS	173	static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
77f193da BS	174	uint32_t val)
e80cfcfc FB	175	{
	176	SLAVIO_INTCTLState *s = opaque;
	177	uint32_t saddr;
	178
a8f48dcc	179	saddr = addr >> 2;
1569fc29	180	DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
e80cfcfc FB	181	switch (saddr) {
e80cfcfc FB	182	case 2: // clear (enable)
f930d07e	183	// Force clear unused bits
9a87ce9b	184	val &= MASTER_IRQ_MASK;
f930d07e	185	s->intregm_disabled &= ~val;
77f193da BS	186	DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
77f193da BS	187	s->intregm_disabled);
f930d07e BS	188	slavio_check_interrupts(s);
f930d07e BS	189	break;
e80cfcfc	190	case 3: // set (disable, clear pending)
f930d07e	191	// Force clear unused bits
9a87ce9b	192	val &= MASTER_IRQ_MASK;
f930d07e BS	193	s->intregm_disabled \|= val;
f930d07e BS	194	s->intregm_pending &= ~val;
327ac2e7	195	slavio_check_interrupts(s);
77f193da BS	196	DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
77f193da BS	197	s->intregm_disabled);
f930d07e	198	break;
e80cfcfc	199	case 4:
f930d07e	200	s->target_cpu = val & (MAX_CPUS - 1);
327ac2e7	201	slavio_check_interrupts(s);
f930d07e BS	202	DPRINTF("Set master irq cpu %d\n", s->target_cpu);
f930d07e BS	203	break;
e80cfcfc	204	default:
f930d07e	205	break;
e80cfcfc FB	206	}
	207	}
	208
	209	static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
7c560456 BS	210	NULL,
7c560456 BS	211	NULL,
e80cfcfc FB	212	slavio_intctlm_mem_readl,
	213	};
	214
	215	static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
7c560456 BS	216	NULL,
7c560456 BS	217	NULL,
e80cfcfc FB	218	slavio_intctlm_mem_writel,
	219	};
	220
376253ec	221	void slavio_pic_info(Monitor mon, void opaque)
e80cfcfc FB	222	{
	223	SLAVIO_INTCTLState *s = opaque;
	224	int i;
	225
	226	for (i = 0; i < MAX_CPUS; i++) {
376253ec AL	227	monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
376253ec AL	228	s->slaves[i]->intreg_pending);
e80cfcfc	229	}
376253ec AL	230	monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
376253ec AL	231	s->intregm_pending, s->intregm_disabled);
e80cfcfc FB	232	}
e80cfcfc FB	233
376253ec	234	void slavio_irq_info(Monitor mon, void opaque)
e80cfcfc FB	235	{
e80cfcfc FB	236	#ifndef DEBUG_IRQ_COUNT
376253ec	237	monitor_printf(mon, "irq statistic code not compiled.\n");
e80cfcfc FB	238	#else
	239	SLAVIO_INTCTLState *s = opaque;
	240	int i;
	241	int64_t count;
	242
376253ec	243	monitor_printf(mon, "IRQ statistics:\n");
e80cfcfc FB	244	for (i = 0; i < 32; i++) {
	245	count = s->irq_count[i];
	246	if (count > 0)
376253ec	247	monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
e80cfcfc FB	248	}
	249	#endif
	250	}
	251
a8f48dcc	252	static void slavio_check_interrupts(SLAVIO_INTCTLState *s)
66321a11	253	{
327ac2e7 BS	254	uint32_t pending = s->intregm_pending, pil_pending;
327ac2e7 BS	255	unsigned int i, j;
66321a11 FB	256
	257	pending &= ~s->intregm_disabled;
	258
b3a23197	259	DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
ba3c64fb	260	for (i = 0; i < MAX_CPUS; i++) {
327ac2e7	261	pil_pending = 0;
9a87ce9b	262	if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
b3a23197 BS	263	(i == s->target_cpu)) {
b3a23197 BS	264	for (j = 0; j < 32; j++) {
327ac2e7 BS	265	if (pending & (1 << j))
327ac2e7 BS	266	pil_pending \|= 1 << s->intbit_to_level[j];
b3a23197 BS	267	}
b3a23197 BS	268	}
a8f48dcc	269	pil_pending \|= (s->slaves[i]->intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
327ac2e7 BS	270
	271	for (j = 0; j < MAX_PILS; j++) {
	272	if (pil_pending & (1 << j)) {
	273	if (!(s->pil_out[i] & (1 << j)))
	274	qemu_irq_raise(s->cpu_irqs[i][j]);
	275	} else {
	276	if (s->pil_out[i] & (1 << j))
	277	qemu_irq_lower(s->cpu_irqs[i][j]);
ba3c64fb FB	278	}
ba3c64fb FB	279	}
327ac2e7	280	s->pil_out[i] = pil_pending;
ba3c64fb	281	}
66321a11 FB	282	}
66321a11 FB	283
e80cfcfc FB	284	/*
	285	* "irq" here is the bit number in the system interrupt register to
	286	* separate serial and keyboard interrupts sharing a level.
	287	*/
d7edfd27	288	static void slavio_set_irq(void *opaque, int irq, int level)
e80cfcfc FB	289	{
e80cfcfc FB	290	SLAVIO_INTCTLState *s = opaque;
b3a23197 BS	291	uint32_t mask = 1 << irq;
	292	uint32_t pil = s->intbit_to_level[irq];
	293
	294	DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
	295	level);
	296	if (pil > 0) {
	297	if (level) {
327ac2e7 BS	298	#ifdef DEBUG_IRQ_COUNT
	299	s->irq_count[pil]++;
	300	#endif
b3a23197	301	s->intregm_pending \|= mask;
a8f48dcc	302	s->slaves[s->target_cpu]->intreg_pending \|= 1 << pil;
b3a23197 BS	303	} else {
b3a23197 BS	304	s->intregm_pending &= ~mask;
a8f48dcc	305	s->slaves[s->target_cpu]->intreg_pending &= ~(1 << pil);
b3a23197 BS	306	}
b3a23197 BS	307	slavio_check_interrupts(s);
e80cfcfc FB	308	}
	309	}
	310
d7edfd27	311	static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
ba3c64fb FB	312	{
	313	SLAVIO_INTCTLState *s = opaque;
	314
b3a23197	315	DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
d7edfd27	316
e3a79bca BS	317	if (level) {
e3a79bca BS	318	s->intregm_pending \|= s->cputimer_mbit;
a8f48dcc	319	s->slaves[cpu]->intreg_pending \|= s->cputimer_lbit;
e3a79bca BS	320	} else {
e3a79bca BS	321	s->intregm_pending &= ~s->cputimer_mbit;
a8f48dcc	322	s->slaves[cpu]->intreg_pending &= ~s->cputimer_lbit;
e3a79bca	323	}
d7edfd27	324
ba3c64fb FB	325	slavio_check_interrupts(s);
	326	}
	327
e80cfcfc FB	328	static void slavio_intctl_save(QEMUFile f, void opaque)
	329	{
	330	SLAVIO_INTCTLState *s = opaque;
	331	int i;
3b46e624	332
e80cfcfc	333	for (i = 0; i < MAX_CPUS; i++) {
a8f48dcc	334	qemu_put_be32s(f, &s->slaves[i]->intreg_pending);
e80cfcfc FB	335	}
	336	qemu_put_be32s(f, &s->intregm_pending);
	337	qemu_put_be32s(f, &s->intregm_disabled);
	338	qemu_put_be32s(f, &s->target_cpu);
	339	}
	340
	341	static int slavio_intctl_load(QEMUFile f, void opaque, int version_id)
	342	{
	343	SLAVIO_INTCTLState *s = opaque;
	344	int i;
	345
	346	if (version_id != 1)
	347	return -EINVAL;
	348
	349	for (i = 0; i < MAX_CPUS; i++) {
a8f48dcc	350	qemu_get_be32s(f, &s->slaves[i]->intreg_pending);
e80cfcfc FB	351	}
	352	qemu_get_be32s(f, &s->intregm_pending);
	353	qemu_get_be32s(f, &s->intregm_disabled);
	354	qemu_get_be32s(f, &s->target_cpu);
327ac2e7	355	slavio_check_interrupts(s);
e80cfcfc FB	356	return 0;
	357	}
	358
	359	static void slavio_intctl_reset(void *opaque)
	360	{
	361	SLAVIO_INTCTLState *s = opaque;
	362	int i;
	363
	364	for (i = 0; i < MAX_CPUS; i++) {
a8f48dcc	365	s->slaves[i]->intreg_pending = 0;
e80cfcfc	366	}
9a87ce9b	367	s->intregm_disabled = ~MASTER_IRQ_MASK;
e80cfcfc FB	368	s->intregm_pending = 0;
e80cfcfc FB	369	s->target_cpu = 0;
327ac2e7	370	slavio_check_interrupts(s);
e80cfcfc FB	371	}
e80cfcfc FB	372
5dcb6b91	373	void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
d537cf6c	374	const uint32_t *intbit_to_level,
d7edfd27	375	qemu_irq irq, qemu_irq cpu_irq,
b3a23197	376	qemu_irq **parent_irq, unsigned int cputimer)
e80cfcfc FB	377	{
	378	int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
	379	SLAVIO_INTCTLState *s;
a8f48dcc	380	SLAVIO_CPUINTCTLState *slave;
e80cfcfc FB	381
e80cfcfc FB	382	s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
e80cfcfc	383
e0353fe2	384	s->intbit_to_level = intbit_to_level;
e80cfcfc	385	for (i = 0; i < MAX_CPUS; i++) {
a8f48dcc	386	slave = qemu_mallocz(sizeof(SLAVIO_CPUINTCTLState));
a8f48dcc BS	387
	388	slave->cpu = i;
	389	slave->master = s;
	390
77f193da BS	391	slavio_intctl_io_memory = cpu_register_io_memory(0,
	392	slavio_intctl_mem_read,
	393	slavio_intctl_mem_write,
a8f48dcc BS	394	slave);
	395	cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
	396	slavio_intctl_io_memory);
	397
	398	s->slaves[i] = slave;
b3a23197	399	s->cpu_irqs[i] = parent_irq[i];
e80cfcfc FB	400	}
e80cfcfc FB	401
77f193da BS	402	slavio_intctlm_io_memory = cpu_register_io_memory(0,
	403	slavio_intctlm_mem_read,
	404	slavio_intctlm_mem_write,
	405	s);
5aca8c3b	406	cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
e80cfcfc	407
77f193da BS	408	register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
77f193da BS	409	slavio_intctl_load, s);
e80cfcfc	410	qemu_register_reset(slavio_intctl_reset, s);
d537cf6c	411	*irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
d7edfd27 BS	412
d7edfd27 BS	413	*cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
e3a79bca BS	414	s->cputimer_mbit = 1 << cputimer;
e3a79bca BS	415	s->cputimer_lbit = 1 << intbit_to_level[cputimer];
e80cfcfc FB	416	slavio_intctl_reset(s);
	417	return s;
	418	}