]> Git Repo - qemu.git/blame - tcg/riscv/tcg-target.inc.c
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tcg/riscv: Add the prologue generation and register the JIT
[qemu.git] / tcg / riscv / tcg-target.inc.c
CommitLineData
505e75c5
AF		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2018 SiFive, Inc
5 * Copyright (c) 2008-2009 Arnaud Patard <[email protected]>
6 * Copyright (c) 2009 Aurelien Jarno <[email protected]>
7 * Copyright (c) 2008 Fabrice Bellard
8 *
9 * Based on i386/tcg-target.c and mips/tcg-target.c
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a copy
12 * of this software and associated documentation files (the "Software"), to deal
13 * in the Software without restriction, including without limitation the rights
14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
15 * copies of the Software, and to permit persons to whom the Software is
16 * furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice shall be included in
19 * all copies or substantial portions of the Software.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 * THE SOFTWARE.
28 */
29
30#include "tcg-pool.inc.c"
31
32#ifdef CONFIG_DEBUG_TCG
33static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
34 "zero",
35 "ra",
36 "sp",
37 "gp",
38 "tp",
39 "t0",
40 "t1",
41 "t2",
42 "s0",
43 "s1",
44 "a0",
45 "a1",
46 "a2",
47 "a3",
48 "a4",
49 "a5",
50 "a6",
51 "a7",
52 "s2",
53 "s3",
54 "s4",
55 "s5",
56 "s6",
57 "s7",
58 "s8",
59 "s9",
60 "s10",
61 "s11",
62 "t3",
63 "t4",
64 "t5",
65 "t6"
66};
67#endif
68
69static const int tcg_target_reg_alloc_order[] = {
70 /* Call saved registers */
71 /* TCG_REG_S0 reservered for TCG_AREG0 */
72 TCG_REG_S1,
73 TCG_REG_S2,
74 TCG_REG_S3,
75 TCG_REG_S4,
76 TCG_REG_S5,
77 TCG_REG_S6,
78 TCG_REG_S7,
79 TCG_REG_S8,
80 TCG_REG_S9,
81 TCG_REG_S10,
82 TCG_REG_S11,
83
84 /* Call clobbered registers */
85 TCG_REG_T0,
86 TCG_REG_T1,
87 TCG_REG_T2,
88 TCG_REG_T3,
89 TCG_REG_T4,
90 TCG_REG_T5,
91 TCG_REG_T6,
92
93 /* Argument registers */
94 TCG_REG_A0,
95 TCG_REG_A1,
96 TCG_REG_A2,
97 TCG_REG_A3,
98 TCG_REG_A4,
99 TCG_REG_A5,
100 TCG_REG_A6,
101 TCG_REG_A7,
102};
103
104static const int tcg_target_call_iarg_regs[] = {
105 TCG_REG_A0,
106 TCG_REG_A1,
107 TCG_REG_A2,
108 TCG_REG_A3,
109 TCG_REG_A4,
110 TCG_REG_A5,
111 TCG_REG_A6,
112 TCG_REG_A7,
113};
114
115static const int tcg_target_call_oarg_regs[] = {
116 TCG_REG_A0,
117 TCG_REG_A1,
118};
8ce23a13
AF		 119
120#define TCG_CT_CONST_ZERO 0x100
121#define TCG_CT_CONST_S12 0x200
122#define TCG_CT_CONST_N12 0x400
123#define TCG_CT_CONST_M12 0x800
124
125static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
126{
127 if (TCG_TARGET_REG_BITS == 32) {
128 return sextract32(val, pos, len);
129 } else {
130 return sextract64(val, pos, len);
131 }
132}
133
134/* parse target specific constraints */
135static const char *target_parse_constraint(TCGArgConstraint *ct,
136 const char *ct_str, TCGType type)
137{
138 switch (*ct_str++) {
139 case 'r':
140 ct->ct |= TCG_CT_REG;
141 ct->u.regs = 0xffffffff;
142 break;
143 case 'L':
144 /* qemu_ld/qemu_st constraint */
145 ct->ct |= TCG_CT_REG;
146 ct->u.regs = 0xffffffff;
147 /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
148#if defined(CONFIG_SOFTMMU)
149 tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
150 tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
151 tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
152 tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
153 tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
154#endif
155 break;
156 case 'I':
157 ct->ct |= TCG_CT_CONST_S12;
158 break;
159 case 'N':
160 ct->ct |= TCG_CT_CONST_N12;
161 break;
162 case 'M':
163 ct->ct |= TCG_CT_CONST_M12;
164 break;
165 case 'Z':
166 /* we can use a zero immediate as a zero register argument. */
167 ct->ct |= TCG_CT_CONST_ZERO;
168 break;
169 default:
170 return NULL;
171 }
172 return ct_str;
173}
174
175/* test if a constant matches the constraint */
176static int tcg_target_const_match(tcg_target_long val, TCGType type,
177 const TCGArgConstraint *arg_ct)
178{
179 int ct = arg_ct->ct;
180 if (ct & TCG_CT_CONST) {
181 return 1;
182 }
183 if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
184 return 1;
185 }
186 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
187 return 1;
188 }
189 if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) {
190 return 1;
191 }
192 if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) {
193 return 1;
194 }
195 return 0;
196}
197
198/*
199 * RISC-V Base ISA opcodes (IM)
200 */
201
202typedef enum {
203 OPC_ADD = 0x33,
204 OPC_ADDI = 0x13,
205 OPC_AND = 0x7033,
206 OPC_ANDI = 0x7013,
207 OPC_AUIPC = 0x17,
208 OPC_BEQ = 0x63,
209 OPC_BGE = 0x5063,
210 OPC_BGEU = 0x7063,
211 OPC_BLT = 0x4063,
212 OPC_BLTU = 0x6063,
213 OPC_BNE = 0x1063,
214 OPC_DIV = 0x2004033,
215 OPC_DIVU = 0x2005033,
216 OPC_JAL = 0x6f,
217 OPC_JALR = 0x67,
218 OPC_LB = 0x3,
219 OPC_LBU = 0x4003,
220 OPC_LD = 0x3003,
221 OPC_LH = 0x1003,
222 OPC_LHU = 0x5003,
223 OPC_LUI = 0x37,
224 OPC_LW = 0x2003,
225 OPC_LWU = 0x6003,
226 OPC_MUL = 0x2000033,
227 OPC_MULH = 0x2001033,
228 OPC_MULHSU = 0x2002033,
229 OPC_MULHU = 0x2003033,
230 OPC_OR = 0x6033,
231 OPC_ORI = 0x6013,
232 OPC_REM = 0x2006033,
233 OPC_REMU = 0x2007033,
234 OPC_SB = 0x23,
235 OPC_SD = 0x3023,
236 OPC_SH = 0x1023,
237 OPC_SLL = 0x1033,
238 OPC_SLLI = 0x1013,
239 OPC_SLT = 0x2033,
240 OPC_SLTI = 0x2013,
241 OPC_SLTIU = 0x3013,
242 OPC_SLTU = 0x3033,
243 OPC_SRA = 0x40005033,
244 OPC_SRAI = 0x40005013,
245 OPC_SRL = 0x5033,
246 OPC_SRLI = 0x5013,
247 OPC_SUB = 0x40000033,
248 OPC_SW = 0x2023,
249 OPC_XOR = 0x4033,
250 OPC_XORI = 0x4013,
251
252#if TCG_TARGET_REG_BITS == 64
253 OPC_ADDIW = 0x1b,
254 OPC_ADDW = 0x3b,
255 OPC_DIVUW = 0x200503b,
256 OPC_DIVW = 0x200403b,
257 OPC_MULW = 0x200003b,
258 OPC_REMUW = 0x200703b,
259 OPC_REMW = 0x200603b,
260 OPC_SLLIW = 0x101b,
261 OPC_SLLW = 0x103b,
262 OPC_SRAIW = 0x4000501b,
263 OPC_SRAW = 0x4000503b,
264 OPC_SRLIW = 0x501b,
265 OPC_SRLW = 0x503b,
266 OPC_SUBW = 0x4000003b,
267#else
268 /* Simplify code throughout by defining aliases for RV32. */
269 OPC_ADDIW = OPC_ADDI,
270 OPC_ADDW = OPC_ADD,
271 OPC_DIVUW = OPC_DIVU,
272 OPC_DIVW = OPC_DIV,
273 OPC_MULW = OPC_MUL,
274 OPC_REMUW = OPC_REMU,
275 OPC_REMW = OPC_REM,
276 OPC_SLLIW = OPC_SLLI,
277 OPC_SLLW = OPC_SLL,
278 OPC_SRAIW = OPC_SRAI,
279 OPC_SRAW = OPC_SRA,
280 OPC_SRLIW = OPC_SRLI,
281 OPC_SRLW = OPC_SRL,
282 OPC_SUBW = OPC_SUB,
283#endif
284
285 OPC_FENCE = 0x0000000f,
286} RISCVInsn;
54a9ce0f
AF		 287
288/*
289 * RISC-V immediate and instruction encoders (excludes 16-bit RVC)
290 */
291
292/* Type-R */
293
294static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2)
295{
296 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
297}
298
299/* Type-I */
300
301static int32_t encode_imm12(uint32_t imm)
302{
303 return (imm & 0xfff) << 20;
304}
305
306static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm)
307{
308 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm);
309}
310
311/* Type-S */
312
313static int32_t encode_simm12(uint32_t imm)
314{
315 int32_t ret = 0;
316
317 ret |= (imm & 0xFE0) << 20;
318 ret |= (imm & 0x1F) << 7;
319
320 return ret;
321}
322
323static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
324{
325 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm);
326}
327
328/* Type-SB */
329
330static int32_t encode_sbimm12(uint32_t imm)
331{
332 int32_t ret = 0;
333
334 ret |= (imm & 0x1000) << 19;
335 ret |= (imm & 0x7e0) << 20;
336 ret |= (imm & 0x1e) << 7;
337 ret |= (imm & 0x800) >> 4;
338
339 return ret;
340}
341
342static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
343{
344 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm);
345}
346
347/* Type-U */
348
349static int32_t encode_uimm20(uint32_t imm)
350{
351 return imm & 0xfffff000;
352}
353
354static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm)
355{
356 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm);
357}
358
359/* Type-UJ */
360
361static int32_t encode_ujimm20(uint32_t imm)
362{
363 int32_t ret = 0;
364
365 ret |= (imm & 0x0007fe) << (21 - 1);
366 ret |= (imm & 0x000800) << (20 - 11);
367 ret |= (imm & 0x0ff000) << (12 - 12);
368 ret |= (imm & 0x100000) << (31 - 20);
369
370 return ret;
371}
372
373static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm)
374{
375 return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm);
376}
bedf14e3
AF		 377
378/*
379 * RISC-V instruction emitters
380 */
381
382static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc,
383 TCGReg rd, TCGReg rs1, TCGReg rs2)
384{
385 tcg_out32(s, encode_r(opc, rd, rs1, rs2));
386}
387
388static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc,
389 TCGReg rd, TCGReg rs1, TCGArg imm)
390{
391 tcg_out32(s, encode_i(opc, rd, rs1, imm));
392}
393
394static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc,
395 TCGReg rs1, TCGReg rs2, uint32_t imm)
396{
397 tcg_out32(s, encode_s(opc, rs1, rs2, imm));
398}
399
400static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc,
401 TCGReg rs1, TCGReg rs2, uint32_t imm)
402{
403 tcg_out32(s, encode_sb(opc, rs1, rs2, imm));
404}
405
406static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc,
407 TCGReg rd, uint32_t imm)
408{
409 tcg_out32(s, encode_u(opc, rd, imm));
410}
411
412static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc,
413 TCGReg rd, uint32_t imm)
414{
415 tcg_out32(s, encode_uj(opc, rd, imm));
416}
417
418static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
419{
420 int i;
421 for (i = 0; i < count; ++i) {
422 p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
423 }
424}
dfa8e74f
AF		 425
426/*
427 * Relocations
428 */
429
430static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
431{
432 intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
433
434 if (offset == sextreg(offset, 1, 12) << 1) {
435 code_ptr[0] |= encode_sbimm12(offset);
436 return true;
437 }
438
439 return false;
440}
441
442static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
443{
444 intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
445
446 if (offset == sextreg(offset, 1, 20) << 1) {
447 code_ptr[0] |= encode_ujimm20(offset);
448 return true;
449 }
450
451 return false;
452}
453
454static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
455{
456 intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
457 int32_t lo = sextreg(offset, 0, 12);
458 int32_t hi = offset - lo;
459
460 if (offset == hi + lo) {
461 code_ptr[0] |= encode_uimm20(hi);
462 code_ptr[1] |= encode_imm12(lo);
463 return true;
464 }
465
466 return false;
467}
468
469static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
470 intptr_t value, intptr_t addend)
471{
472 uint32_t insn = *code_ptr;
473 intptr_t diff;
474 bool short_jmp;
475
476 tcg_debug_assert(addend == 0);
477
478 switch (type) {
479 case R_RISCV_BRANCH:
480 diff = value - (uintptr_t)code_ptr;
481 short_jmp = diff == sextreg(diff, 0, 12);
482 if (short_jmp) {
483 return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value);
484 } else {
485 /* Invert the condition */
486 insn = insn ^ (1 << 12);
487 /* Clear the offset */
488 insn &= 0x01fff07f;
489 /* Set the offset to the PC + 8 */
490 insn |= encode_sbimm12(8);
491
492 /* Move forward */
493 code_ptr[0] = insn;
494
495 /* Overwrite the NOP with jal x0,value */
496 diff = value - (uintptr_t)(code_ptr + 1);
497 insn = encode_uj(OPC_JAL, TCG_REG_ZERO, diff);
498 code_ptr[1] = insn;
499
500 return true;
501 }
502 break;
503 case R_RISCV_JAL:
504 return reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
505 break;
506 case R_RISCV_CALL:
507 return reloc_call(code_ptr, (tcg_insn_unit *)value);
508 break;
509 default:
510 tcg_abort();
511 }
512}
6cd2eda3
AF		 513
514/*
515 * TCG intrinsics
516 */
517
518static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
519{
520 if (ret == arg) {
521 return;
522 }
523 switch (type) {
524 case TCG_TYPE_I32:
525 case TCG_TYPE_I64:
526 tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
527 break;
528 default:
529 g_assert_not_reached();
530 }
531}
532
533static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
534 tcg_target_long val)
535{
536 tcg_target_long lo, hi, tmp;
537 int shift, ret;
538
539 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
540 val = (int32_t)val;
541 }
542
543 lo = sextreg(val, 0, 12);
544 if (val == lo) {
545 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo);
546 return;
547 }
548
549 hi = val - lo;
550 if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) {
551 tcg_out_opc_upper(s, OPC_LUI, rd, hi);
552 if (lo != 0) {
553 tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo);
554 }
555 return;
556 }
557
558 /* We can only be here if TCG_TARGET_REG_BITS != 32 */
559 tmp = tcg_pcrel_diff(s, (void *)val);
560 if (tmp == (int32_t)tmp) {
561 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
562 tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0);
563 ret = reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val);
564 tcg_debug_assert(ret == true);
565 return;
566 }
567
568 /* Look for a single 20-bit section. */
569 shift = ctz64(val);
570 tmp = val >> shift;
571 if (tmp == sextreg(tmp, 0, 20)) {
572 tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12);
573 if (shift > 12) {
574 tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12);
575 } else {
576 tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift);
577 }
578 return;
579 }
580
581 /* Look for a few high zero bits, with lots of bits set in the middle. */
582 shift = clz64(val);
583 tmp = val << shift;
584 if (tmp == sextreg(tmp, 12, 20) << 12) {
585 tcg_out_opc_upper(s, OPC_LUI, rd, tmp);
586 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
587 return;
588 } else if (tmp == sextreg(tmp, 0, 12)) {
589 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp);
590 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift);
591 return;
592 }
593
594 /* Drop into the constant pool. */
595 new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0);
596 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
597 tcg_out_opc_imm(s, OPC_LD, rd, rd, 0);
598}
27fd6414
AF		 599
600static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
601{
602 tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff);
603}
604
605static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
606{
607 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
608 tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16);
609}
610
611static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
612{
613 tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
614 tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
615}
616
617static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
618{
619 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24);
620 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24);
621}
622
623static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
624{
625 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16);
626 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16);
627}
628
629static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
630{
631 tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
632}
61535d49
AF		 633
634static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
635 TCGReg addr, intptr_t offset)
636{
637 intptr_t imm12 = sextreg(offset, 0, 12);
638
639 if (offset != imm12) {
640 intptr_t diff = offset - (uintptr_t)s->code_ptr;
641
642 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
643 imm12 = sextreg(diff, 0, 12);
644 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12);
645 } else {
646 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
647 if (addr != TCG_REG_ZERO) {
648 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr);
649 }
650 }
651 addr = TCG_REG_TMP2;
652 }
653
654 switch (opc) {
655 case OPC_SB:
656 case OPC_SH:
657 case OPC_SW:
658 case OPC_SD:
659 tcg_out_opc_store(s, opc, addr, data, imm12);
660 break;
661 case OPC_LB:
662 case OPC_LBU:
663 case OPC_LH:
664 case OPC_LHU:
665 case OPC_LW:
666 case OPC_LWU:
667 case OPC_LD:
668 tcg_out_opc_imm(s, opc, data, addr, imm12);
669 break;
670 default:
671 g_assert_not_reached();
672 }
673}
674
675static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
676 TCGReg arg1, intptr_t arg2)
677{
678 bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
679 tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2);
680}
681
682static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
683 TCGReg arg1, intptr_t arg2)
684{
685 bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
686 tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2);
687}
688
689static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
690 TCGReg base, intptr_t ofs)
691{
692 if (val == 0) {
693 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
694 return true;
695 }
696 return false;
697}
28ca738e
AF		 698
699static void tcg_out_addsub2(TCGContext *s,
700 TCGReg rl, TCGReg rh,
701 TCGReg al, TCGReg ah,
702 TCGArg bl, TCGArg bh,
703 bool cbl, bool cbh, bool is_sub, bool is32bit)
704{
705 const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD;
706 const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI;
707 const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB;
708 TCGReg th = TCG_REG_TMP1;
709
710 /* If we have a negative constant such that negating it would
711 make the high part zero, we can (usually) eliminate one insn. */
712 if (cbl && cbh && bh == -1 && bl != 0) {
713 bl = -bl;
714 bh = 0;
715 is_sub = !is_sub;
716 }
717
718 /* By operating on the high part first, we get to use the final
719 carry operation to move back from the temporary. */
720 if (!cbh) {
721 tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh);
722 } else if (bh != 0 || ah == rl) {
723 tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh));
724 } else {
725 th = ah;
726 }
727
728 /* Note that tcg optimization should eliminate the bl == 0 case. */
729 if (is_sub) {
730 if (cbl) {
731 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl);
732 tcg_out_opc_imm(s, opc_addi, rl, al, -bl);
733 } else {
734 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl);
735 tcg_out_opc_reg(s, opc_sub, rl, al, bl);
736 }
737 tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0);
738 } else {
739 if (cbl) {
740 tcg_out_opc_imm(s, opc_addi, rl, al, bl);
741 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl);
742 } else if (rl == al && rl == bl) {
743 tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
744 tcg_out_opc_reg(s, opc_addi, rl, al, bl);
745 } else {
746 tcg_out_opc_reg(s, opc_add, rl, al, bl);
747 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
748 rl, (rl == bl ? al : bl));
749 }
750 tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0);
751 }
752}
15840069
AF		 753
754static const struct {
755 RISCVInsn op;
756 bool swap;
757} tcg_brcond_to_riscv[] = {
758 [TCG_COND_EQ] = { OPC_BEQ, false },
759 [TCG_COND_NE] = { OPC_BNE, false },
760 [TCG_COND_LT] = { OPC_BLT, false },
761 [TCG_COND_GE] = { OPC_BGE, false },
762 [TCG_COND_LE] = { OPC_BGE, true },
763 [TCG_COND_GT] = { OPC_BLT, true },
764 [TCG_COND_LTU] = { OPC_BLTU, false },
765 [TCG_COND_GEU] = { OPC_BGEU, false },
766 [TCG_COND_LEU] = { OPC_BGEU, true },
767 [TCG_COND_GTU] = { OPC_BLTU, true }
768};
769
770static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
771 TCGReg arg2, TCGLabel *l)
772{
773 RISCVInsn op = tcg_brcond_to_riscv[cond].op;
774
775 tcg_debug_assert(op != 0);
776
777 if (tcg_brcond_to_riscv[cond].swap) {
778 TCGReg t = arg1;
779 arg1 = arg2;
780 arg2 = t;
781 }
782
783 if (l->has_value) {
784 intptr_t diff = tcg_pcrel_diff(s, l->u.value_ptr);
785 if (diff == sextreg(diff, 0, 12)) {
786 tcg_out_opc_branch(s, op, arg1, arg2, diff);
787 } else {
788 /* Invert the conditional branch. */
789 tcg_out_opc_branch(s, op ^ (1 << 12), arg1, arg2, 8);
790 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, diff - 4);
791 }
792 } else {
793 tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0);
794 tcg_out_opc_branch(s, op, arg1, arg2, 0);
795 /* NOP to allow patching later */
796 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
797 }
798}
799
800static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
801 TCGReg arg1, TCGReg arg2)
802{
803 switch (cond) {
804 case TCG_COND_EQ:
805 tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
806 tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1);
807 break;
808 case TCG_COND_NE:
809 tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
810 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret);
811 break;
812 case TCG_COND_LT:
813 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
814 break;
815 case TCG_COND_GE:
816 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
817 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
818 break;
819 case TCG_COND_LE:
820 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
821 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
822 break;
823 case TCG_COND_GT:
824 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
825 break;
826 case TCG_COND_LTU:
827 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
828 break;
829 case TCG_COND_GEU:
830 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
831 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
832 break;
833 case TCG_COND_LEU:
834 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
835 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
836 break;
837 case TCG_COND_GTU:
838 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
839 break;
840 default:
841 g_assert_not_reached();
842 break;
843 }
844}
845
846static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
847 TCGReg bl, TCGReg bh, TCGLabel *l)
848{
849 /* todo */
850 g_assert_not_reached();
851}
852
853static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
854 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
855{
856 /* todo */
857 g_assert_not_reached();
858}
859
860static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target)
861{
862 ptrdiff_t offset = tcg_pcrel_diff(s, target);
863 tcg_debug_assert(offset == sextreg(offset, 1, 20) << 1);
864 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset);
865}
866
867static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
868{
869 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
870 ptrdiff_t offset = tcg_pcrel_diff(s, arg);
871 int ret;
872
873 if (offset == sextreg(offset, 1, 20) << 1) {
874 /* short jump: -2097150 to 2097152 */
875 tcg_out_opc_jump(s, OPC_JAL, link, offset);
876 } else if (TCG_TARGET_REG_BITS == 32 ||
877 offset == sextreg(offset, 1, 31) << 1) {
878 /* long jump: -2147483646 to 2147483648 */
879 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
880 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
881 ret = reloc_call(s->code_ptr - 2, arg);\
882 tcg_debug_assert(ret == true);
883 } else if (TCG_TARGET_REG_BITS == 64) {
884 /* far jump: 64-bit */
885 tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12);
886 tcg_target_long base = (tcg_target_long)arg - imm;
887 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base);
888 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
889 } else {
890 g_assert_not_reached();
891 }
892}
893
894static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
895{
896 tcg_out_call_int(s, arg, false);
897}
efbea94c
AF		 898
899static void tcg_out_mb(TCGContext *s, TCGArg a0)
900{
901 tcg_insn_unit insn = OPC_FENCE;
902
903 if (a0 & TCG_MO_LD_LD) {
904 insn |= 0x02200000;
905 }
906 if (a0 & TCG_MO_ST_LD) {
907 insn |= 0x01200000;
908 }
909 if (a0 & TCG_MO_LD_ST) {
910 insn |= 0x02100000;
911 }
912 if (a0 & TCG_MO_ST_ST) {
913 insn |= 0x02200000;
914 }
915 tcg_out32(s, insn);
916}
917
918/*
919 * Load/store and TLB
920 */
921
922#if defined(CONFIG_SOFTMMU)
923#include "tcg-ldst.inc.c"
924
925/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
926 * TCGMemOpIdx oi, uintptr_t ra)
927 */
928static void * const qemu_ld_helpers[16] = {
929 [MO_UB] = helper_ret_ldub_mmu,
930 [MO_SB] = helper_ret_ldsb_mmu,
931 [MO_LEUW] = helper_le_lduw_mmu,
932 [MO_LESW] = helper_le_ldsw_mmu,
933 [MO_LEUL] = helper_le_ldul_mmu,
934#if TCG_TARGET_REG_BITS == 64
935 [MO_LESL] = helper_le_ldsl_mmu,
936#endif
937 [MO_LEQ] = helper_le_ldq_mmu,
938 [MO_BEUW] = helper_be_lduw_mmu,
939 [MO_BESW] = helper_be_ldsw_mmu,
940 [MO_BEUL] = helper_be_ldul_mmu,
941#if TCG_TARGET_REG_BITS == 64
942 [MO_BESL] = helper_be_ldsl_mmu,
943#endif
944 [MO_BEQ] = helper_be_ldq_mmu,
945};
946
947/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
948 * uintxx_t val, TCGMemOpIdx oi,
949 * uintptr_t ra)
950 */
951static void * const qemu_st_helpers[16] = {
952 [MO_UB] = helper_ret_stb_mmu,
953 [MO_LEUW] = helper_le_stw_mmu,
954 [MO_LEUL] = helper_le_stl_mmu,
955 [MO_LEQ] = helper_le_stq_mmu,
956 [MO_BEUW] = helper_be_stw_mmu,
957 [MO_BEUL] = helper_be_stl_mmu,
958 [MO_BEQ] = helper_be_stq_mmu,
959};
960
961static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
962 TCGReg addrh, TCGMemOpIdx oi,
963 tcg_insn_unit **label_ptr, bool is_load)
964{
965 TCGMemOp opc = get_memop(oi);
966 unsigned s_bits = opc & MO_SIZE;
967 unsigned a_bits = get_alignment_bits(opc);
968 target_ulong mask;
969 int mem_index = get_mmuidx(oi);
970 int cmp_off
971 = (is_load
972 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
973 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
974 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
975 RISCVInsn load_cmp_op = (TARGET_LONG_BITS == 64 ? OPC_LD :
976 TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW);
977 RISCVInsn load_add_op = TCG_TARGET_REG_BITS == 64 ? OPC_LD : OPC_LW;
978 TCGReg base = TCG_AREG0;
979
980 /* We don't support oversize guests */
981 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
982 g_assert_not_reached();
983 }
984
985 /* We don't support unaligned accesses. */
986 if (a_bits < s_bits) {
987 a_bits = s_bits;
988 }
989 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
990
991
992 /* Compensate for very large offsets. */
993 if (add_off >= 0x1000) {
994 int adj;
995 base = TCG_REG_TMP2;
996 if (cmp_off <= 2 * 0xfff) {
997 adj = 0xfff;
998 tcg_out_opc_imm(s, OPC_ADDI, base, TCG_AREG0, adj);
999 } else {
1000 adj = cmp_off - sextreg(cmp_off, 0, 12);
1001 tcg_debug_assert(add_off - adj >= -0x1000
1002 && add_off - adj < 0x1000);
1003
1004 tcg_out_opc_upper(s, OPC_LUI, base, adj);
1005 tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_AREG0);
1006 }
1007 add_off -= adj;
1008 cmp_off -= adj;
1009 }
1010
1011 /* Extract the page index. */
1012 if (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS < 12) {
1013 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP0, addrl,
1014 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
1015 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP0, TCG_REG_TMP0,
1016 MAKE_64BIT_MASK(CPU_TLB_ENTRY_BITS, CPU_TLB_BITS));
1017 } else if (TARGET_PAGE_BITS >= 12) {
1018 tcg_out_opc_upper(s, OPC_LUI, TCG_REG_TMP0,
1019 MAKE_64BIT_MASK(TARGET_PAGE_BITS, CPU_TLB_BITS));
1020 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP0, TCG_REG_TMP0, addrl);
1021 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP0, TCG_REG_TMP0,
1022 CPU_TLB_BITS - CPU_TLB_ENTRY_BITS);
1023 } else {
1024 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP0, addrl, TARGET_PAGE_BITS);
1025 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP0, TCG_REG_TMP0,
1026 MAKE_64BIT_MASK(0, CPU_TLB_BITS));
1027 tcg_out_opc_imm(s, OPC_SLLI, TCG_REG_TMP0, TCG_REG_TMP0,
1028 CPU_TLB_ENTRY_BITS);
1029 }
1030
1031 /* Add that to the base address to index the tlb. */
1032 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, base, TCG_REG_TMP0);
1033 base = TCG_REG_TMP2;
1034
1035 /* Load the tlb comparator and the addend. */
1036 tcg_out_ldst(s, load_cmp_op, TCG_REG_TMP0, base, cmp_off);
1037 tcg_out_ldst(s, load_add_op, TCG_REG_TMP2, base, add_off);
1038
1039 /* Clear the non-page, non-alignment bits from the address. */
1040 if (mask == sextreg(mask, 0, 12)) {
1041 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, mask);
1042 } else {
1043 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, mask);
1044 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl);
1045 }
1046
1047 /* Compare masked address with the TLB entry. */
1048 label_ptr[0] = s->code_ptr;
1049 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
1050 /* NOP to allow patching later */
1051 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0);
1052 /* TODO: Move this out of line
1053 * see:
1054 * https://lists.nongnu.org/archive/html/qemu-devel/2018-11/msg02234.html
1055 */
1056
1057 /* TLB Hit - translate address using addend. */
1058 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1059 tcg_out_ext32u(s, TCG_REG_TMP0, addrl);
1060 addrl = TCG_REG_TMP0;
1061 }
1062 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
1063}
1064
1065static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
1066 TCGType ext,
1067 TCGReg datalo, TCGReg datahi,
1068 TCGReg addrlo, TCGReg addrhi,
1069 void *raddr, tcg_insn_unit **label_ptr)
1070{
1071 TCGLabelQemuLdst *label = new_ldst_label(s);
1072
1073 label->is_ld = is_ld;
1074 label->oi = oi;
1075 label->type = ext;
1076 label->datalo_reg = datalo;
1077 label->datahi_reg = datahi;
1078 label->addrlo_reg = addrlo;
1079 label->addrhi_reg = addrhi;
1080 label->raddr = raddr;
1081 label->label_ptr[0] = label_ptr[0];
1082}
1083
1084static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1085{
1086 TCGMemOpIdx oi = l->oi;
1087 TCGMemOp opc = get_memop(oi);
1088 TCGReg a0 = tcg_target_call_iarg_regs[0];
1089 TCGReg a1 = tcg_target_call_iarg_regs[1];
1090 TCGReg a2 = tcg_target_call_iarg_regs[2];
1091 TCGReg a3 = tcg_target_call_iarg_regs[3];
1092
1093 /* We don't support oversize guests */
1094 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1095 g_assert_not_reached();
1096 }
1097
1098 /* resolve label address */
1099 patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0);
1100
1101 /* call load helper */
1102 tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
1103 tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);
1104 tcg_out_movi(s, TCG_TYPE_PTR, a2, oi);
1105 tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr);
1106
1107 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
1108 tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0);
1109
1110 tcg_out_goto(s, l->raddr);
1111}
1112
1113static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1114{
1115 TCGMemOpIdx oi = l->oi;
1116 TCGMemOp opc = get_memop(oi);
1117 TCGMemOp s_bits = opc & MO_SIZE;
1118 TCGReg a0 = tcg_target_call_iarg_regs[0];
1119 TCGReg a1 = tcg_target_call_iarg_regs[1];
1120 TCGReg a2 = tcg_target_call_iarg_regs[2];
1121 TCGReg a3 = tcg_target_call_iarg_regs[3];
1122 TCGReg a4 = tcg_target_call_iarg_regs[4];
1123
1124 /* We don't support oversize guests */
1125 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1126 g_assert_not_reached();
1127 }
1128
1129 /* resolve label address */
1130 patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0);
1131
1132 /* call store helper */
1133 tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
1134 tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg);
1135 tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg);
1136 switch (s_bits) {
1137 case MO_8:
1138 tcg_out_ext8u(s, a2, a2);
1139 break;
1140 case MO_16:
1141 tcg_out_ext16u(s, a2, a2);
1142 break;
1143 default:
1144 break;
1145 }
1146 tcg_out_movi(s, TCG_TYPE_PTR, a3, oi);
1147 tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr);
1148
1149 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
1150
1151 tcg_out_goto(s, l->raddr);
1152}
1153#endif /* CONFIG_SOFTMMU */
03a7d021
AF		 1154
1155static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1156 TCGReg base, TCGMemOp opc, bool is_64)
1157{
1158 const TCGMemOp bswap = opc & MO_BSWAP;
1159
1160 /* We don't yet handle byteswapping, assert */
1161 g_assert(!bswap);
1162
1163 switch (opc & (MO_SSIZE)) {
1164 case MO_UB:
1165 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1166 break;
1167 case MO_SB:
1168 tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1169 break;
1170 case MO_UW:
1171 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1172 break;
1173 case MO_SW:
1174 tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1175 break;
1176 case MO_UL:
1177 if (TCG_TARGET_REG_BITS == 64 && is_64) {
1178 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1179 break;
1180 }
1181 /* FALLTHRU */
1182 case MO_SL:
1183 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1184 break;
1185 case MO_Q:
1186 /* Prefer to load from offset 0 first, but allow for overlap. */
1187 if (TCG_TARGET_REG_BITS == 64) {
1188 tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1189 } else if (lo != base) {
1190 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1191 tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
1192 } else {
1193 tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
1194 tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1195 }
1196 break;
1197 default:
1198 g_assert_not_reached();
1199 }
1200}
1201
1202static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1203{
1204 TCGReg addr_regl, addr_regh __attribute__((unused));
1205 TCGReg data_regl, data_regh;
1206 TCGMemOpIdx oi;
1207 TCGMemOp opc;
1208#if defined(CONFIG_SOFTMMU)
1209 tcg_insn_unit *label_ptr[1];
1210#endif
1211 TCGReg base = TCG_REG_TMP0;
1212
1213 data_regl = *args++;
1214 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1215 addr_regl = *args++;
1216 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1217 oi = *args++;
1218 opc = get_memop(oi);
1219
1220#if defined(CONFIG_SOFTMMU)
1221 tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
1222 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1223 add_qemu_ldst_label(s, 1, oi,
1224 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1225 data_regl, data_regh, addr_regl, addr_regh,
1226 s->code_ptr, label_ptr);
1227#else
1228 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1229 tcg_out_ext32u(s, base, addr_regl);
1230 addr_regl = base;
1231 }
1232
1233 if (guest_base == 0) {
1234 tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
1235 } else {
1236 tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
1237 }
1238 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
1239#endif
1240}
1241
1242static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1243 TCGReg base, TCGMemOp opc)
1244{
1245 const TCGMemOp bswap = opc & MO_BSWAP;
1246
1247 /* We don't yet handle byteswapping, assert */
1248 g_assert(!bswap);
1249
1250 switch (opc & (MO_SSIZE)) {
1251 case MO_8:
1252 tcg_out_opc_store(s, OPC_SB, base, lo, 0);
1253 break;
1254 case MO_16:
1255 tcg_out_opc_store(s, OPC_SH, base, lo, 0);
1256 break;
1257 case MO_32:
1258 tcg_out_opc_store(s, OPC_SW, base, lo, 0);
1259 break;
1260 case MO_64:
1261 if (TCG_TARGET_REG_BITS == 64) {
1262 tcg_out_opc_store(s, OPC_SD, base, lo, 0);
1263 } else {
1264 tcg_out_opc_store(s, OPC_SW, base, lo, 0);
1265 tcg_out_opc_store(s, OPC_SW, base, hi, 4);
1266 }
1267 break;
1268 default:
1269 g_assert_not_reached();
1270 }
1271}
1272
1273static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1274{
1275 TCGReg addr_regl, addr_regh __attribute__((unused));
1276 TCGReg data_regl, data_regh;
1277 TCGMemOpIdx oi;
1278 TCGMemOp opc;
1279#if defined(CONFIG_SOFTMMU)
1280 tcg_insn_unit *label_ptr[1];
1281#endif
1282 TCGReg base = TCG_REG_TMP0;
1283
1284 data_regl = *args++;
1285 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1286 addr_regl = *args++;
1287 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1288 oi = *args++;
1289 opc = get_memop(oi);
1290
1291#if defined(CONFIG_SOFTMMU)
1292 tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
1293 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1294 add_qemu_ldst_label(s, 0, oi,
1295 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
1296 data_regl, data_regh, addr_regl, addr_regh,
1297 s->code_ptr, label_ptr);
1298#else
1299 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1300 tcg_out_ext32u(s, base, addr_regl);
1301 addr_regl = base;
1302 }
1303
1304 if (guest_base == 0) {
1305 tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO);
1306 } else {
1307 tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
1308 }
1309 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
1310#endif
1311}
bdf50381
AF		 1312
1313static tcg_insn_unit *tb_ret_addr;
1314
1315static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1316 const TCGArg *args, const int *const_args)
1317{
1318 TCGArg a0 = args[0];
1319 TCGArg a1 = args[1];
1320 TCGArg a2 = args[2];
1321 int c2 = const_args[2];
1322
1323 switch (opc) {
1324 case INDEX_op_exit_tb:
1325 /* Reuse the zeroing that exists for goto_ptr. */
1326 if (a0 == 0) {
1327 tcg_out_call_int(s, s->code_gen_epilogue, true);
1328 } else {
1329 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0);
1330 tcg_out_call_int(s, tb_ret_addr, true);
1331 }
1332 break;
1333
1334 case INDEX_op_goto_tb:
1335 assert(s->tb_jmp_insn_offset == 0);
1336 /* indirect jump method */
1337 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO,
1338 (uintptr_t)(s->tb_jmp_target_addr + a0));
1339 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1340 set_jmp_reset_offset(s, a0);
1341 break;
1342
1343 case INDEX_op_goto_ptr:
1344 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
1345 break;
1346
1347 case INDEX_op_br:
1348 tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0);
1349 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
1350 break;
1351
1352 case INDEX_op_ld8u_i32:
1353 case INDEX_op_ld8u_i64:
1354 tcg_out_ldst(s, OPC_LBU, a0, a1, a2);
1355 break;
1356 case INDEX_op_ld8s_i32:
1357 case INDEX_op_ld8s_i64:
1358 tcg_out_ldst(s, OPC_LB, a0, a1, a2);
1359 break;
1360 case INDEX_op_ld16u_i32:
1361 case INDEX_op_ld16u_i64:
1362 tcg_out_ldst(s, OPC_LHU, a0, a1, a2);
1363 break;
1364 case INDEX_op_ld16s_i32:
1365 case INDEX_op_ld16s_i64:
1366 tcg_out_ldst(s, OPC_LH, a0, a1, a2);
1367 break;
1368 case INDEX_op_ld32u_i64:
1369 tcg_out_ldst(s, OPC_LWU, a0, a1, a2);
1370 break;
1371 case INDEX_op_ld_i32:
1372 case INDEX_op_ld32s_i64:
1373 tcg_out_ldst(s, OPC_LW, a0, a1, a2);
1374 break;
1375 case INDEX_op_ld_i64:
1376 tcg_out_ldst(s, OPC_LD, a0, a1, a2);
1377 break;
1378
1379 case INDEX_op_st8_i32:
1380 case INDEX_op_st8_i64:
1381 tcg_out_ldst(s, OPC_SB, a0, a1, a2);
1382 break;
1383 case INDEX_op_st16_i32:
1384 case INDEX_op_st16_i64:
1385 tcg_out_ldst(s, OPC_SH, a0, a1, a2);
1386 break;
1387 case INDEX_op_st_i32:
1388 case INDEX_op_st32_i64:
1389 tcg_out_ldst(s, OPC_SW, a0, a1, a2);
1390 break;
1391 case INDEX_op_st_i64:
1392 tcg_out_ldst(s, OPC_SD, a0, a1, a2);
1393 break;
1394
1395 case INDEX_op_add_i32:
1396 if (c2) {
1397 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2);
1398 } else {
1399 tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2);
1400 }
1401 break;
1402 case INDEX_op_add_i64:
1403 if (c2) {
1404 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2);
1405 } else {
1406 tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2);
1407 }
1408 break;
1409
1410 case INDEX_op_sub_i32:
1411 if (c2) {
1412 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2);
1413 } else {
1414 tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2);
1415 }
1416 break;
1417 case INDEX_op_sub_i64:
1418 if (c2) {
1419 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2);
1420 } else {
1421 tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2);
1422 }
1423 break;
1424
1425 case INDEX_op_and_i32:
1426 case INDEX_op_and_i64:
1427 if (c2) {
1428 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2);
1429 } else {
1430 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2);
1431 }
1432 break;
1433
1434 case INDEX_op_or_i32:
1435 case INDEX_op_or_i64:
1436 if (c2) {
1437 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2);
1438 } else {
1439 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2);
1440 }
1441 break;
1442
1443 case INDEX_op_xor_i32:
1444 case INDEX_op_xor_i64:
1445 if (c2) {
1446 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
1447 } else {
1448 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
1449 }
1450 break;
1451
1452 case INDEX_op_not_i32:
1453 case INDEX_op_not_i64:
1454 tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1);
1455 break;
1456
1457 case INDEX_op_neg_i32:
1458 tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1);
1459 break;
1460 case INDEX_op_neg_i64:
1461 tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1);
1462 break;
1463
1464 case INDEX_op_mul_i32:
1465 tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2);
1466 break;
1467 case INDEX_op_mul_i64:
1468 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1469 break;
1470
1471 case INDEX_op_div_i32:
1472 tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2);
1473 break;
1474 case INDEX_op_div_i64:
1475 tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2);
1476 break;
1477
1478 case INDEX_op_divu_i32:
1479 tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2);
1480 break;
1481 case INDEX_op_divu_i64:
1482 tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2);
1483 break;
1484
1485 case INDEX_op_rem_i32:
1486 tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2);
1487 break;
1488 case INDEX_op_rem_i64:
1489 tcg_out_opc_reg(s, OPC_REM, a0, a1, a2);
1490 break;
1491
1492 case INDEX_op_remu_i32:
1493 tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2);
1494 break;
1495 case INDEX_op_remu_i64:
1496 tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2);
1497 break;
1498
1499 case INDEX_op_shl_i32:
1500 if (c2) {
1501 tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2);
1502 } else {
1503 tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
1504 }
1505 break;
1506 case INDEX_op_shl_i64:
1507 if (c2) {
1508 tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2);
1509 } else {
1510 tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
1511 }
1512 break;
1513
1514 case INDEX_op_shr_i32:
1515 if (c2) {
1516 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
1517 } else {
1518 tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
1519 }
1520 break;
1521 case INDEX_op_shr_i64:
1522 if (c2) {
1523 tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2);
1524 } else {
1525 tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
1526 }
1527 break;
1528
1529 case INDEX_op_sar_i32:
1530 if (c2) {
1531 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2);
1532 } else {
1533 tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
1534 }
1535 break;
1536 case INDEX_op_sar_i64:
1537 if (c2) {
1538 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2);
1539 } else {
1540 tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
1541 }
1542 break;
1543
1544 case INDEX_op_add2_i32:
1545 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1546 const_args[4], const_args[5], false, true);
1547 break;
1548 case INDEX_op_add2_i64:
1549 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1550 const_args[4], const_args[5], false, false);
1551 break;
1552 case INDEX_op_sub2_i32:
1553 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1554 const_args[4], const_args[5], true, true);
1555 break;
1556 case INDEX_op_sub2_i64:
1557 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
1558 const_args[4], const_args[5], true, false);
1559 break;
1560
1561 case INDEX_op_brcond_i32:
1562 case INDEX_op_brcond_i64:
1563 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
1564 break;
1565 case INDEX_op_brcond2_i32:
1566 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
1567 break;
1568
1569 case INDEX_op_setcond_i32:
1570 case INDEX_op_setcond_i64:
1571 tcg_out_setcond(s, args[3], a0, a1, a2);
1572 break;
1573 case INDEX_op_setcond2_i32:
1574 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
1575 break;
1576
1577 case INDEX_op_qemu_ld_i32:
1578 tcg_out_qemu_ld(s, args, false);
1579 break;
1580 case INDEX_op_qemu_ld_i64:
1581 tcg_out_qemu_ld(s, args, true);
1582 break;
1583 case INDEX_op_qemu_st_i32:
1584 tcg_out_qemu_st(s, args, false);
1585 break;
1586 case INDEX_op_qemu_st_i64:
1587 tcg_out_qemu_st(s, args, true);
1588 break;
1589
1590 case INDEX_op_ext8u_i32:
1591 case INDEX_op_ext8u_i64:
1592 tcg_out_ext8u(s, a0, a1);
1593 break;
1594
1595 case INDEX_op_ext16u_i32:
1596 case INDEX_op_ext16u_i64:
1597 tcg_out_ext16u(s, a0, a1);
1598 break;
1599
1600 case INDEX_op_ext32u_i64:
1601 case INDEX_op_extu_i32_i64:
1602 tcg_out_ext32u(s, a0, a1);
1603 break;
1604
1605 case INDEX_op_ext8s_i32:
1606 case INDEX_op_ext8s_i64:
1607 tcg_out_ext8s(s, a0, a1);
1608 break;
1609
1610 case INDEX_op_ext16s_i32:
1611 case INDEX_op_ext16s_i64:
1612 tcg_out_ext16s(s, a0, a1);
1613 break;
1614
1615 case INDEX_op_ext32s_i64:
1616 case INDEX_op_extrl_i64_i32:
1617 case INDEX_op_ext_i32_i64:
1618 tcg_out_ext32s(s, a0, a1);
1619 break;
1620
1621 case INDEX_op_extrh_i64_i32:
1622 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32);
1623 break;
1624
1625 case INDEX_op_mulsh_i32:
1626 case INDEX_op_mulsh_i64:
1627 tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
1628 break;
1629
1630 case INDEX_op_muluh_i32:
1631 case INDEX_op_muluh_i64:
1632 tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2);
1633 break;
1634
1635 case INDEX_op_mb:
1636 tcg_out_mb(s, a0);
1637 break;
1638
1639 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
1640 case INDEX_op_mov_i64:
1641 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
1642 case INDEX_op_movi_i64:
1643 case INDEX_op_call: /* Always emitted via tcg_out_call. */
1644 default:
1645 g_assert_not_reached();
1646 }
1647}
1648
1649static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
1650{
1651 static const TCGTargetOpDef r
1652 = { .args_ct_str = { "r" } };
1653 static const TCGTargetOpDef r_r
1654 = { .args_ct_str = { "r", "r" } };
1655 static const TCGTargetOpDef rZ_r
1656 = { .args_ct_str = { "rZ", "r" } };
1657 static const TCGTargetOpDef rZ_rZ
1658 = { .args_ct_str = { "rZ", "rZ" } };
1659 static const TCGTargetOpDef rZ_rZ_rZ_rZ
1660 = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
1661 static const TCGTargetOpDef r_r_ri
1662 = { .args_ct_str = { "r", "r", "ri" } };
1663 static const TCGTargetOpDef r_r_rI
1664 = { .args_ct_str = { "r", "r", "rI" } };
1665 static const TCGTargetOpDef r_rZ_rN
1666 = { .args_ct_str = { "r", "rZ", "rN" } };
1667 static const TCGTargetOpDef r_rZ_rZ
1668 = { .args_ct_str = { "r", "rZ", "rZ" } };
1669 static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
1670 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
1671 static const TCGTargetOpDef r_L
1672 = { .args_ct_str = { "r", "L" } };
1673 static const TCGTargetOpDef r_r_L
1674 = { .args_ct_str = { "r", "r", "L" } };
1675 static const TCGTargetOpDef r_L_L
1676 = { .args_ct_str = { "r", "L", "L" } };
1677 static const TCGTargetOpDef r_r_L_L
1678 = { .args_ct_str = { "r", "r", "L", "L" } };
1679 static const TCGTargetOpDef LZ_L
1680 = { .args_ct_str = { "LZ", "L" } };
1681 static const TCGTargetOpDef LZ_L_L
1682 = { .args_ct_str = { "LZ", "L", "L" } };
1683 static const TCGTargetOpDef LZ_LZ_L
1684 = { .args_ct_str = { "LZ", "LZ", "L" } };
1685 static const TCGTargetOpDef LZ_LZ_L_L
1686 = { .args_ct_str = { "LZ", "LZ", "L", "L" } };
1687 static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
1688 = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
1689
1690 switch (op) {
1691 case INDEX_op_goto_ptr:
1692 return &r;
1693
1694 case INDEX_op_ld8u_i32:
1695 case INDEX_op_ld8s_i32:
1696 case INDEX_op_ld16u_i32:
1697 case INDEX_op_ld16s_i32:
1698 case INDEX_op_ld_i32:
1699 case INDEX_op_not_i32:
1700 case INDEX_op_neg_i32:
1701 case INDEX_op_ld8u_i64:
1702 case INDEX_op_ld8s_i64:
1703 case INDEX_op_ld16u_i64:
1704 case INDEX_op_ld16s_i64:
1705 case INDEX_op_ld32s_i64:
1706 case INDEX_op_ld32u_i64:
1707 case INDEX_op_ld_i64:
1708 case INDEX_op_not_i64:
1709 case INDEX_op_neg_i64:
1710 case INDEX_op_ext8u_i32:
1711 case INDEX_op_ext8u_i64:
1712 case INDEX_op_ext16u_i32:
1713 case INDEX_op_ext16u_i64:
1714 case INDEX_op_ext32u_i64:
1715 case INDEX_op_extu_i32_i64:
1716 case INDEX_op_ext8s_i32:
1717 case INDEX_op_ext8s_i64:
1718 case INDEX_op_ext16s_i32:
1719 case INDEX_op_ext16s_i64:
1720 case INDEX_op_ext32s_i64:
1721 case INDEX_op_extrl_i64_i32:
1722 case INDEX_op_extrh_i64_i32:
1723 case INDEX_op_ext_i32_i64:
1724 return &r_r;
1725
1726 case INDEX_op_st8_i32:
1727 case INDEX_op_st16_i32:
1728 case INDEX_op_st_i32:
1729 case INDEX_op_st8_i64:
1730 case INDEX_op_st16_i64:
1731 case INDEX_op_st32_i64:
1732 case INDEX_op_st_i64:
1733 return &rZ_r;
1734
1735 case INDEX_op_add_i32:
1736 case INDEX_op_and_i32:
1737 case INDEX_op_or_i32:
1738 case INDEX_op_xor_i32:
1739 case INDEX_op_add_i64:
1740 case INDEX_op_and_i64:
1741 case INDEX_op_or_i64:
1742 case INDEX_op_xor_i64:
1743 return &r_r_rI;
1744
1745 case INDEX_op_sub_i32:
1746 case INDEX_op_sub_i64:
1747 return &r_rZ_rN;
1748
1749 case INDEX_op_mul_i32:
1750 case INDEX_op_mulsh_i32:
1751 case INDEX_op_muluh_i32:
1752 case INDEX_op_div_i32:
1753 case INDEX_op_divu_i32:
1754 case INDEX_op_rem_i32:
1755 case INDEX_op_remu_i32:
1756 case INDEX_op_setcond_i32:
1757 case INDEX_op_mul_i64:
1758 case INDEX_op_mulsh_i64:
1759 case INDEX_op_muluh_i64:
1760 case INDEX_op_div_i64:
1761 case INDEX_op_divu_i64:
1762 case INDEX_op_rem_i64:
1763 case INDEX_op_remu_i64:
1764 case INDEX_op_setcond_i64:
1765 return &r_rZ_rZ;
1766
1767 case INDEX_op_shl_i32:
1768 case INDEX_op_shr_i32:
1769 case INDEX_op_sar_i32:
1770 case INDEX_op_shl_i64:
1771 case INDEX_op_shr_i64:
1772 case INDEX_op_sar_i64:
1773 return &r_r_ri;
1774
1775 case INDEX_op_brcond_i32:
1776 case INDEX_op_brcond_i64:
1777 return &rZ_rZ;
1778
1779 case INDEX_op_add2_i32:
1780 case INDEX_op_add2_i64:
1781 case INDEX_op_sub2_i32:
1782 case INDEX_op_sub2_i64:
1783 return &r_r_rZ_rZ_rM_rM;
1784
1785 case INDEX_op_brcond2_i32:
1786 return &rZ_rZ_rZ_rZ;
1787
1788 case INDEX_op_setcond2_i32:
1789 return &r_rZ_rZ_rZ_rZ;
1790
1791 case INDEX_op_qemu_ld_i32:
1792 return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
1793 case INDEX_op_qemu_st_i32:
1794 return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L;
1795 case INDEX_op_qemu_ld_i64:
1796 return TCG_TARGET_REG_BITS == 64 ? &r_L
1797 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
1798 : &r_r_L_L;
1799 case INDEX_op_qemu_st_i64:
1800 return TCG_TARGET_REG_BITS == 64 ? &LZ_L
1801 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L
1802 : &LZ_LZ_L_L;
1803
1804 default:
1805 return NULL;
1806 }
1807}
92c041c5
AF		 1808
1809static const int tcg_target_callee_save_regs[] = {
1810 TCG_REG_S0, /* used for the global env (TCG_AREG0) */
1811 TCG_REG_S1,
1812 TCG_REG_S2,
1813 TCG_REG_S3,
1814 TCG_REG_S4,
1815 TCG_REG_S5,
1816 TCG_REG_S6,
1817 TCG_REG_S7,
1818 TCG_REG_S8,
1819 TCG_REG_S9,
1820 TCG_REG_S10,
1821 TCG_REG_S11,
1822 TCG_REG_RA, /* should be last for ABI compliance */
1823};
1824
1825/* Stack frame parameters. */
1826#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
1827#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
1828#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1829#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
1830 + TCG_TARGET_STACK_ALIGN - 1) \
1831 & -TCG_TARGET_STACK_ALIGN)
1832#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
1833
1834/* We're expecting to be able to use an immediate for frame allocation. */
1835QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
1836
1837/* Generate global QEMU prologue and epilogue code */
1838static void tcg_target_qemu_prologue(TCGContext *s)
1839{
1840 int i;
1841
1842 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
1843
1844 /* TB prologue */
1845 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
1846 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1847 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1848 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
1849 }
1850
1851#if !defined(CONFIG_SOFTMMU)
1852 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
1853 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1854#endif
1855
1856 /* Call generated code */
1857 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1858 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
1859
1860 /* Return path for goto_ptr. Set return value to 0 */
1861 s->code_gen_epilogue = s->code_ptr;
1862 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
1863
1864 /* TB epilogue */
1865 tb_ret_addr = s->code_ptr;
1866 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
1867 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1868 TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
1869 }
1870
1871 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
1872 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
1873}
1874
1875typedef struct {
1876 DebugFrameHeader h;
1877 uint8_t fde_def_cfa[4];
1878 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
1879} DebugFrame;
1880
1881#define ELF_HOST_MACHINE EM_RISCV
1882
1883static const DebugFrame debug_frame = {
1884 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
1885 .h.cie.id = -1,
1886 .h.cie.version = 1,
1887 .h.cie.code_align = 1,
1888 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
1889 .h.cie.return_column = TCG_REG_RA,
1890
1891 /* Total FDE size does not include the "len" member. */
1892 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
1893
1894 .fde_def_cfa = {
1895 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
1896 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
1897 (FRAME_SIZE >> 7)
1898 },
1899 .fde_reg_ofs = {
1900 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */
1901 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */
1902 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */
1903 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */
1904 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */
1905 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */
1906 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */
1907 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */
1908 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */
1909 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */
1910 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */
1911 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
1912 }
1913};
1914
1915void tcg_register_jit(void *buf, size_t buf_size)
1916{
1917 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
1918}
Empty description
This page took 0.215445 seconds and 4 git commands to generate.