[qemu.git] / hw / parallel.c

/*
 * QEMU Parallel PORT emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2007 Marko Kohtala
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "qemu-char.h"
#include "isa.h"
#include "pc.h"

//#define DEBUG_PARALLEL

#ifdef DEBUG_PARALLEL
#define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
#else
#define pdebug(fmt, arg...) ((void)0)
#endif

#define PARA_REG_DATA 0
#define PARA_REG_STS 1
#define PARA_REG_CTR 2
#define PARA_REG_EPP_ADDR 3
#define PARA_REG_EPP_DATA 4

/*
 * These are the definitions for the Printer Status Register
 */
#define PARA_STS_BUSY	0x80	/* Busy complement */
#define PARA_STS_ACK	0x40	/* Acknowledge */
#define PARA_STS_PAPER	0x20	/* Out of paper */
#define PARA_STS_ONLINE	0x10	/* Online */
#define PARA_STS_ERROR	0x08	/* Error complement */
#define PARA_STS_TMOUT	0x01	/* EPP timeout */

/*
 * These are the definitions for the Printer Control Register
 */
#define PARA_CTR_DIR	0x20	/* Direction (1=read, 0=write) */
#define PARA_CTR_INTEN	0x10	/* IRQ Enable */
#define PARA_CTR_SELECT	0x08	/* Select In complement */
#define PARA_CTR_INIT	0x04	/* Initialize Printer complement */
#define PARA_CTR_AUTOLF	0x02	/* Auto linefeed complement */
#define PARA_CTR_STROBE	0x01	/* Strobe complement */

#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)

struct ParallelState {
    uint8_t dataw;
    uint8_t datar;
    uint8_t status;
    uint8_t control;
    qemu_irq irq;
    int irq_pending;
    CharDriverState *chr;
    int hw_driver;
    int epp_timeout;
    uint32_t last_read_offset; /* For debugging */
    /* Memory-mapped interface */
    target_phys_addr_t base;
    int it_shift;
};

static void parallel_update_irq(ParallelState *s)
{
    if (s->irq_pending)
        qemu_irq_raise(s->irq);
    else
        qemu_irq_lower(s->irq);
}

static void
parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;

    pdebug("write addr=0x%02x val=0x%02x\n", addr, val);

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        s->dataw = val;
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if ((val & PARA_CTR_INIT) == 0 ) {
            s->status = PARA_STS_BUSY;
            s->status |= PARA_STS_ACK;
            s->status |= PARA_STS_ONLINE;
            s->status |= PARA_STS_ERROR;
        }
        else if (val & PARA_CTR_SELECT) {
            if (val & PARA_CTR_STROBE) {
                s->status &= ~PARA_STS_BUSY;
                if ((s->control & PARA_CTR_STROBE) == 0)
                    qemu_chr_write(s->chr, &s->dataw, 1);
            } else {
                if (s->control & PARA_CTR_INTEN) {
                    s->irq_pending = 1;
                }
            }
        }
        parallel_update_irq(s);
        s->control = val;
        break;
    }
}

static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint8_t parm = val;

    /* Sometimes programs do several writes for timing purposes on old
       HW. Take care not to waste time on writes that do nothing. */

    s->last_read_offset = ~0U;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->dataw == val)
            return;
        pdebug("wd%02x\n", val);
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
        s->dataw = val;
        break;
    case PARA_REG_STS:
        pdebug("ws%02x\n", val);
        if (val & PARA_STS_TMOUT)
            s->epp_timeout = 0;
        break;
    case PARA_REG_CTR:
        val |= 0xc0;
        if (s->control == val)
            return;
        pdebug("wc%02x\n", val);
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
        s->control = val;
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP address cycle, so do nothing */
            pdebug("wa%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("wa%02x t\n", val);
            }
            else
                pdebug("wa%02x\n", val);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("we%02x s\n", val);
        else {
            struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("we%02x t\n", val);
            }
            else
                pdebug("we%02x\n", val);
        }
        break;
    }
}

static void
parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint16_t eppdata = cpu_to_le16(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%04x s\n", val);
        return;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%04x t\n", val);
    }
    else
        pdebug("we%04x\n", val);
}

static void
parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
{
    ParallelState *s = opaque;
    uint32_t eppdata = cpu_to_le32(val);
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("we%08x s\n", val);
        return;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
    if (err) {
        s->epp_timeout = 1;
        pdebug("we%08x t\n", val);
    }
    else
        pdebug("we%08x\n", val);
}

static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret = 0xff;

    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        if (s->control & PARA_CTR_DIR)
            ret = s->datar;
        else
            ret = s->dataw;
        break;
    case PARA_REG_STS:
        ret = s->status;
        s->irq_pending = 0;
        if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
            /* XXX Fixme: wait 5 microseconds */
            if (s->status & PARA_STS_ACK)
                s->status &= ~PARA_STS_ACK;
            else {
                /* XXX Fixme: wait 5 microseconds */
                s->status |= PARA_STS_ACK;
                s->status |= PARA_STS_BUSY;
            }
        }
        parallel_update_irq(s);
        break;
    case PARA_REG_CTR:
        ret = s->control;
        break;
    }
    pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
    return ret;
}

static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint8_t ret = 0xff;
    addr &= 7;
    switch(addr) {
    case PARA_REG_DATA:
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
        if (s->last_read_offset != addr || s->datar != ret)
            pdebug("rd%02x\n", ret);
        s->datar = ret;
        break;
    case PARA_REG_STS:
        qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
        ret &= ~PARA_STS_TMOUT;
        if (s->epp_timeout)
            ret |= PARA_STS_TMOUT;
        if (s->last_read_offset != addr || s->status != ret)
            pdebug("rs%02x\n", ret);
        s->status = ret;
        break;
    case PARA_REG_CTR:
        /* s->control has some bits fixed to 1. It is zero only when
           it has not been yet written to.  */
        if (s->control == 0) {
            qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
            s->control = ret;
        }
        else {
            ret = s->control;
            if (s->last_read_offset != addr)
                pdebug("rc%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_ADDR:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP addr cycle, so do nothing */
            pdebug("ra%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("ra%02x t\n", ret);
            }
            else
                pdebug("ra%02x\n", ret);
        }
        break;
    case PARA_REG_EPP_DATA:
        if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
            /* Controls not correct for EPP data cycle, so do nothing */
            pdebug("re%02x s\n", ret);
        else {
            struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
            if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
                s->epp_timeout = 1;
                pdebug("re%02x t\n", ret);
            }
            else
                pdebug("re%02x\n", ret);
        }
        break;
    }
    s->last_read_offset = addr;
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint16_t eppdata = ~0;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%04x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le16_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%04x t\n", ret);
    }
    else
        pdebug("re%04x\n", ret);
    return ret;
}

static uint32_t
parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
{
    ParallelState *s = opaque;
    uint32_t ret;
    uint32_t eppdata = ~0U;
    int err;
    struct ParallelIOArg ioarg = {
        .buffer = &eppdata, .count = sizeof(eppdata)
    };
    if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
        /* Controls not correct for EPP data cycle, so do nothing */
        pdebug("re%08x s\n", eppdata);
        return eppdata;
    }
    err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
    ret = le32_to_cpu(eppdata);

    if (err) {
        s->epp_timeout = 1;
        pdebug("re%08x t\n", ret);
    }
    else
        pdebug("re%08x\n", ret);
    return ret;
}

static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
{
    addr &= 7;
    pdebug("wecp%d=%02x\n", addr, val);
}

static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
{
    uint8_t ret = 0xff;
    addr &= 7;
    pdebug("recp%d:%02x\n", addr, ret);
    return ret;
}

static void parallel_reset(ParallelState *s, qemu_irq irq, CharDriverState *chr)
{
    s->datar = ~0;
    s->dataw = ~0;
    s->status = PARA_STS_BUSY;
    s->status |= PARA_STS_ACK;
    s->status |= PARA_STS_ONLINE;
    s->status |= PARA_STS_ERROR;
    s->status |= PARA_STS_TMOUT;
    s->control = PARA_CTR_SELECT;
    s->control |= PARA_CTR_INIT;
    s->control |= 0xc0;
    s->irq = irq;
    s->irq_pending = 0;
    s->chr = chr;
    s->hw_driver = 0;
    s->epp_timeout = 0;
    s->last_read_offset = ~0U;
}

/* If fd is zero, it means that the parallel device uses the console */
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
{
    ParallelState *s;
    uint8_t dummy;

    s = qemu_mallocz(sizeof(ParallelState));
    if (!s)
        return NULL;
    parallel_reset(s, irq, chr);

    if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
        s->hw_driver = 1;
        s->status = dummy;
    }

    if (s->hw_driver) {
        register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
        register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
        register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
        register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
        register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
        register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
        register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
        register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
    }
    else {
        register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
        register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
    }
    return s;
}

/* Memory mapped interface */
static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
}

static void parallel_mm_writeb (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
}

static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
}

static void parallel_mm_writew (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
}

static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
{
    ParallelState *s = opaque;

    return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
}

static void parallel_mm_writel (void *opaque,
                                target_phys_addr_t addr, uint32_t value)
{
    ParallelState *s = opaque;

    parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);
}

static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
    &parallel_mm_readb,
    &parallel_mm_readw,
    &parallel_mm_readl,
};

static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
    &parallel_mm_writeb,
    &parallel_mm_writew,
    &parallel_mm_writel,
};

/* If fd is zero, it means that the parallel device uses the console */
ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr)
{
    ParallelState *s;
    int io_sw;

    s = qemu_mallocz(sizeof(ParallelState));
    if (!s)
        return NULL;
    parallel_reset(s, irq, chr);
    s->base = base;
    s->it_shift = it_shift;

    io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
    cpu_register_physical_memory(base, 8 << it_shift, io_sw);
    return s;
}
Commit	Line	Data
6508fe59 FB	1	/*
6508fe59 FB	2	* QEMU Parallel PORT emulation
5fafdf24	3	*
e57a8c0e	4	* Copyright (c) 2003-2005 Fabrice Bellard
5867c88a	5	* Copyright (c) 2007 Marko Kohtala
5fafdf24	6	*
6508fe59 FB	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
87ecb68b PB	25	#include "hw.h"
	26	#include "qemu-char.h"
	27	#include "isa.h"
	28	#include "pc.h"
6508fe59 FB	29
	30	//#define DEBUG_PARALLEL
	31
5867c88a TS	32	#ifdef DEBUG_PARALLEL
	33	#define pdebug(fmt, arg...) printf("pp: " fmt, ##arg)
	34	#else
	35	#define pdebug(fmt, arg...) ((void)0)
	36	#endif
	37
	38	#define PARA_REG_DATA 0
	39	#define PARA_REG_STS 1
	40	#define PARA_REG_CTR 2
	41	#define PARA_REG_EPP_ADDR 3
	42	#define PARA_REG_EPP_DATA 4
	43
6508fe59 FB	44	/*
	45	* These are the definitions for the Printer Status Register
	46	*/
	47	#define PARA_STS_BUSY 0x80 /* Busy complement */
	48	#define PARA_STS_ACK 0x40 /* Acknowledge */
	49	#define PARA_STS_PAPER 0x20 /* Out of paper */
	50	#define PARA_STS_ONLINE 0x10 /* Online */
	51	#define PARA_STS_ERROR 0x08 /* Error complement */
5867c88a	52	#define PARA_STS_TMOUT 0x01 /* EPP timeout */
6508fe59 FB	53
	54	/*
	55	* These are the definitions for the Printer Control Register
	56	*/
5867c88a	57	#define PARA_CTR_DIR 0x20 /* Direction (1=read, 0=write) */
6508fe59 FB	58	#define PARA_CTR_INTEN 0x10 /* IRQ Enable */
	59	#define PARA_CTR_SELECT 0x08 /* Select In complement */
	60	#define PARA_CTR_INIT 0x04 /* Initialize Printer complement */
	61	#define PARA_CTR_AUTOLF 0x02 /* Auto linefeed complement */
	62	#define PARA_CTR_STROBE 0x01 /* Strobe complement */
	63
5867c88a TS	64	#define PARA_CTR_SIGNAL (PARA_CTR_SELECT\|PARA_CTR_INIT\|PARA_CTR_AUTOLF\|PARA_CTR_STROBE)
5867c88a TS	65
6508fe59	66	struct ParallelState {
5867c88a TS	67	uint8_t dataw;
	68	uint8_t datar;
	69	uint8_t status;
6508fe59	70	uint8_t control;
d537cf6c	71	qemu_irq irq;
6508fe59 FB	72	int irq_pending;
6508fe59 FB	73	CharDriverState *chr;
e57a8c0e	74	int hw_driver;
5867c88a TS	75	int epp_timeout;
5867c88a TS	76	uint32_t last_read_offset; /* For debugging */
d60532ca TS	77	/* Memory-mapped interface */
	78	target_phys_addr_t base;
	79	int it_shift;
6508fe59 FB	80	};
	81
	82	static void parallel_update_irq(ParallelState *s)
	83	{
	84	if (s->irq_pending)
d537cf6c	85	qemu_irq_raise(s->irq);
6508fe59	86	else
d537cf6c	87	qemu_irq_lower(s->irq);
6508fe59 FB	88	}
6508fe59 FB	89
5867c88a TS	90	static void
5867c88a TS	91	parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
6508fe59 FB	92	{
6508fe59 FB	93	ParallelState *s = opaque;
3b46e624	94
5867c88a TS	95	pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
	96
	97	addr &= 7;
	98	switch(addr) {
	99	case PARA_REG_DATA:
0fa7f157 TS	100	s->dataw = val;
0fa7f157 TS	101	parallel_update_irq(s);
5867c88a TS	102	break;
5867c88a TS	103	case PARA_REG_CTR:
52ccc5e0	104	val \|= 0xc0;
0fa7f157 TS	105	if ((val & PARA_CTR_INIT) == 0 ) {
	106	s->status = PARA_STS_BUSY;
	107	s->status \|= PARA_STS_ACK;
	108	s->status \|= PARA_STS_ONLINE;
	109	s->status \|= PARA_STS_ERROR;
	110	}
	111	else if (val & PARA_CTR_SELECT) {
	112	if (val & PARA_CTR_STROBE) {
	113	s->status &= ~PARA_STS_BUSY;
	114	if ((s->control & PARA_CTR_STROBE) == 0)
	115	qemu_chr_write(s->chr, &s->dataw, 1);
	116	} else {
	117	if (s->control & PARA_CTR_INTEN) {
	118	s->irq_pending = 1;
	119	}
	120	}
	121	}
	122	parallel_update_irq(s);
	123	s->control = val;
5867c88a TS	124	break;
	125	}
	126	}
	127
	128	static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
	129	{
	130	ParallelState *s = opaque;
	131	uint8_t parm = val;
	132
	133	/* Sometimes programs do several writes for timing purposes on old
	134	HW. Take care not to waste time on writes that do nothing. */
	135
	136	s->last_read_offset = ~0U;
	137
6508fe59	138	addr &= 7;
6508fe59	139	switch(addr) {
5867c88a TS	140	case PARA_REG_DATA:
5867c88a TS	141	if (s->dataw == val)
0fa7f157 TS	142	return;
	143	pdebug("wd%02x\n", val);
	144	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
	145	s->dataw = val;
6508fe59	146	break;
5867c88a	147	case PARA_REG_STS:
0fa7f157 TS	148	pdebug("ws%02x\n", val);
	149	if (val & PARA_STS_TMOUT)
	150	s->epp_timeout = 0;
	151	break;
5867c88a TS	152	case PARA_REG_CTR:
	153	val \|= 0xc0;
	154	if (s->control == val)
0fa7f157 TS	155	return;
	156	pdebug("wc%02x\n", val);
	157	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
	158	s->control = val;
6508fe59	159	break;
5867c88a	160	case PARA_REG_EPP_ADDR:
0fa7f157 TS	161	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	162	/* Controls not correct for EPP address cycle, so do nothing */
	163	pdebug("wa%02x s\n", val);
	164	else {
	165	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	166	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
	167	s->epp_timeout = 1;
	168	pdebug("wa%02x t\n", val);
	169	}
	170	else
	171	pdebug("wa%02x\n", val);
	172	}
	173	break;
5867c88a	174	case PARA_REG_EPP_DATA:
0fa7f157 TS	175	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
	176	/* Controls not correct for EPP data cycle, so do nothing */
	177	pdebug("we%02x s\n", val);
	178	else {
	179	struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
	180	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
	181	s->epp_timeout = 1;
	182	pdebug("we%02x t\n", val);
	183	}
	184	else
	185	pdebug("we%02x\n", val);
	186	}
	187	break;
5867c88a TS	188	}
	189	}
	190
	191	static void
	192	parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
	193	{
	194	ParallelState *s = opaque;
	195	uint16_t eppdata = cpu_to_le16(val);
	196	int err;
	197	struct ParallelIOArg ioarg = {
0fa7f157	198	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	199	};
5867c88a TS	200	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	201	/* Controls not correct for EPP data cycle, so do nothing */
	202	pdebug("we%04x s\n", val);
	203	return;
5867c88a TS	204	}
	205	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
	206	if (err) {
0fa7f157 TS	207	s->epp_timeout = 1;
0fa7f157 TS	208	pdebug("we%04x t\n", val);
5867c88a TS	209	}
5867c88a TS	210	else
0fa7f157	211	pdebug("we%04x\n", val);
5867c88a TS	212	}
	213
	214	static void
	215	parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
	216	{
	217	ParallelState *s = opaque;
	218	uint32_t eppdata = cpu_to_le32(val);
	219	int err;
	220	struct ParallelIOArg ioarg = {
0fa7f157	221	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	222	};
5867c88a TS	223	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
0fa7f157 TS	224	/* Controls not correct for EPP data cycle, so do nothing */
	225	pdebug("we%08x s\n", val);
	226	return;
5867c88a TS	227	}
	228	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
	229	if (err) {
0fa7f157 TS	230	s->epp_timeout = 1;
0fa7f157 TS	231	pdebug("we%08x t\n", val);
6508fe59	232	}
5867c88a	233	else
0fa7f157	234	pdebug("we%08x\n", val);
6508fe59 FB	235	}
6508fe59 FB	236
5867c88a	237	static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
6508fe59 FB	238	{
	239	ParallelState *s = opaque;
	240	uint32_t ret = 0xff;
	241
	242	addr &= 7;
	243	switch(addr) {
5867c88a	244	case PARA_REG_DATA:
0fa7f157 TS	245	if (s->control & PARA_CTR_DIR)
	246	ret = s->datar;
	247	else
	248	ret = s->dataw;
6508fe59	249	break;
5867c88a	250	case PARA_REG_STS:
0fa7f157 TS	251	ret = s->status;
	252	s->irq_pending = 0;
	253	if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
	254	/* XXX Fixme: wait 5 microseconds */
	255	if (s->status & PARA_STS_ACK)
	256	s->status &= ~PARA_STS_ACK;
	257	else {
	258	/* XXX Fixme: wait 5 microseconds */
	259	s->status \|= PARA_STS_ACK;
	260	s->status \|= PARA_STS_BUSY;
	261	}
	262	}
	263	parallel_update_irq(s);
6508fe59	264	break;
5867c88a	265	case PARA_REG_CTR:
6508fe59 FB	266	ret = s->control;
	267	break;
	268	}
5867c88a TS	269	pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
	270	return ret;
	271	}
	272
	273	static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
	274	{
	275	ParallelState *s = opaque;
	276	uint8_t ret = 0xff;
	277	addr &= 7;
	278	switch(addr) {
	279	case PARA_REG_DATA:
0fa7f157 TS	280	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
	281	if (s->last_read_offset != addr \|\| s->datar != ret)
	282	pdebug("rd%02x\n", ret);
5867c88a TS	283	s->datar = ret;
	284	break;
	285	case PARA_REG_STS:
0fa7f157 TS	286	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
	287	ret &= ~PARA_STS_TMOUT;
	288	if (s->epp_timeout)
	289	ret \|= PARA_STS_TMOUT;
	290	if (s->last_read_offset != addr \|\| s->status != ret)
	291	pdebug("rs%02x\n", ret);
	292	s->status = ret;
5867c88a TS	293	break;
	294	case PARA_REG_CTR:
	295	/* s->control has some bits fixed to 1. It is zero only when
0fa7f157 TS	296	it has not been yet written to. */
	297	if (s->control == 0) {
	298	qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
	299	if (s->last_read_offset != addr)
	300	pdebug("rc%02x\n", ret);
	301	s->control = ret;
	302	}
	303	else {
	304	ret = s->control;
	305	if (s->last_read_offset != addr)
	306	pdebug("rc%02x\n", ret);
	307	}
5867c88a TS	308	break;
5867c88a TS	309	case PARA_REG_EPP_ADDR:
0fa7f157 TS	310	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	311	/* Controls not correct for EPP addr cycle, so do nothing */
	312	pdebug("ra%02x s\n", ret);
	313	else {
	314	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	315	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
	316	s->epp_timeout = 1;
	317	pdebug("ra%02x t\n", ret);
	318	}
	319	else
	320	pdebug("ra%02x\n", ret);
	321	}
	322	break;
5867c88a	323	case PARA_REG_EPP_DATA:
0fa7f157 TS	324	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT))
	325	/* Controls not correct for EPP data cycle, so do nothing */
	326	pdebug("re%02x s\n", ret);
	327	else {
	328	struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
	329	if (qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
	330	s->epp_timeout = 1;
	331	pdebug("re%02x t\n", ret);
	332	}
	333	else
	334	pdebug("re%02x\n", ret);
	335	}
	336	break;
5867c88a TS	337	}
	338	s->last_read_offset = addr;
	339	return ret;
	340	}
	341
	342	static uint32_t
	343	parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
	344	{
	345	ParallelState *s = opaque;
	346	uint32_t ret;
	347	uint16_t eppdata = ~0;
	348	int err;
	349	struct ParallelIOArg ioarg = {
0fa7f157	350	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	351	};
5867c88a TS	352	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	353	/* Controls not correct for EPP data cycle, so do nothing */
	354	pdebug("re%04x s\n", eppdata);
	355	return eppdata;
5867c88a TS	356	}
	357	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
	358	ret = le16_to_cpu(eppdata);
	359
	360	if (err) {
0fa7f157 TS	361	s->epp_timeout = 1;
0fa7f157 TS	362	pdebug("re%04x t\n", ret);
5867c88a TS	363	}
5867c88a TS	364	else
0fa7f157	365	pdebug("re%04x\n", ret);
5867c88a TS	366	return ret;
	367	}
	368
	369	static uint32_t
	370	parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
	371	{
	372	ParallelState *s = opaque;
	373	uint32_t ret;
	374	uint32_t eppdata = ~0U;
	375	int err;
	376	struct ParallelIOArg ioarg = {
0fa7f157	377	.buffer = &eppdata, .count = sizeof(eppdata)
5867c88a TS	378	};
5867c88a TS	379	if ((s->control & (PARA_CTR_DIR\|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR\|PARA_CTR_INIT)) {
0fa7f157 TS	380	/* Controls not correct for EPP data cycle, so do nothing */
	381	pdebug("re%08x s\n", eppdata);
	382	return eppdata;
5867c88a TS	383	}
	384	err = qemu_chr_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
	385	ret = le32_to_cpu(eppdata);
	386
	387	if (err) {
0fa7f157 TS	388	s->epp_timeout = 1;
0fa7f157 TS	389	pdebug("re%08x t\n", ret);
5867c88a TS	390	}
5867c88a TS	391	else
0fa7f157	392	pdebug("re%08x\n", ret);
5867c88a TS	393	return ret;
	394	}
	395
	396	static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
	397	{
	398	addr &= 7;
	399	pdebug("wecp%d=%02x\n", addr, val);
	400	}
	401
	402	static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
	403	{
	404	uint8_t ret = 0xff;
	405	addr &= 7;
	406	pdebug("recp%d:%02x\n", addr, ret);
6508fe59 FB	407	return ret;
	408	}
	409
d60532ca	410	static void parallel_reset(ParallelState s, qemu_irq irq, CharDriverState chr)
6508fe59	411	{
5867c88a TS	412	s->datar = ~0;
5867c88a TS	413	s->dataw = ~0;
6508fe59 FB	414	s->status = PARA_STS_BUSY;
	415	s->status \|= PARA_STS_ACK;
	416	s->status \|= PARA_STS_ONLINE;
	417	s->status \|= PARA_STS_ERROR;
52ccc5e0	418	s->status \|= PARA_STS_TMOUT;
6508fe59 FB	419	s->control = PARA_CTR_SELECT;
6508fe59 FB	420	s->control \|= PARA_CTR_INIT;
52ccc5e0	421	s->control \|= 0xc0;
5867c88a TS	422	s->irq = irq;
	423	s->irq_pending = 0;
	424	s->chr = chr;
	425	s->hw_driver = 0;
	426	s->epp_timeout = 0;
	427	s->last_read_offset = ~0U;
d60532ca TS	428	}
	429
	430	/* If fd is zero, it means that the parallel device uses the console */
	431	ParallelState parallel_init(int base, qemu_irq irq, CharDriverState chr)
	432	{
	433	ParallelState *s;
	434	uint8_t dummy;
	435
	436	s = qemu_mallocz(sizeof(ParallelState));
	437	if (!s)
	438	return NULL;
	439	parallel_reset(s, irq, chr);
6508fe59	440
5867c88a TS	441	if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
5867c88a TS	442	s->hw_driver = 1;
0fa7f157	443	s->status = dummy;
5867c88a TS	444	}
	445
	446	if (s->hw_driver) {
0fa7f157 TS	447	register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
	448	register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
	449	register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
	450	register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
	451	register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
	452	register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
	453	register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
	454	register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
5867c88a TS	455	}
5867c88a TS	456	else {
0fa7f157 TS	457	register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
0fa7f157 TS	458	register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
5867c88a	459	}
6508fe59 FB	460	return s;
6508fe59 FB	461	}
d60532ca TS	462
d60532ca TS	463	/* Memory mapped interface */
9596ebb7	464	static uint32_t parallel_mm_readb (void *opaque, target_phys_addr_t addr)
d60532ca TS	465	{
	466	ParallelState *s = opaque;
	467
	468	return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFF;
	469	}
	470
9596ebb7 PB	471	static void parallel_mm_writeb (void *opaque,
9596ebb7 PB	472	target_phys_addr_t addr, uint32_t value)
d60532ca TS	473	{
	474	ParallelState *s = opaque;
	475
	476	parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFF);
	477	}
	478
9596ebb7	479	static uint32_t parallel_mm_readw (void *opaque, target_phys_addr_t addr)
d60532ca TS	480	{
	481	ParallelState *s = opaque;
	482
	483	return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
	484	}
	485
9596ebb7 PB	486	static void parallel_mm_writew (void *opaque,
9596ebb7 PB	487	target_phys_addr_t addr, uint32_t value)
d60532ca TS	488	{
	489	ParallelState *s = opaque;
	490
	491	parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
	492	}
	493
9596ebb7	494	static uint32_t parallel_mm_readl (void *opaque, target_phys_addr_t addr)
d60532ca TS	495	{
	496	ParallelState *s = opaque;
	497
	498	return parallel_ioport_read_sw(s, (addr - s->base) >> s->it_shift);
	499	}
	500
9596ebb7 PB	501	static void parallel_mm_writel (void *opaque,
9596ebb7 PB	502	target_phys_addr_t addr, uint32_t value)
d60532ca TS	503	{
	504	ParallelState *s = opaque;
	505
	506	parallel_ioport_write_sw(s, (addr - s->base) >> s->it_shift, value);
	507	}
	508
	509	static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
	510	&parallel_mm_readb,
	511	&parallel_mm_readw,
	512	&parallel_mm_readl,
	513	};
	514
	515	static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
	516	&parallel_mm_writeb,
	517	&parallel_mm_writew,
	518	&parallel_mm_writel,
	519	};
	520
	521	/* If fd is zero, it means that the parallel device uses the console */
	522	ParallelState parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState chr)
	523	{
	524	ParallelState *s;
	525	int io_sw;
	526
	527	s = qemu_mallocz(sizeof(ParallelState));
	528	if (!s)
	529	return NULL;
	530	parallel_reset(s, irq, chr);
	531	s->base = base;
	532	s->it_shift = it_shift;
	533
	534	io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
	535	cpu_register_physical_memory(base, 8 << it_shift, io_sw);
	536	return s;
	537	}