[qemu.git] / hw / i8259.c

/*
 * QEMU 8259 interrupt controller emulation
 * 
 * Copyright (c) 2003-2004 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

/* debug PIC */
//#define DEBUG_PIC

//#define DEBUG_IRQ_LATENCY
//#define DEBUG_IRQ_COUNT

typedef struct PicState {
    uint8_t last_irr; /* edge detection */
    uint8_t irr; /* interrupt request register */
    uint8_t imr; /* interrupt mask register */
    uint8_t isr; /* interrupt service register */
    uint8_t priority_add; /* highest irq priority */
    uint8_t irq_base;
    uint8_t read_reg_select;
    uint8_t poll;
    uint8_t special_mask;
    uint8_t init_state;
    uint8_t auto_eoi;
    uint8_t rotate_on_auto_eoi;
    uint8_t special_fully_nested_mode;
    uint8_t init4; /* true if 4 byte init */
    uint8_t elcr; /* PIIX edge/trigger selection*/
    uint8_t elcr_mask;
} PicState;

/* 0 is master pic, 1 is slave pic */
static PicState pics[2];

#if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
static int irq_level[16];
#endif
#ifdef DEBUG_IRQ_COUNT
static uint64_t irq_count[16];
#endif

/* set irq level. If an edge is detected, then the IRR is set to 1 */
static inline void pic_set_irq1(PicState *s, int irq, int level)
{
    int mask;
    mask = 1 << irq;
    if (s->elcr & mask) {
        /* level triggered */
        if (level) {
            s->irr |= mask;
            s->last_irr |= mask;
        } else {
            s->irr &= ~mask;
            s->last_irr &= ~mask;
        }
    } else {
        /* edge triggered */
        if (level) {
            if ((s->last_irr & mask) == 0)
                s->irr |= mask;
            s->last_irr |= mask;
        } else {
            s->last_irr &= ~mask;
        }
    }
}

/* return the highest priority found in mask (highest = smallest
   number). Return 8 if no irq */
static inline int get_priority(PicState *s, int mask)
{
    int priority;
    if (mask == 0)
        return 8;
    priority = 0;
    while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
        priority++;
    return priority;
}

/* return the pic wanted interrupt. return -1 if none */
static int pic_get_irq(PicState *s)
{
    int mask, cur_priority, priority;

    mask = s->irr & ~s->imr;
    priority = get_priority(s, mask);
    if (priority == 8)
        return -1;
    /* compute current priority. If special fully nested mode on the
       master, the IRQ coming from the slave is not taken into account
       for the priority computation. */
    mask = s->isr;
    if (s->special_fully_nested_mode && s == &pics[0])
        mask &= ~(1 << 2);
    cur_priority = get_priority(s, mask);
    if (priority < cur_priority) {
        /* higher priority found: an irq should be generated */
        return (priority + s->priority_add) & 7;
    } else {
        return -1;
    }
}

/* raise irq to CPU if necessary. must be called every time the active
   irq may change */
static void pic_update_irq(void)
{
    int irq2, irq;

    /* first look at slave pic */
    irq2 = pic_get_irq(&pics[1]);
    if (irq2 >= 0) {
        /* if irq request by slave pic, signal master PIC */
        pic_set_irq1(&pics[0], 2, 1);
        pic_set_irq1(&pics[0], 2, 0);
    }
    /* look at requested irq */
    irq = pic_get_irq(&pics[0]);
    if (irq >= 0) {
#if defined(DEBUG_PIC)
        {
            int i;
            for(i = 0; i < 2; i++) {
                printf("pic%d: imr=%x irr=%x padd=%d\n", 
                       i, pics[i].imr, pics[i].irr, pics[i].priority_add);
                
            }
        }
        printf("pic: cpu_interrupt\n");
#endif
        cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
    }
}

#ifdef DEBUG_IRQ_LATENCY
int64_t irq_time[16];
#endif

void pic_set_irq(int irq, int level)
{
#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
    if (level != irq_level[irq]) {
#if defined(DEBUG_PIC)
        printf("pic_set_irq: irq=%d level=%d\n", irq, level);
#endif
        irq_level[irq] = level;
#ifdef DEBUG_IRQ_COUNT
	if (level == 1)
	    irq_count[irq]++;
#endif
    }
#endif
#ifdef DEBUG_IRQ_LATENCY
    if (level) {
        irq_time[irq] = qemu_get_clock(vm_clock);
    }
#endif
    pic_set_irq1(&pics[irq >> 3], irq & 7, level);
    pic_update_irq();
}

/* acknowledge interrupt 'irq' */
static inline void pic_intack(PicState *s, int irq)
{
    if (s->auto_eoi) {
        if (s->rotate_on_auto_eoi)
            s->priority_add = (irq + 1) & 7;
    } else {
        s->isr |= (1 << irq);
    }
    s->irr &= ~(1 << irq);
}

int cpu_get_pic_interrupt(CPUState *env)
{
    int irq, irq2, intno;

    /* read the irq from the PIC */

    irq = pic_get_irq(&pics[0]);
    if (irq >= 0) {
        pic_intack(&pics[0], irq);
        if (irq == 2) {
            irq2 = pic_get_irq(&pics[1]);
            if (irq2 >= 0) {
                pic_intack(&pics[1], irq2);
            } else {
                /* spurious IRQ on slave controller */
                irq2 = 7;
            }
            intno = pics[1].irq_base + irq2;
            irq = irq2 + 8;
        } else {
            intno = pics[0].irq_base + irq;
        }
    } else {
        /* spurious IRQ on host controller */
        irq = 7;
        intno = pics[0].irq_base + irq;
    }
    pic_update_irq();
        
#ifdef DEBUG_IRQ_LATENCY
    printf("IRQ%d latency=%0.3fus\n", 
           irq, 
           (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
#endif
#if defined(DEBUG_PIC)
    printf("pic_interrupt: irq=%d\n", irq);
#endif
    return intno;
}

static void pic_reset(void *opaque)
{
    PicState *s = opaque;
    int tmp;

    tmp = s->elcr_mask;
    memset(s, 0, sizeof(PicState));
    s->elcr_mask = tmp;
}

static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    PicState *s = opaque;
    int priority, cmd, irq;

#ifdef DEBUG_PIC
    printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
#endif
    addr &= 1;
    if (addr == 0) {
        if (val & 0x10) {
            /* init */
            pic_reset(s);
            /* deassert a pending interrupt */
            cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);

            s->init_state = 1;
            s->init4 = val & 1;
            if (val & 0x02)
                hw_error("single mode not supported");
            if (val & 0x08)
                hw_error("level sensitive irq not supported");
        } else if (val & 0x08) {
            if (val & 0x04)
                s->poll = 1;
            if (val & 0x02)
                s->read_reg_select = val & 1;
            if (val & 0x40)
                s->special_mask = (val >> 5) & 1;
        } else {
            cmd = val >> 5;
            switch(cmd) {
            case 0:
            case 4:
                s->rotate_on_auto_eoi = cmd >> 2;
                break;
            case 1: /* end of interrupt */
            case 5:
                priority = get_priority(s, s->isr);
                if (priority != 8) {
                    irq = (priority + s->priority_add) & 7;
                    s->isr &= ~(1 << irq);
                    if (cmd == 5)
                        s->priority_add = (irq + 1) & 7;
                    pic_update_irq();
                }
                break;
            case 3:
                irq = val & 7;
                s->isr &= ~(1 << irq);
                pic_update_irq();
                break;
            case 6:
                s->priority_add = (val + 1) & 7;
                pic_update_irq();
                break;
            case 7:
                irq = val & 7;
                s->isr &= ~(1 << irq);
                s->priority_add = (irq + 1) & 7;
                pic_update_irq();
                break;
            default:
                /* no operation */
                break;
            }
        }
    } else {
        switch(s->init_state) {
        case 0:
            /* normal mode */
            s->imr = val;
            pic_update_irq();
            break;
        case 1:
            s->irq_base = val & 0xf8;
            s->init_state = 2;
            break;
        case 2:
            if (s->init4) {
                s->init_state = 3;
            } else {
                s->init_state = 0;
            }
            break;
        case 3:
            s->special_fully_nested_mode = (val >> 4) & 1;
            s->auto_eoi = (val >> 1) & 1;
            s->init_state = 0;
            break;
        }
    }
}

static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
{
    int ret;

    ret = pic_get_irq(s);
    if (ret >= 0) {
        if (addr1 >> 7) {
            pics[0].isr &= ~(1 << 2);
            pics[0].irr &= ~(1 << 2);
        }
        s->irr &= ~(1 << ret);
        s->isr &= ~(1 << ret);
        if (addr1 >> 7 || ret != 2)
            pic_update_irq();
    } else {
        ret = 0x07;
        pic_update_irq();
    }

    return ret;
}

static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
{
    PicState *s = opaque;
    unsigned int addr;
    int ret;

    addr = addr1;
    addr &= 1;
    if (s->poll) {
        ret = pic_poll_read(s, addr1);
        s->poll = 0;
    } else {
        if (addr == 0) {
            if (s->read_reg_select)
                ret = s->isr;
            else
                ret = s->irr;
        } else {
            ret = s->imr;
        }
    }
#ifdef DEBUG_PIC
    printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
#endif
    return ret;
}

/* memory mapped interrupt status */
uint32_t pic_intack_read(CPUState *env)
{
    int ret;

    ret = pic_poll_read(&pics[0], 0x00);
    if (ret == 2)
        ret = pic_poll_read(&pics[1], 0x80) + 8;
    /* Prepare for ISR read */
    pics[0].read_reg_select = 1;
    
    return ret;
}

static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    PicState *s = opaque;
    s->elcr = val & s->elcr_mask;
}

static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
{
    PicState *s = opaque;
    return s->elcr;
}

static void pic_save(QEMUFile *f, void *opaque)
{
    PicState *s = opaque;
    
    qemu_put_8s(f, &s->last_irr);
    qemu_put_8s(f, &s->irr);
    qemu_put_8s(f, &s->imr);
    qemu_put_8s(f, &s->isr);
    qemu_put_8s(f, &s->priority_add);
    qemu_put_8s(f, &s->irq_base);
    qemu_put_8s(f, &s->read_reg_select);
    qemu_put_8s(f, &s->poll);
    qemu_put_8s(f, &s->special_mask);
    qemu_put_8s(f, &s->init_state);
    qemu_put_8s(f, &s->auto_eoi);
    qemu_put_8s(f, &s->rotate_on_auto_eoi);
    qemu_put_8s(f, &s->special_fully_nested_mode);
    qemu_put_8s(f, &s->init4);
    qemu_put_8s(f, &s->elcr);
}

static int pic_load(QEMUFile *f, void *opaque, int version_id)
{
    PicState *s = opaque;
    
    if (version_id != 1)
        return -EINVAL;

    qemu_get_8s(f, &s->last_irr);
    qemu_get_8s(f, &s->irr);
    qemu_get_8s(f, &s->imr);
    qemu_get_8s(f, &s->isr);
    qemu_get_8s(f, &s->priority_add);
    qemu_get_8s(f, &s->irq_base);
    qemu_get_8s(f, &s->read_reg_select);
    qemu_get_8s(f, &s->poll);
    qemu_get_8s(f, &s->special_mask);
    qemu_get_8s(f, &s->init_state);
    qemu_get_8s(f, &s->auto_eoi);
    qemu_get_8s(f, &s->rotate_on_auto_eoi);
    qemu_get_8s(f, &s->special_fully_nested_mode);
    qemu_get_8s(f, &s->init4);
    qemu_get_8s(f, &s->elcr);
    return 0;
}

/* XXX: add generic master/slave system */
static void pic_init1(int io_addr, int elcr_addr, PicState *s)
{
    register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
    register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
    if (elcr_addr >= 0) {
        register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
        register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
    }
    register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
    qemu_register_reset(pic_reset, s);
}

void pic_info(void)
{
    int i;
    PicState *s;

    for(i=0;i<2;i++) {
        s = &pics[i];
        term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
                    i, s->irr, s->imr, s->isr, s->priority_add, 
                    s->irq_base, s->read_reg_select, s->elcr, 
                    s->special_fully_nested_mode);
    }
}

void irq_info(void)
{
#ifndef DEBUG_IRQ_COUNT
    term_printf("irq statistic code not compiled.\n");
#else
    int i;
    int64_t count;

    term_printf("IRQ statistics:\n");
    for (i = 0; i < 16; i++) {
        count = irq_count[i];
        if (count > 0)
            term_printf("%2d: %lld\n", i, count);
    }
#endif
}

void pic_init(void)
{
    pic_init1(0x20, 0x4d0, &pics[0]);
    pic_init1(0xa0, 0x4d1, &pics[1]);
    pics[0].elcr_mask = 0xf8;
    pics[1].elcr_mask = 0xde;
}
Commit	Line	Data
80cabfad FB	1	/*
	2	* QEMU 8259 interrupt controller emulation
	3	*
	4	* Copyright (c) 2003-2004 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
80cabfad FB	24	#include "vl.h"
	25
	26	/* debug PIC */
	27	//#define DEBUG_PIC
	28
b41a2cd1	29	//#define DEBUG_IRQ_LATENCY
4a0fb71e	30	//#define DEBUG_IRQ_COUNT
b41a2cd1	31
80cabfad FB	32	typedef struct PicState {
	33	uint8_t last_irr; /* edge detection */
	34	uint8_t irr; /* interrupt request register */
	35	uint8_t imr; /* interrupt mask register */
	36	uint8_t isr; /* interrupt service register */
	37	uint8_t priority_add; /* highest irq priority */
	38	uint8_t irq_base;
	39	uint8_t read_reg_select;
	40	uint8_t poll;
	41	uint8_t special_mask;
	42	uint8_t init_state;
	43	uint8_t auto_eoi;
	44	uint8_t rotate_on_auto_eoi;
	45	uint8_t special_fully_nested_mode;
	46	uint8_t init4; /* true if 4 byte init */
660de336 FB	47	uint8_t elcr; /* PIIX edge/trigger selection*/
660de336 FB	48	uint8_t elcr_mask;
80cabfad FB	49	} PicState;
	50
	51	/* 0 is master pic, 1 is slave pic */
ba91cd80	52	static PicState pics[2];
80cabfad	53
4a0fb71e FB	54	#if defined(DEBUG_PIC) \|\| defined (DEBUG_IRQ_COUNT)
	55	static int irq_level[16];
	56	#endif
	57	#ifdef DEBUG_IRQ_COUNT
	58	static uint64_t irq_count[16];
	59	#endif
	60
80cabfad FB	61	/* set irq level. If an edge is detected, then the IRR is set to 1 */
	62	static inline void pic_set_irq1(PicState *s, int irq, int level)
	63	{
	64	int mask;
	65	mask = 1 << irq;
660de336 FB	66	if (s->elcr & mask) {
	67	/* level triggered */
	68	if (level) {
80cabfad	69	s->irr \|= mask;
660de336 FB	70	s->last_irr \|= mask;
	71	} else {
	72	s->irr &= ~mask;
	73	s->last_irr &= ~mask;
	74	}
80cabfad	75	} else {
660de336 FB	76	/* edge triggered */
	77	if (level) {
	78	if ((s->last_irr & mask) == 0)
	79	s->irr \|= mask;
	80	s->last_irr \|= mask;
	81	} else {
	82	s->last_irr &= ~mask;
	83	}
80cabfad FB	84	}
	85	}
	86
	87	/* return the highest priority found in mask (highest = smallest
	88	number). Return 8 if no irq */
	89	static inline int get_priority(PicState *s, int mask)
	90	{
	91	int priority;
	92	if (mask == 0)
	93	return 8;
	94	priority = 0;
	95	while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
	96	priority++;
	97	return priority;
	98	}
	99
	100	/* return the pic wanted interrupt. return -1 if none */
	101	static int pic_get_irq(PicState *s)
	102	{
	103	int mask, cur_priority, priority;
	104
	105	mask = s->irr & ~s->imr;
	106	priority = get_priority(s, mask);
	107	if (priority == 8)
	108	return -1;
	109	/* compute current priority. If special fully nested mode on the
	110	master, the IRQ coming from the slave is not taken into account
	111	for the priority computation. */
	112	mask = s->isr;
	113	if (s->special_fully_nested_mode && s == &pics[0])
	114	mask &= ~(1 << 2);
	115	cur_priority = get_priority(s, mask);
	116	if (priority < cur_priority) {
	117	/* higher priority found: an irq should be generated */
	118	return (priority + s->priority_add) & 7;
	119	} else {
	120	return -1;
	121	}
	122	}
	123
	124	/* raise irq to CPU if necessary. must be called every time the active
	125	irq may change */
b0a21b53	126	static void pic_update_irq(void)
80cabfad FB	127	{
	128	int irq2, irq;
	129
	130	/* first look at slave pic */
	131	irq2 = pic_get_irq(&pics[1]);
	132	if (irq2 >= 0) {
	133	/* if irq request by slave pic, signal master PIC */
	134	pic_set_irq1(&pics[0], 2, 1);
	135	pic_set_irq1(&pics[0], 2, 0);
	136	}
	137	/* look at requested irq */
	138	irq = pic_get_irq(&pics[0]);
	139	if (irq >= 0) {
80cabfad FB	140	#if defined(DEBUG_PIC)
	141	{
	142	int i;
	143	for(i = 0; i < 2; i++) {
	144	printf("pic%d: imr=%x irr=%x padd=%d\n",
	145	i, pics[i].imr, pics[i].irr, pics[i].priority_add);
	146
	147	}
	148	}
2444ca41	149	printf("pic: cpu_interrupt\n");
80cabfad FB	150	#endif
	151	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
	152	}
	153	}
	154
	155	#ifdef DEBUG_IRQ_LATENCY
	156	int64_t irq_time[16];
80cabfad	157	#endif
80cabfad FB	158
	159	void pic_set_irq(int irq, int level)
	160	{
4a0fb71e	161	#if defined(DEBUG_PIC) \|\| defined(DEBUG_IRQ_COUNT)
80cabfad	162	if (level != irq_level[irq]) {
4a0fb71e	163	#if defined(DEBUG_PIC)
80cabfad	164	printf("pic_set_irq: irq=%d level=%d\n", irq, level);
4a0fb71e	165	#endif
80cabfad	166	irq_level[irq] = level;
4a0fb71e FB	167	#ifdef DEBUG_IRQ_COUNT
	168	if (level == 1)
	169	irq_count[irq]++;
	170	#endif
80cabfad FB	171	}
	172	#endif
	173	#ifdef DEBUG_IRQ_LATENCY
	174	if (level) {
2444ca41	175	irq_time[irq] = qemu_get_clock(vm_clock);
80cabfad FB	176	}
	177	#endif
	178	pic_set_irq1(&pics[irq >> 3], irq & 7, level);
	179	pic_update_irq();
	180	}
	181
	182	/* acknowledge interrupt 'irq' */
	183	static inline void pic_intack(PicState *s, int irq)
	184	{
	185	if (s->auto_eoi) {
	186	if (s->rotate_on_auto_eoi)
	187	s->priority_add = (irq + 1) & 7;
	188	} else {
	189	s->isr \|= (1 << irq);
	190	}
	191	s->irr &= ~(1 << irq);
	192	}
	193
a541f297	194	int cpu_get_pic_interrupt(CPUState *env)
80cabfad FB	195	{
	196	int irq, irq2, intno;
	197
15aeac38 FB	198	/* read the irq from the PIC */
	199
	200	irq = pic_get_irq(&pics[0]);
	201	if (irq >= 0) {
	202	pic_intack(&pics[0], irq);
	203	if (irq == 2) {
	204	irq2 = pic_get_irq(&pics[1]);
	205	if (irq2 >= 0) {
	206	pic_intack(&pics[1], irq2);
	207	} else {
	208	/* spurious IRQ on slave controller */
	209	irq2 = 7;
	210	}
	211	intno = pics[1].irq_base + irq2;
	212	irq = irq2 + 8;
	213	} else {
	214	intno = pics[0].irq_base + irq;
	215	}
	216	} else {
	217	/* spurious IRQ on host controller */
	218	irq = 7;
	219	intno = pics[0].irq_base + irq;
	220	}
	221	pic_update_irq();
	222
80cabfad FB	223	#ifdef DEBUG_IRQ_LATENCY
	224	printf("IRQ%d latency=%0.3fus\n",
	225	irq,
2444ca41	226	(double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
80cabfad FB	227	#endif
	228	#if defined(DEBUG_PIC)
	229	printf("pic_interrupt: irq=%d\n", irq);
	230	#endif
80cabfad FB	231	return intno;
	232	}
	233
d7d02e3c FB	234	static void pic_reset(void *opaque)
	235	{
	236	PicState *s = opaque;
	237	int tmp;
	238
	239	tmp = s->elcr_mask;
	240	memset(s, 0, sizeof(PicState));
	241	s->elcr_mask = tmp;
	242	}
	243
b41a2cd1	244	static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
80cabfad	245	{
b41a2cd1	246	PicState *s = opaque;
d7d02e3c	247	int priority, cmd, irq;
80cabfad FB	248
	249	#ifdef DEBUG_PIC
	250	printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
	251	#endif
80cabfad FB	252	addr &= 1;
	253	if (addr == 0) {
	254	if (val & 0x10) {
	255	/* init */
d7d02e3c	256	pic_reset(s);
b54ad049 FB	257	/* deassert a pending interrupt */
b54ad049 FB	258	cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
660de336	259
80cabfad FB	260	s->init_state = 1;
	261	s->init4 = val & 1;
	262	if (val & 0x02)
	263	hw_error("single mode not supported");
	264	if (val & 0x08)
	265	hw_error("level sensitive irq not supported");
	266	} else if (val & 0x08) {
	267	if (val & 0x04)
	268	s->poll = 1;
	269	if (val & 0x02)
	270	s->read_reg_select = val & 1;
	271	if (val & 0x40)
	272	s->special_mask = (val >> 5) & 1;
	273	} else {
	274	cmd = val >> 5;
	275	switch(cmd) {
	276	case 0:
	277	case 4:
	278	s->rotate_on_auto_eoi = cmd >> 2;
	279	break;
	280	case 1: /* end of interrupt */
	281	case 5:
	282	priority = get_priority(s, s->isr);
	283	if (priority != 8) {
	284	irq = (priority + s->priority_add) & 7;
	285	s->isr &= ~(1 << irq);
	286	if (cmd == 5)
	287	s->priority_add = (irq + 1) & 7;
	288	pic_update_irq();
	289	}
	290	break;
	291	case 3:
	292	irq = val & 7;
	293	s->isr &= ~(1 << irq);
	294	pic_update_irq();
	295	break;
	296	case 6:
	297	s->priority_add = (val + 1) & 7;
	298	pic_update_irq();
	299	break;
	300	case 7:
	301	irq = val & 7;
	302	s->isr &= ~(1 << irq);
	303	s->priority_add = (irq + 1) & 7;
	304	pic_update_irq();
	305	break;
	306	default:
	307	/* no operation */
	308	break;
	309	}
	310	}
	311	} else {
	312	switch(s->init_state) {
	313	case 0:
	314	/* normal mode */
	315	s->imr = val;
	316	pic_update_irq();
	317	break;
	318	case 1:
	319	s->irq_base = val & 0xf8;
	320	s->init_state = 2;
	321	break;
	322	case 2:
	323	if (s->init4) {
324	s->init_state = 3;
325	} else {
326	s->init_state = 0;
327	}
328	break;
329	case 3:
330	s->special_fully_nested_mode = (val >> 4) & 1;
331	s->auto_eoi = (val >> 1) & 1;
332	s->init_state = 0;
333	break;
334	}
335	}
336	}
337
338	static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
339	{
340	int ret;
341
342	ret = pic_get_irq(s);
343	if (ret >= 0) {
344	if (addr1 >> 7) {
345	pics[0].isr &= ~(1 << 2);
346	pics[0].irr &= ~(1 << 2);
347	}
348	s->irr &= ~(1 << ret);
349	s->isr &= ~(1 << ret);
350	if (addr1 >> 7 \|\| ret != 2)
351	pic_update_irq();
352	} else {
353	ret = 0x07;
354	pic_update_irq();
355	}
356
357	return ret;
358	}
359
b41a2cd1	360	static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
80cabfad	361	{
b41a2cd1	362	PicState *s = opaque;
80cabfad FB	363	unsigned int addr;
	364	int ret;
	365
	366	addr = addr1;
80cabfad FB	367	addr &= 1;
	368	if (s->poll) {
	369	ret = pic_poll_read(s, addr1);
	370	s->poll = 0;
	371	} else {
	372	if (addr == 0) {
	373	if (s->read_reg_select)
	374	ret = s->isr;
	375	else
	376	ret = s->irr;
	377	} else {
	378	ret = s->imr;
	379	}
	380	}
	381	#ifdef DEBUG_PIC
	382	printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
	383	#endif
	384	return ret;
	385	}
	386
	387	/* memory mapped interrupt status */
	388	uint32_t pic_intack_read(CPUState *env)
	389	{
	390	int ret;
	391
	392	ret = pic_poll_read(&pics[0], 0x00);
	393	if (ret == 2)
	394	ret = pic_poll_read(&pics[1], 0x80) + 8;
	395	/* Prepare for ISR read */
	396	pics[0].read_reg_select = 1;
	397
	398	return ret;
	399	}
	400
660de336 FB	401	static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
	402	{
	403	PicState *s = opaque;
	404	s->elcr = val & s->elcr_mask;
	405	}
	406
	407	static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
	408	{
	409	PicState *s = opaque;
	410	return s->elcr;
	411	}
	412
b0a21b53 FB	413	static void pic_save(QEMUFile f, void opaque)
	414	{
	415	PicState *s = opaque;
	416
	417	qemu_put_8s(f, &s->last_irr);
	418	qemu_put_8s(f, &s->irr);
	419	qemu_put_8s(f, &s->imr);
	420	qemu_put_8s(f, &s->isr);
	421	qemu_put_8s(f, &s->priority_add);
	422	qemu_put_8s(f, &s->irq_base);
	423	qemu_put_8s(f, &s->read_reg_select);
	424	qemu_put_8s(f, &s->poll);
	425	qemu_put_8s(f, &s->special_mask);
	426	qemu_put_8s(f, &s->init_state);
	427	qemu_put_8s(f, &s->auto_eoi);
	428	qemu_put_8s(f, &s->rotate_on_auto_eoi);
	429	qemu_put_8s(f, &s->special_fully_nested_mode);
	430	qemu_put_8s(f, &s->init4);
660de336	431	qemu_put_8s(f, &s->elcr);
b0a21b53 FB	432	}
	433
	434	static int pic_load(QEMUFile f, void opaque, int version_id)
	435	{
	436	PicState *s = opaque;
	437
	438	if (version_id != 1)
	439	return -EINVAL;
	440
	441	qemu_get_8s(f, &s->last_irr);
	442	qemu_get_8s(f, &s->irr);
	443	qemu_get_8s(f, &s->imr);
	444	qemu_get_8s(f, &s->isr);
	445	qemu_get_8s(f, &s->priority_add);
	446	qemu_get_8s(f, &s->irq_base);
	447	qemu_get_8s(f, &s->read_reg_select);
	448	qemu_get_8s(f, &s->poll);
	449	qemu_get_8s(f, &s->special_mask);
	450	qemu_get_8s(f, &s->init_state);
	451	qemu_get_8s(f, &s->auto_eoi);
	452	qemu_get_8s(f, &s->rotate_on_auto_eoi);
	453	qemu_get_8s(f, &s->special_fully_nested_mode);
	454	qemu_get_8s(f, &s->init4);
660de336	455	qemu_get_8s(f, &s->elcr);
b0a21b53 FB	456	return 0;
	457	}
	458
	459	/* XXX: add generic master/slave system */
660de336	460	static void pic_init1(int io_addr, int elcr_addr, PicState *s)
b0a21b53 FB	461	{
	462	register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
	463	register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
660de336 FB	464	if (elcr_addr >= 0) {
	465	register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
	466	register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
	467	}
b0a21b53	468	register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
d7d02e3c	469	qemu_register_reset(pic_reset, s);
b0a21b53 FB	470	}
b0a21b53 FB	471
ba91cd80 FB	472	void pic_info(void)
	473	{
	474	int i;
	475	PicState *s;
	476
	477	for(i=0;i<2;i++) {
	478	s = &pics[i];
15aeac38	479	term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
660de336	480	i, s->irr, s->imr, s->isr, s->priority_add,
15aeac38 FB	481	s->irq_base, s->read_reg_select, s->elcr,
15aeac38 FB	482	s->special_fully_nested_mode);
ba91cd80 FB	483	}
	484	}
	485
4a0fb71e FB	486	void irq_info(void)
	487	{
	488	#ifndef DEBUG_IRQ_COUNT
	489	term_printf("irq statistic code not compiled.\n");
	490	#else
	491	int i;
	492	int64_t count;
	493
	494	term_printf("IRQ statistics:\n");
	495	for (i = 0; i < 16; i++) {
	496	count = irq_count[i];
	497	if (count > 0)
	498	term_printf("%2d: %lld\n", i, count);
	499	}
	500	#endif
	501	}
ba91cd80	502
80cabfad FB	503	void pic_init(void)
80cabfad FB	504	{
660de336 FB	505	pic_init1(0x20, 0x4d0, &pics[0]);
	506	pic_init1(0xa0, 0x4d1, &pics[1]);
	507	pics[0].elcr_mask = 0xf8;
	508	pics[1].elcr_mask = 0xde;
80cabfad FB	509	}
80cabfad FB	510