[qemu.git] / hw / dma.c

/*
 * QEMU DMA emulation
 * 
 * Copyright (c) 2003 Vassili Karpov (malc)
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_DMA

#define log(...) fprintf (stderr, "dma: " __VA_ARGS__)
#ifdef DEBUG_DMA
#define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__)
#define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
#define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
#else
#define lwarn(...)
#define linfo(...)
#define ldebug(...)
#endif

#define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))

struct dma_regs {
    int now[2];
    uint16_t base[2];
    uint8_t mode;
    uint8_t page;
    uint8_t pageh;
    uint8_t dack;
    uint8_t eop;
    DMA_transfer_handler transfer_handler;
    void *opaque;
};

#define ADDR 0
#define COUNT 1

static struct dma_cont {
    uint8_t status;
    uint8_t command;
    uint8_t mask;
    uint8_t flip_flop;
    int dshift;
    struct dma_regs regs[4];
} dma_controllers[2];

enum {
  CMD_MEMORY_TO_MEMORY = 0x01,
  CMD_FIXED_ADDRESS    = 0x02,
  CMD_BLOCK_CONTROLLER = 0x04,
  CMD_COMPRESSED_TIME  = 0x08,
  CMD_CYCLIC_PRIORITY  = 0x10,
  CMD_EXTENDED_WRITE   = 0x20,
  CMD_LOW_DREQ         = 0x40,
  CMD_LOW_DACK         = 0x80,
  CMD_NOT_SUPPORTED    = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS
  | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE
  | CMD_LOW_DREQ | CMD_LOW_DACK

};

static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};

static void write_page (void *opaque, uint32_t nport, uint32_t data)
{
    struct dma_cont *d = opaque;
    int ichan;

    ichan = channels[nport & 7];
    if (-1 == ichan) {
        log ("invalid channel %#x %#x\n", nport, data);
        return;
    }
    d->regs[ichan].page = data;
}

static void write_pageh (void *opaque, uint32_t nport, uint32_t data)
{
    struct dma_cont *d = opaque;
    int ichan;

    ichan = channels[nport & 7];
    if (-1 == ichan) {
        log ("invalid channel %#x %#x\n", nport, data);
        return;
    }
    d->regs[ichan].pageh = data;
}

static uint32_t read_page (void *opaque, uint32_t nport)
{
    struct dma_cont *d = opaque;
    int ichan;

    ichan = channels[nport & 7];
    if (-1 == ichan) {
        log ("invalid channel read %#x\n", nport);
        return 0;
    }
    return d->regs[ichan].page;
}

static uint32_t read_pageh (void *opaque, uint32_t nport)
{
    struct dma_cont *d = opaque;
    int ichan;

    ichan = channels[nport & 7];
    if (-1 == ichan) {
        log ("invalid channel read %#x\n", nport);
        return 0;
    }
    return d->regs[ichan].pageh;
}

static inline void init_chan (struct dma_cont *d, int ichan)
{
    struct dma_regs *r;

    r = d->regs + ichan;
    r->now[ADDR] = r->base[0] << d->dshift;
    r->now[COUNT] = 0;
}

static inline int getff (struct dma_cont *d)
{
    int ff;

    ff = d->flip_flop;
    d->flip_flop = !ff;
    return ff;
}

static uint32_t read_chan (void *opaque, uint32_t nport)
{
    struct dma_cont *d = opaque;
    int ichan, nreg, iport, ff, val;
    struct dma_regs *r;

    iport = (nport >> d->dshift) & 0x0f;
    ichan = iport >> 1;
    nreg = iport & 1;
    r = d->regs + ichan;

    ff = getff (d);
    if (nreg)
        val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
    else
        val = r->now[ADDR] + r->now[COUNT];

    return (val >> (d->dshift + (ff << 3))) & 0xff;
}

static void write_chan (void *opaque, uint32_t nport, uint32_t data)
{
    struct dma_cont *d = opaque;
    int iport, ichan, nreg;
    struct dma_regs *r;

    iport = (nport >> d->dshift) & 0x0f;
    ichan = iport >> 1;
    nreg = iport & 1;
    r = d->regs + ichan;
    if (getff (d)) {
        r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
        init_chan (d, ichan);
    } else {
        r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
    }
}

static void write_cont (void *opaque, uint32_t nport, uint32_t data)
{
    struct dma_cont *d = opaque;
    int iport, ichan;

    iport = (nport >> d->dshift) & 0x0f;
    switch (iport) {
    case 8:                     /* command */
        if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
            log ("command %#x not supported\n", data);
            return;
        }
        d->command = data;
        break;

    case 9:
        ichan = data & 3;
        if (data & 4) {
            d->status |= 1 << (ichan + 4);
        }
        else {
            d->status &= ~(1 << (ichan + 4));
        }
        d->status &= ~(1 << ichan);
        break;

    case 0xa:                   /* single mask */
        if (data & 4)
            d->mask |= 1 << (data & 3);
        else
            d->mask &= ~(1 << (data & 3));
        break;

    case 0xb:                   /* mode */
        {
            ichan = data & 3;
#ifdef DEBUG_DMA
            int op;
            int ai;
            int dir;
            int opmode;

            op = (data >> 2) & 3;
            ai = (data >> 4) & 1;
            dir = (data >> 5) & 1;
            opmode = (data >> 6) & 3;

            linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
                   ichan, op, ai, dir, opmode);
#endif

            d->regs[ichan].mode = data;
            break;
        }

    case 0xc:                   /* clear flip flop */
        d->flip_flop = 0;
        break;

    case 0xd:                   /* reset */
        d->flip_flop = 0;
        d->mask = ~0;
        d->status = 0;
        d->command = 0;
        break;

    case 0xe:                   /* clear mask for all channels */
        d->mask = 0;
        break;

    case 0xf:                   /* write mask for all channels */
        d->mask = data;
        break;

    default:
        log ("dma: unknown iport %#x\n", iport);
        break;
    }

#ifdef DEBUG_DMA
    if (0xc != iport) {
        linfo ("nport %#06x, ichan % 2d, val %#06x\n",
               nport, ichan, data);
    }
#endif
}

static uint32_t read_cont (void *opaque, uint32_t nport)
{
    struct dma_cont *d = opaque;
    int iport, val;
    
    iport = (nport >> d->dshift) & 0x0f;
    switch (iport) {
    case 0x08: /* status */
        val = d->status;
        d->status &= 0xf0;
        break;
    case 0x0f: /* mask */
        val = d->mask;
        break;
    default:
        val = 0;
        break;
    }
    return val;
}

int DMA_get_channel_mode (int nchan)
{
    return dma_controllers[nchan > 3].regs[nchan & 3].mode;
}

void DMA_hold_DREQ (int nchan)
{
    int ncont, ichan;

    ncont = nchan > 3;
    ichan = nchan & 3;
    linfo ("held cont=%d chan=%d\n", ncont, ichan);
    dma_controllers[ncont].status |= 1 << (ichan + 4);
}

void DMA_release_DREQ (int nchan)
{
    int ncont, ichan;

    ncont = nchan > 3;
    ichan = nchan & 3;
    linfo ("released cont=%d chan=%d\n", ncont, ichan);
    dma_controllers[ncont].status &= ~(1 << (ichan + 4));
}

static void channel_run (int ncont, int ichan)
{
    struct dma_regs *r;
    int n;
    target_ulong addr;
/*     int ai, dir; */

    r = dma_controllers[ncont].regs + ichan;
/*   ai = r->mode & 16; */
/*   dir = r->mode & 32 ? -1 : 1; */

    /* NOTE: pageh is only used by PPC PREP */
    addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
    n = r->transfer_handler (r->opaque, addr, 
                             (r->base[COUNT] << ncont) + (1 << ncont));
    r->now[COUNT] = n;

    ldebug ("dma_pos %d size %d\n",
            n, (r->base[1] << ncont) + (1 << ncont));
}

void DMA_run (void)
{
    struct dma_cont *d;
    int icont, ichan;

    d = dma_controllers;

    for (icont = 0; icont < 2; icont++, d++) {
        for (ichan = 0; ichan < 4; ichan++) {
            int mask;

            mask = 1 << ichan;

            if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4))))
                channel_run (icont, ichan);
        }
    }
}

void DMA_register_channel (int nchan,
                           DMA_transfer_handler transfer_handler, 
                           void *opaque)
{
    struct dma_regs *r;
    int ichan, ncont;

    ncont = nchan > 3;
    ichan = nchan & 3;

    r = dma_controllers[ncont].regs + ichan;
    r->transfer_handler = transfer_handler;
    r->opaque = opaque;
}

/* request the emulator to transfer a new DMA memory block ASAP */
void DMA_schedule(int nchan)
{
    cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
}

static void dma_reset(void *opaque)
{
    struct dma_cont *d = opaque;
    write_cont (d, (0x0d << d->dshift), 0);
}

/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
static void dma_init2(struct dma_cont *d, int base, int dshift, 
                      int page_base, int pageh_base)
{
    const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
    int i;

    d->dshift = dshift;
    for (i = 0; i < 8; i++) {
        register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
        register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
    }
    for (i = 0; i < LENOFA (page_port_list); i++) {
        register_ioport_write (page_base + page_port_list[i], 1, 1, 
                               write_page, d);
        register_ioport_read (page_base + page_port_list[i], 1, 1, 
                              read_page, d);
        if (pageh_base >= 0) {
            register_ioport_write (pageh_base + page_port_list[i], 1, 1, 
                                   write_pageh, d);
            register_ioport_read (pageh_base + page_port_list[i], 1, 1, 
                                  read_pageh, d);
        }
    }
    for (i = 0; i < 8; i++) {
        register_ioport_write (base + ((i + 8) << dshift), 1, 1, 
                               write_cont, d);
        register_ioport_read (base + ((i + 8) << dshift), 1, 1, 
                              read_cont, d);
    }
    qemu_register_reset(dma_reset, d);
    dma_reset(d);
}

void DMA_init (int high_page_enable)
{
    dma_init2(&dma_controllers[0], 0x00, 0, 0x80, 
              high_page_enable ? 0x480 : -1);
    dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,
              high_page_enable ? 0x488 : -1);
}
Commit	Line	Data
27503323 FB	1	/*
	2	* QEMU DMA emulation
	3	*
	4	* Copyright (c) 2003 Vassili Karpov (malc)
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
16d17fdb	24	#include "vl.h"
27503323	25
7ebb5e41 FB	26	//#define DEBUG_DMA
7ebb5e41 FB	27
27503323 FB	28	#define log(...) fprintf (stderr, "dma: " __VA_ARGS__)
	29	#ifdef DEBUG_DMA
	30	#define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__)
	31	#define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
	32	#define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
	33	#else
	34	#define lwarn(...)
	35	#define linfo(...)
	36	#define ldebug(...)
	37	#endif
	38
27503323 FB	39	#define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))
	40
	41	struct dma_regs {
	42	int now[2];
	43	uint16_t base[2];
	44	uint8_t mode;
	45	uint8_t page;
b0bda528	46	uint8_t pageh;
27503323 FB	47	uint8_t dack;
27503323 FB	48	uint8_t eop;
16f62432 FB	49	DMA_transfer_handler transfer_handler;
16f62432 FB	50	void *opaque;
27503323 FB	51	};
	52
	53	#define ADDR 0
	54	#define COUNT 1
	55
	56	static struct dma_cont {
	57	uint8_t status;
	58	uint8_t command;
	59	uint8_t mask;
	60	uint8_t flip_flop;
9eb153f1	61	int dshift;
27503323 FB	62	struct dma_regs regs[4];
	63	} dma_controllers[2];
	64
	65	enum {
	66	CMD_MEMORY_TO_MEMORY = 0x01,
	67	CMD_FIXED_ADDRESS = 0x02,
	68	CMD_BLOCK_CONTROLLER = 0x04,
	69	CMD_COMPRESSED_TIME = 0x08,
	70	CMD_CYCLIC_PRIORITY = 0x10,
	71	CMD_EXTENDED_WRITE = 0x20,
	72	CMD_LOW_DREQ = 0x40,
	73	CMD_LOW_DACK = 0x80,
	74	CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY \| CMD_FIXED_ADDRESS
	75	\| CMD_COMPRESSED_TIME \| CMD_CYCLIC_PRIORITY \| CMD_EXTENDED_WRITE
	76	\| CMD_LOW_DREQ \| CMD_LOW_DACK
	77
	78	};
	79
9eb153f1 FB	80	static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
9eb153f1 FB	81
7d977de7	82	static void write_page (void *opaque, uint32_t nport, uint32_t data)
27503323	83	{
9eb153f1	84	struct dma_cont *d = opaque;
27503323	85	int ichan;
27503323	86
9eb153f1	87	ichan = channels[nport & 7];
27503323 FB	88	if (-1 == ichan) {
	89	log ("invalid channel %#x %#x\n", nport, data);
	90	return;
	91	}
9eb153f1 FB	92	d->regs[ichan].page = data;
	93	}
	94
b0bda528	95	static void write_pageh (void *opaque, uint32_t nport, uint32_t data)
9eb153f1 FB	96	{
	97	struct dma_cont *d = opaque;
	98	int ichan;
27503323	99
9eb153f1	100	ichan = channels[nport & 7];
b0bda528 FB	101	if (-1 == ichan) {
	102	log ("invalid channel %#x %#x\n", nport, data);
	103	return;
	104	}
	105	d->regs[ichan].pageh = data;
	106	}
9eb153f1	107
b0bda528 FB	108	static uint32_t read_page (void *opaque, uint32_t nport)
	109	{
	110	struct dma_cont *d = opaque;
	111	int ichan;
	112
	113	ichan = channels[nport & 7];
9eb153f1 FB	114	if (-1 == ichan) {
	115	log ("invalid channel read %#x\n", nport);
	116	return 0;
	117	}
	118	return d->regs[ichan].page;
27503323 FB	119	}
27503323 FB	120
b0bda528 FB	121	static uint32_t read_pageh (void *opaque, uint32_t nport)
	122	{
	123	struct dma_cont *d = opaque;
	124	int ichan;
	125
	126	ichan = channels[nport & 7];
	127	if (-1 == ichan) {
	128	log ("invalid channel read %#x\n", nport);
	129	return 0;
	130	}
	131	return d->regs[ichan].pageh;
	132	}
	133
9eb153f1	134	static inline void init_chan (struct dma_cont *d, int ichan)
27503323 FB	135	{
	136	struct dma_regs *r;
	137
9eb153f1 FB	138	r = d->regs + ichan;
9eb153f1 FB	139	r->now[ADDR] = r->base[0] << d->dshift;
27503323 FB	140	r->now[COUNT] = 0;
	141	}
	142
9eb153f1	143	static inline int getff (struct dma_cont *d)
27503323 FB	144	{
	145	int ff;
	146
9eb153f1 FB	147	ff = d->flip_flop;
9eb153f1 FB	148	d->flip_flop = !ff;
27503323 FB	149	return ff;
	150	}
	151
7d977de7	152	static uint32_t read_chan (void *opaque, uint32_t nport)
27503323	153	{
9eb153f1 FB	154	struct dma_cont *d = opaque;
9eb153f1 FB	155	int ichan, nreg, iport, ff, val;
27503323	156	struct dma_regs *r;
27503323	157
9eb153f1 FB	158	iport = (nport >> d->dshift) & 0x0f;
	159	ichan = iport >> 1;
	160	nreg = iport & 1;
	161	r = d->regs + ichan;
27503323	162
9eb153f1	163	ff = getff (d);
27503323	164	if (nreg)
9eb153f1	165	val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
27503323 FB	166	else
	167	val = r->now[ADDR] + r->now[COUNT];
	168
9eb153f1	169	return (val >> (d->dshift + (ff << 3))) & 0xff;
27503323 FB	170	}
27503323 FB	171
7d977de7	172	static void write_chan (void *opaque, uint32_t nport, uint32_t data)
27503323	173	{
9eb153f1 FB	174	struct dma_cont *d = opaque;
9eb153f1 FB	175	int iport, ichan, nreg;
27503323 FB	176	struct dma_regs *r;
27503323 FB	177
9eb153f1 FB	178	iport = (nport >> d->dshift) & 0x0f;
	179	ichan = iport >> 1;
	180	nreg = iport & 1;
	181	r = d->regs + ichan;
	182	if (getff (d)) {
3504fe17	183	r->base[nreg] = (r->base[nreg] & 0xff) \| ((data << 8) & 0xff00);
9eb153f1	184	init_chan (d, ichan);
3504fe17 FB	185	} else {
3504fe17 FB	186	r->base[nreg] = (r->base[nreg] & 0xff00) \| (data & 0xff);
27503323	187	}
27503323 FB	188	}
27503323 FB	189
7d977de7	190	static void write_cont (void *opaque, uint32_t nport, uint32_t data)
27503323	191	{
9eb153f1 FB	192	struct dma_cont *d = opaque;
9eb153f1 FB	193	int iport, ichan;
27503323	194
9eb153f1	195	iport = (nport >> d->dshift) & 0x0f;
27503323 FB	196	switch (iport) {
27503323 FB	197	case 8: /* command */
df475d18	198	if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
27503323	199	log ("command %#x not supported\n", data);
df475d18	200	return;
27503323 FB	201	}
	202	d->command = data;
	203	break;
	204
	205	case 9:
	206	ichan = data & 3;
	207	if (data & 4) {
	208	d->status \|= 1 << (ichan + 4);
	209	}
	210	else {
	211	d->status &= ~(1 << (ichan + 4));
	212	}
	213	d->status &= ~(1 << ichan);
	214	break;
	215
	216	case 0xa: /* single mask */
	217	if (data & 4)
	218	d->mask \|= 1 << (data & 3);
	219	else
	220	d->mask &= ~(1 << (data & 3));
	221	break;
	222
	223	case 0xb: /* mode */
	224	{
16d17fdb FB	225	ichan = data & 3;
16d17fdb FB	226	#ifdef DEBUG_DMA
27503323 FB	227	int op;
	228	int ai;
	229	int dir;
	230	int opmode;
	231
16d17fdb FB	232	op = (data >> 2) & 3;
	233	ai = (data >> 4) & 1;
	234	dir = (data >> 5) & 1;
	235	opmode = (data >> 6) & 3;
27503323 FB	236
	237	linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
	238	ichan, op, ai, dir, opmode);
	239	#endif
	240
	241	d->regs[ichan].mode = data;
	242	break;
	243	}
	244
	245	case 0xc: /* clear flip flop */
	246	d->flip_flop = 0;
	247	break;
	248
	249	case 0xd: /* reset */
	250	d->flip_flop = 0;
	251	d->mask = ~0;
	252	d->status = 0;
	253	d->command = 0;
	254	break;
	255
	256	case 0xe: /* clear mask for all channels */
	257	d->mask = 0;
	258	break;
	259
	260	case 0xf: /* write mask for all channels */
	261	d->mask = data;
	262	break;
	263
	264	default:
	265	log ("dma: unknown iport %#x\n", iport);
df475d18	266	break;
27503323 FB	267	}
27503323 FB	268
16d17fdb	269	#ifdef DEBUG_DMA
27503323	270	if (0xc != iport) {
9eb153f1 FB	271	linfo ("nport %#06x, ichan % 2d, val %#06x\n",
9eb153f1 FB	272	nport, ichan, data);
27503323 FB	273	}
27503323 FB	274	#endif
27503323 FB	275	}
27503323 FB	276
9eb153f1 FB	277	static uint32_t read_cont (void *opaque, uint32_t nport)
	278	{
	279	struct dma_cont *d = opaque;
	280	int iport, val;
	281
	282	iport = (nport >> d->dshift) & 0x0f;
	283	switch (iport) {
	284	case 0x08: /* status */
	285	val = d->status;
	286	d->status &= 0xf0;
	287	break;
	288	case 0x0f: /* mask */
	289	val = d->mask;
	290	break;
	291	default:
	292	val = 0;
	293	break;
	294	}
	295	return val;
	296	}
	297
27503323 FB	298	int DMA_get_channel_mode (int nchan)
	299	{
	300	return dma_controllers[nchan > 3].regs[nchan & 3].mode;
	301	}
	302
	303	void DMA_hold_DREQ (int nchan)
	304	{
	305	int ncont, ichan;
	306
	307	ncont = nchan > 3;
	308	ichan = nchan & 3;
	309	linfo ("held cont=%d chan=%d\n", ncont, ichan);
	310	dma_controllers[ncont].status \|= 1 << (ichan + 4);
	311	}
	312
	313	void DMA_release_DREQ (int nchan)
	314	{
	315	int ncont, ichan;
	316
	317	ncont = nchan > 3;
	318	ichan = nchan & 3;
	319	linfo ("released cont=%d chan=%d\n", ncont, ichan);
	320	dma_controllers[ncont].status &= ~(1 << (ichan + 4));
	321	}
	322
	323	static void channel_run (int ncont, int ichan)
	324	{
	325	struct dma_regs *r;
	326	int n;
16f62432	327	target_ulong addr;
27503323 FB	328	/* int ai, dir; */
	329
	330	r = dma_controllers[ncont].regs + ichan;
	331	/* ai = r->mode & 16; */
	332	/* dir = r->mode & 32 ? -1 : 1; */
	333
b0bda528 FB	334	/* NOTE: pageh is only used by PPC PREP */
b0bda528 FB	335	addr = ((r->pageh & 0x7f) << 24) \| (r->page << 16) \| r->now[ADDR];
16f62432 FB	336	n = r->transfer_handler (r->opaque, addr,
16f62432 FB	337	(r->base[COUNT] << ncont) + (1 << ncont));
27503323 FB	338	r->now[COUNT] = n;
27503323 FB	339
16f62432 FB	340	ldebug ("dma_pos %d size %d\n",
16f62432 FB	341	n, (r->base[1] << ncont) + (1 << ncont));
27503323 FB	342	}
	343
	344	void DMA_run (void)
	345	{
27503323 FB	346	struct dma_cont *d;
	347	int icont, ichan;
	348
27503323 FB	349	d = dma_controllers;
	350
	351	for (icont = 0; icont < 2; icont++, d++) {
	352	for (ichan = 0; ichan < 4; ichan++) {
	353	int mask;
	354
	355	mask = 1 << ichan;
	356
	357	if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4))))
	358	channel_run (icont, ichan);
	359	}
	360	}
27503323 FB	361	}
	362
	363	void DMA_register_channel (int nchan,
16f62432 FB	364	DMA_transfer_handler transfer_handler,
16f62432 FB	365	void *opaque)
27503323 FB	366	{
	367	struct dma_regs *r;
	368	int ichan, ncont;
	369
	370	ncont = nchan > 3;
	371	ichan = nchan & 3;
	372
	373	r = dma_controllers[ncont].regs + ichan;
16f62432 FB	374	r->transfer_handler = transfer_handler;
	375	r->opaque = opaque;
	376	}
	377
	378	/* request the emulator to transfer a new DMA memory block ASAP */
	379	void DMA_schedule(int nchan)
	380	{
	381	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
27503323 FB	382	}
27503323 FB	383
d7d02e3c FB	384	static void dma_reset(void *opaque)
	385	{
	386	struct dma_cont *d = opaque;
	387	write_cont (d, (0x0d << d->dshift), 0);
	388	}
	389
9eb153f1	390	/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
b0bda528 FB	391	static void dma_init2(struct dma_cont *d, int base, int dshift,
b0bda528 FB	392	int page_base, int pageh_base)
27503323	393	{
9eb153f1	394	const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
27503323	395	int i;
27503323	396
9eb153f1	397	d->dshift = dshift;
27503323	398	for (i = 0; i < 8; i++) {
9eb153f1 FB	399	register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
9eb153f1 FB	400	register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
27503323	401	}
27503323	402	for (i = 0; i < LENOFA (page_port_list); i++) {
9eb153f1 FB	403	register_ioport_write (page_base + page_port_list[i], 1, 1,
	404	write_page, d);
	405	register_ioport_read (page_base + page_port_list[i], 1, 1,
	406	read_page, d);
b0bda528 FB	407	if (pageh_base >= 0) {
	408	register_ioport_write (pageh_base + page_port_list[i], 1, 1,
	409	write_pageh, d);
	410	register_ioport_read (pageh_base + page_port_list[i], 1, 1,
	411	read_pageh, d);
	412	}
27503323	413	}
27503323	414	for (i = 0; i < 8; i++) {
9eb153f1 FB	415	register_ioport_write (base + ((i + 8) << dshift), 1, 1,
	416	write_cont, d);
	417	register_ioport_read (base + ((i + 8) << dshift), 1, 1,
	418	read_cont, d);
27503323	419	}
d7d02e3c FB	420	qemu_register_reset(dma_reset, d);
d7d02e3c FB	421	dma_reset(d);
9eb153f1	422	}
27503323	423
b0bda528	424	void DMA_init (int high_page_enable)
9eb153f1	425	{
b0bda528 FB	426	dma_init2(&dma_controllers[0], 0x00, 0, 0x80,
	427	high_page_enable ? 0x480 : -1);
	428	dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,
	429	high_page_enable ? 0x488 : -1);
27503323	430	}