[qemu.git] / hw / pci / pci_bridge.c

/*
 * QEMU PCI bus manager
 *
 * Copyright (c) 2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to dea

 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
/*
 * split out from pci.c
 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
 *                    VA Linux Systems Japan K.K.
 */

#include "qemu/osdep.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pci_bus.h"
#include "qemu/range.h"
#include "qapi/error.h"

/* PCI bridge subsystem vendor ID helper functions */
#define PCI_SSVID_SIZEOF        8
#define PCI_SSVID_SVID          4
#define PCI_SSVID_SSID          6

int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
                          uint16_t svid, uint16_t ssid,
                          Error **errp)
{
    int pos;

    pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,
                             PCI_SSVID_SIZEOF, errp);
    if (pos < 0) {
        return pos;
    }

    pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
    pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
    return pos;
}

/* Accessor function to get parent bridge device from pci bus. */
PCIDevice *pci_bridge_get_device(PCIBus *bus)
{
    return bus->parent_dev;
}

/* Accessor function to get secondary bus from pci-to-pci bridge device */
PCIBus *pci_bridge_get_sec_bus(PCIBridge *br)
{
    return &br->sec_bus;
}

static uint32_t pci_config_get_io_base(const PCIDevice *d,
                                       uint32_t base, uint32_t base_upper16)
{
    uint32_t val;

    val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
    if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
        val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
    }
    return val;
}

static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base)
{
    return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
        << 16;
}

static pcibus_t pci_config_get_pref_base(const PCIDevice *d,
                                         uint32_t base, uint32_t upper)
{
    pcibus_t tmp;
    pcibus_t val;

    tmp = (pcibus_t)pci_get_word(d->config + base);
    val = (tmp & PCI_PREF_RANGE_MASK) << 16;
    if (tmp & PCI_PREF_RANGE_TYPE_64) {
        val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
    }
    return val;
}

/* accessor function to get bridge filtering base address */
pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
{
    pcibus_t base;
    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
        base = pci_config_get_io_base(bridge,
                                      PCI_IO_BASE, PCI_IO_BASE_UPPER16);
    } else {
        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
            base = pci_config_get_pref_base(
                bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
        } else {
            base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
        }
    }

    return base;
}

/* accessor function to get bridge filtering limit */
pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
{
    pcibus_t limit;
    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
        limit = pci_config_get_io_base(bridge,
                                      PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
        limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
    } else {
        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
            limit = pci_config_get_pref_base(
                bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
        } else {
            limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
        }
        limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
    }
    return limit;
}

static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
                                  uint8_t type, const char *name,
                                  MemoryRegion *space,
                                  MemoryRegion *parent_space,
                                  bool enabled)
{
    PCIDevice *bridge_dev = PCI_DEVICE(bridge);
    pcibus_t base = pci_bridge_get_base(bridge_dev, type);
    pcibus_t limit = pci_bridge_get_limit(bridge_dev, type);
    /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
     * Apparently no way to do this with existing memory APIs. */
    pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;

    memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size);
    memory_region_add_subregion_overlap(parent_space, base, alias, 1);
}

static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
                                        MemoryRegion *alias_vga)
{
    PCIDevice *pd = PCI_DEVICE(br);
    uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL);

    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br),
                             "pci_bridge_vga_io_lo", &br->address_space_io,
                             QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE);
    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br),
                             "pci_bridge_vga_io_hi", &br->address_space_io,
                             QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE);
    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br),
                             "pci_bridge_vga_mem", &br->address_space_mem,
                             QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);

    if (brctl & PCI_BRIDGE_CTL_VGA) {
        pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM],
                         &alias_vga[QEMU_PCI_VGA_IO_LO],
                         &alias_vga[QEMU_PCI_VGA_IO_HI]);
    }
}

static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br)
{
    PCIDevice *pd = PCI_DEVICE(br);
    PCIBus *parent = pci_get_bus(pd);
    PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1);
    uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND);

    pci_bridge_init_alias(br, &w->alias_pref_mem,
                          PCI_BASE_ADDRESS_MEM_PREFETCH,
                          "pci_bridge_pref_mem",
                          &br->address_space_mem,
                          parent->address_space_mem,
                          cmd & PCI_COMMAND_MEMORY);
    pci_bridge_init_alias(br, &w->alias_mem,
                          PCI_BASE_ADDRESS_SPACE_MEMORY,
                          "pci_bridge_mem",
                          &br->address_space_mem,
                          parent->address_space_mem,
                          cmd & PCI_COMMAND_MEMORY);
    pci_bridge_init_alias(br, &w->alias_io,
                          PCI_BASE_ADDRESS_SPACE_IO,
                          "pci_bridge_io",
                          &br->address_space_io,
                          parent->address_space_io,
                          cmd & PCI_COMMAND_IO);

    pci_bridge_init_vga_aliases(br, parent, w->alias_vga);

    return w;
}

static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w)
{
    PCIDevice *pd = PCI_DEVICE(br);
    PCIBus *parent = pci_get_bus(pd);

    memory_region_del_subregion(parent->address_space_io, &w->alias_io);
    memory_region_del_subregion(parent->address_space_mem, &w->alias_mem);
    memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem);
    pci_unregister_vga(pd);
}

static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w)
{
    object_unparent(OBJECT(&w->alias_io));
    object_unparent(OBJECT(&w->alias_mem));
    object_unparent(OBJECT(&w->alias_pref_mem));
    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_LO]));
    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_HI]));
    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_MEM]));
    g_free(w);
}

void pci_bridge_update_mappings(PCIBridge *br)
{
    PCIBridgeWindows *w = br->windows;

    /* Make updates atomic to: handle the case of one VCPU updating the bridge
     * while another accesses an unaffected region. */
    memory_region_transaction_begin();
    pci_bridge_region_del(br, br->windows);
    pci_bridge_region_cleanup(br, w);
    br->windows = pci_bridge_region_init(br);
    memory_region_transaction_commit();
}

/* default write_config function for PCI-to-PCI bridge */
void pci_bridge_write_config(PCIDevice *d,
                             uint32_t address, uint32_t val, int len)
{
    PCIBridge *s = PCI_BRIDGE(d);
    uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
    uint16_t newctl;

    pci_default_write_config(d, address, val, len);

    if (ranges_overlap(address, len, PCI_COMMAND, 2) ||

        /* io base/limit */
        ranges_overlap(address, len, PCI_IO_BASE, 2) ||

        /* memory base/limit, prefetchable base/limit and
           io base/limit upper 16 */
        ranges_overlap(address, len, PCI_MEMORY_BASE, 20) ||

        /* vga enable */
        ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {
        pci_bridge_update_mappings(s);
    }

    newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
    if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
        /* Trigger hot reset on 0->1 transition. */
        qbus_reset_all(&s->sec_bus.qbus);
    }
}

void pci_bridge_disable_base_limit(PCIDevice *dev)
{
    uint8_t *conf = dev->config;

    pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
                               PCI_IO_RANGE_MASK & 0xff);
    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
                                 PCI_IO_RANGE_MASK & 0xff);
    pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
                               PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
                                 PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
                               PCI_PREF_RANGE_MASK & 0xffff);
    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
                                 PCI_PREF_RANGE_MASK & 0xffff);
    pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
    pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
}

/* reset bridge specific configuration registers */
void pci_bridge_reset(DeviceState *qdev)
{
    PCIDevice *dev = PCI_DEVICE(qdev);
    uint8_t *conf = dev->config;

    conf[PCI_PRIMARY_BUS] = 0;
    conf[PCI_SECONDARY_BUS] = 0;
    conf[PCI_SUBORDINATE_BUS] = 0;
    conf[PCI_SEC_LATENCY_TIMER] = 0;

    /*
     * the default values for base/limit registers aren't specified
     * in the PCI-to-PCI-bridge spec. So we don't thouch them here.
     * Each implementation can override it.
     * typical implementation does
     * zero base/limit registers or
     * disable forwarding: pci_bridge_disable_base_limit()
     * If disable forwarding is wanted, call pci_bridge_disable_base_limit()
     * after this function.
     */
    pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
                                 PCI_IO_RANGE_MASK & 0xff);
    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
                                 PCI_IO_RANGE_MASK & 0xff);
    pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
                                 PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
                                 PCI_MEMORY_RANGE_MASK & 0xffff);
    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
                                 PCI_PREF_RANGE_MASK & 0xffff);
    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
                                 PCI_PREF_RANGE_MASK & 0xffff);
    pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
    pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);

    pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
}

/* default qdev initialization function for PCI-to-PCI bridge */
void pci_bridge_initfn(PCIDevice *dev, const char *typename)
{
    PCIBus *parent = pci_get_bus(dev);
    PCIBridge *br = PCI_BRIDGE(dev);
    PCIBus *sec_bus = &br->sec_bus;

    pci_word_test_and_set_mask(dev->config + PCI_STATUS,
                               PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);

    /*
     * TODO: We implement VGA Enable in the Bridge Control Register
     * therefore per the PCI to PCI bridge spec we must also implement
     * VGA Palette Snooping.  When done, set this bit writable:
     *
     * pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND,
     *                            PCI_COMMAND_VGA_PALETTE);
     */

    pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
    dev->config[PCI_HEADER_TYPE] =
        (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
        PCI_HEADER_TYPE_BRIDGE;
    pci_set_word(dev->config + PCI_SEC_STATUS,
                 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);

    /*
     * If we don't specify the name, the bus will be addressed as <id>.0, where
     * id is the device id.
     * Since PCI Bridge devices have a single bus each, we don't need the index:
     * let users address the bus using the device name.
     */
    if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
            br->bus_name = dev->qdev.id;
    }

    qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
                        br->bus_name);
    sec_bus->parent_dev = dev;
    sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
    sec_bus->address_space_mem = &br->address_space_mem;
    memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
    sec_bus->address_space_io = &br->address_space_io;
    memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
                       UINT32_MAX);
    br->windows = pci_bridge_region_init(br);
    QLIST_INIT(&sec_bus->child);
    QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
}

/* default qdev clean up function for PCI-to-PCI bridge */
void pci_bridge_exitfn(PCIDevice *pci_dev)
{
    PCIBridge *s = PCI_BRIDGE(pci_dev);
    assert(QLIST_EMPTY(&s->sec_bus.child));
    QLIST_REMOVE(&s->sec_bus, sibling);
    pci_bridge_region_del(s, s->windows);
    pci_bridge_region_cleanup(s, s->windows);
    /* object_unparent() is called automatically during device deletion */
}

/*
 * before qdev initialization(qdev_init()), this function sets bus_name and
 * map_irq callback which are necessary for pci_bridge_initfn() to
 * initialize bus.
 */
void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
                        pci_map_irq_fn map_irq)
{
    br->map_irq = map_irq;
    br->bus_name = bus_name;
}


int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
                                     PCIResReserve res_reserve, Error **errp)
{
    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
        res_reserve.mem_pref_64 != (uint64_t)-1) {
        error_setg(errp,
                   "PCI resource reserve cap: PREF32 and PREF64 conflict");
        return -EINVAL;
    }

    if (res_reserve.mem_non_pref != (uint64_t)-1 &&
        res_reserve.mem_non_pref >= (1ULL << 32)) {
        error_setg(errp,
                   "PCI resource reserve cap: mem-reserve must be less than 4G");
        return -EINVAL;
    }

    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
        res_reserve.mem_pref_32 >= (1ULL << 32)) {
        error_setg(errp,
                   "PCI resource reserve cap: pref32-reserve  must be less than 4G");
        return -EINVAL;
    }

    if (res_reserve.bus == (uint32_t)-1 &&
        res_reserve.io == (uint64_t)-1 &&
        res_reserve.mem_non_pref == (uint64_t)-1 &&
        res_reserve.mem_pref_32 == (uint64_t)-1 &&
        res_reserve.mem_pref_64 == (uint64_t)-1) {
        return 0;
    }

    size_t cap_len = sizeof(PCIBridgeQemuCap);
    PCIBridgeQemuCap cap = {
            .len = cap_len,
            .type = REDHAT_PCI_CAP_RESOURCE_RESERVE,
            .bus_res = res_reserve.bus,
            .io = res_reserve.io,
            .mem = res_reserve.mem_non_pref,
            .mem_pref_32 = res_reserve.mem_pref_32,
            .mem_pref_64 = res_reserve.mem_pref_64
    };

    int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
                                    cap_offset, cap_len, errp);
    if (offset < 0) {
        return offset;
    }

    memcpy(dev->config + offset + PCI_CAP_FLAGS,
           (char *)&cap + PCI_CAP_FLAGS,
           cap_len - PCI_CAP_FLAGS);
    return 0;
}

static const TypeInfo pci_bridge_type_info = {
    .name = TYPE_PCI_BRIDGE,
    .parent = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIBridge),
    .abstract = true,
};

static void pci_bridge_register_types(void)
{
    type_register_static(&pci_bridge_type_info);
}

type_init(pci_bridge_register_types)
Commit	Line	Data
783753fd IY	1	/*
	2	* QEMU PCI bus manager
	3	*
	4	* Copyright (c) 2004 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to dea
	8
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
	22
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
	26	/*
	27	* split out from pci.c
	28	* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
	29	* VA Linux Systems Japan K.K.
	30	*/
	31
97d5408f	32	#include "qemu/osdep.h"
c759b24f	33	#include "hw/pci/pci_bridge.h"
06aac7bd	34	#include "hw/pci/pci_bus.h"
1de7afc9	35	#include "qemu/range.h"
9a7c2a59	36	#include "qapi/error.h"
783753fd	37
f4c817e0 IY	38	/* PCI bridge subsystem vendor ID helper functions */
	39	#define PCI_SSVID_SIZEOF 8
	40	#define PCI_SSVID_SVID 4
	41	#define PCI_SSVID_SSID 6
	42
	43	int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
f8cd1b02 MZ	44	uint16_t svid, uint16_t ssid,
f8cd1b02 MZ	45	Error **errp)
f4c817e0 IY	46	{
f4c817e0 IY	47	int pos;
9a7c2a59 MZ	48
9a7c2a59 MZ	49	pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,
f8cd1b02	50	PCI_SSVID_SIZEOF, errp);
f4c817e0 IY	51	if (pos < 0) {
	52	return pos;
	53	}
	54
	55	pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
	56	pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
	57	return pos;
	58	}
	59
68f79994	60	/* Accessor function to get parent bridge device from pci bus. */
783753fd IY	61	PCIDevice pci_bridge_get_device(PCIBus bus)
	62	{
	63	return bus->parent_dev;
	64	}
	65
68f79994 IY	66	/* Accessor function to get secondary bus from pci-to-pci bridge device */
	67	PCIBus pci_bridge_get_sec_bus(PCIBridge br)
	68	{
	69	return &br->sec_bus;
	70	}
	71
	72	static uint32_t pci_config_get_io_base(const PCIDevice *d,
783753fd IY	73	uint32_t base, uint32_t base_upper16)
	74	{
	75	uint32_t val;
	76
	77	val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
	78	if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
	79	val \|= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
	80	}
	81	return val;
	82	}
	83
68f79994	84	static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base)
783753fd IY	85	{
	86	return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
	87	<< 16;
	88	}
	89
68f79994	90	static pcibus_t pci_config_get_pref_base(const PCIDevice *d,
783753fd IY	91	uint32_t base, uint32_t upper)
	92	{
	93	pcibus_t tmp;
	94	pcibus_t val;
	95
	96	tmp = (pcibus_t)pci_get_word(d->config + base);
	97	val = (tmp & PCI_PREF_RANGE_MASK) << 16;
	98	if (tmp & PCI_PREF_RANGE_TYPE_64) {
	99	val \|= (pcibus_t)pci_get_long(d->config + upper) << 32;
	100	}
	101	return val;
	102	}
	103
68f79994 IY	104	/* accessor function to get bridge filtering base address */
68f79994 IY	105	pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
783753fd IY	106	{
	107	pcibus_t base;
	108	if (type & PCI_BASE_ADDRESS_SPACE_IO) {
	109	base = pci_config_get_io_base(bridge,
	110	PCI_IO_BASE, PCI_IO_BASE_UPPER16);
	111	} else {
	112	if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
	113	base = pci_config_get_pref_base(
	114	bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
	115	} else {
	116	base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
	117	}
	118	}
	119
	120	return base;
	121	}
	122
cb8d4c8f	123	/* accessor function to get bridge filtering limit */
68f79994	124	pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
783753fd IY	125	{
	126	pcibus_t limit;
	127	if (type & PCI_BASE_ADDRESS_SPACE_IO) {
	128	limit = pci_config_get_io_base(bridge,
	129	PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
	130	limit \|= 0xfff; /* PCI bridge spec 3.2.5.6. */
	131	} else {
	132	if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
	133	limit = pci_config_get_pref_base(
	134	bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
	135	} else {
	136	limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
	137	}
	138	limit \|= 0xfffff; /* PCI bridge spec 3.2.5.{1, 8}. */
	139	}
	140	return limit;
	141	}
	142
7df32ca0 MT	143	static void pci_bridge_init_alias(PCIBridge bridge, MemoryRegion alias,
	144	uint8_t type, const char *name,
	145	MemoryRegion *space,
	146	MemoryRegion *parent_space,
	147	bool enabled)
	148	{
f055e96b AF	149	PCIDevice *bridge_dev = PCI_DEVICE(bridge);
	150	pcibus_t base = pci_bridge_get_base(bridge_dev, type);
	151	pcibus_t limit = pci_bridge_get_limit(bridge_dev, type);
7df32ca0 MT	152	/* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
	153	* Apparently no way to do this with existing memory APIs. */
	154	pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;
	155
40c5dce9	156	memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size);
7df32ca0 MT	157	memory_region_add_subregion_overlap(parent_space, base, alias, 1);
	158	}
	159
ba7d8515 AW	160	static void pci_bridge_init_vga_aliases(PCIBridge br, PCIBus parent,
	161	MemoryRegion *alias_vga)
	162	{
f055e96b AF	163	PCIDevice *pd = PCI_DEVICE(br);
f055e96b AF	164	uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL);
ba7d8515	165
40c5dce9	166	memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br),
ba7d8515 AW	167	"pci_bridge_vga_io_lo", &br->address_space_io,
ba7d8515 AW	168	QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE);
40c5dce9	169	memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br),
ba7d8515 AW	170	"pci_bridge_vga_io_hi", &br->address_space_io,
ba7d8515 AW	171	QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE);
40c5dce9	172	memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br),
ba7d8515 AW	173	"pci_bridge_vga_mem", &br->address_space_mem,
	174	QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);
	175
	176	if (brctl & PCI_BRIDGE_CTL_VGA) {
f055e96b	177	pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM],
ba7d8515 AW	178	&alias_vga[QEMU_PCI_VGA_IO_LO],
	179	&alias_vga[QEMU_PCI_VGA_IO_HI]);
	180	}
	181	}
	182
b308c82c	183	static PCIBridgeWindows pci_bridge_region_init(PCIBridge br)
7df32ca0	184	{
f055e96b	185	PCIDevice *pd = PCI_DEVICE(br);
fd56e061	186	PCIBus *parent = pci_get_bus(pd);
b308c82c	187	PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1);
f055e96b	188	uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND);
7df32ca0	189
b308c82c	190	pci_bridge_init_alias(br, &w->alias_pref_mem,
7df32ca0 MT	191	PCI_BASE_ADDRESS_MEM_PREFETCH,
7df32ca0 MT	192	"pci_bridge_pref_mem",
336411ca	193	&br->address_space_mem,
7df32ca0 MT	194	parent->address_space_mem,
7df32ca0 MT	195	cmd & PCI_COMMAND_MEMORY);
b308c82c	196	pci_bridge_init_alias(br, &w->alias_mem,
7df32ca0 MT	197	PCI_BASE_ADDRESS_SPACE_MEMORY,
7df32ca0 MT	198	"pci_bridge_mem",
336411ca	199	&br->address_space_mem,
7df32ca0 MT	200	parent->address_space_mem,
7df32ca0 MT	201	cmd & PCI_COMMAND_MEMORY);
b308c82c	202	pci_bridge_init_alias(br, &w->alias_io,
7df32ca0 MT	203	PCI_BASE_ADDRESS_SPACE_IO,
7df32ca0 MT	204	"pci_bridge_io",
336411ca	205	&br->address_space_io,
7df32ca0 MT	206	parent->address_space_io,
7df32ca0 MT	207	cmd & PCI_COMMAND_IO);
ba7d8515 AW	208
ba7d8515 AW	209	pci_bridge_init_vga_aliases(br, parent, w->alias_vga);
b308c82c AK	210
b308c82c AK	211	return w;
7df32ca0 MT	212	}
7df32ca0 MT	213
b308c82c	214	static void pci_bridge_region_del(PCIBridge br, PCIBridgeWindows w)
7df32ca0	215	{
f055e96b	216	PCIDevice *pd = PCI_DEVICE(br);
fd56e061	217	PCIBus *parent = pci_get_bus(pd);
b308c82c AK	218
	219	memory_region_del_subregion(parent->address_space_io, &w->alias_io);
	220	memory_region_del_subregion(parent->address_space_mem, &w->alias_mem);
	221	memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem);
f055e96b	222	pci_unregister_vga(pd);
b308c82c AK	223	}
	224
	225	static void pci_bridge_region_cleanup(PCIBridge br, PCIBridgeWindows w)
	226	{
9f6b2f1c PB	227	object_unparent(OBJECT(&w->alias_io));
	228	object_unparent(OBJECT(&w->alias_mem));
	229	object_unparent(OBJECT(&w->alias_pref_mem));
	230	object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_LO]));
	231	object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_HI]));
	232	object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_MEM]));
b308c82c	233	g_free(w);
7df32ca0 MT	234	}
7df32ca0 MT	235
e78e9ae4	236	void pci_bridge_update_mappings(PCIBridge *br)
7df32ca0	237	{
b308c82c AK	238	PCIBridgeWindows *w = br->windows;
b308c82c AK	239
7df32ca0 MT	240	/* Make updates atomic to: handle the case of one VCPU updating the bridge
	241	* while another accesses an unaffected region. */
	242	memory_region_transaction_begin();
b308c82c	243	pci_bridge_region_del(br, br->windows);
e7176cdb	244	pci_bridge_region_cleanup(br, w);
b308c82c	245	br->windows = pci_bridge_region_init(br);
7df32ca0 MT	246	memory_region_transaction_commit();
	247	}
	248
68f79994 IY	249	/* default write_config function for PCI-to-PCI bridge */
68f79994 IY	250	void pci_bridge_write_config(PCIDevice *d,
783753fd IY	251	uint32_t address, uint32_t val, int len)
783753fd IY	252	{
f055e96b	253	PCIBridge *s = PCI_BRIDGE(d);
a5fce077 IY	254	uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
	255	uint16_t newctl;
	256
783753fd IY	257	pci_default_write_config(d, address, val, len);
783753fd IY	258
7df32ca0 MT	259	if (ranges_overlap(address, len, PCI_COMMAND, 2) \|\|
	260
	261	/* io base/limit */
783753fd IY	262	ranges_overlap(address, len, PCI_IO_BASE, 2) \|\|
	263
	264	/* memory base/limit, prefetchable base/limit and
	265	io base/limit upper 16 */
ba7d8515 AW	266	ranges_overlap(address, len, PCI_MEMORY_BASE, 20) \|\|
	267
	268	/* vga enable */
	269	ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {
7df32ca0	270	pci_bridge_update_mappings(s);
783753fd	271	}
a5fce077 IY	272
	273	newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
	274	if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
	275	/* Trigger hot reset on 0->1 transition. */
81e3e75b	276	qbus_reset_all(&s->sec_bus.qbus);
a5fce077	277	}
783753fd IY	278	}
783753fd IY	279
0208def1 IY	280	void pci_bridge_disable_base_limit(PCIDevice *dev)
	281	{
	282	uint8_t *conf = dev->config;
	283
	284	pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
	285	PCI_IO_RANGE_MASK & 0xff);
	286	pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
	287	PCI_IO_RANGE_MASK & 0xff);
	288	pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
	289	PCI_MEMORY_RANGE_MASK & 0xffff);
	290	pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
	291	PCI_MEMORY_RANGE_MASK & 0xffff);
	292	pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
	293	PCI_PREF_RANGE_MASK & 0xffff);
	294	pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
	295	PCI_PREF_RANGE_MASK & 0xffff);
cd7898f7 MT	296	pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
cd7898f7 MT	297	pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
0208def1 IY	298	}
0208def1 IY	299
68f79994	300	/* reset bridge specific configuration registers */
cbd2d434	301	void pci_bridge_reset(DeviceState *qdev)
68f79994	302	{
cbd2d434	303	PCIDevice *dev = PCI_DEVICE(qdev);
68f79994 IY	304	uint8_t *conf = dev->config;
	305
	306	conf[PCI_PRIMARY_BUS] = 0;
	307	conf[PCI_SECONDARY_BUS] = 0;
	308	conf[PCI_SUBORDINATE_BUS] = 0;
	309	conf[PCI_SEC_LATENCY_TIMER] = 0;
	310
0208def1 IY	311	/*
	312	* the default values for base/limit registers aren't specified
	313	* in the PCI-to-PCI-bridge spec. So we don't thouch them here.
	314	* Each implementation can override it.
	315	* typical implementation does
	316	* zero base/limit registers or
	317	* disable forwarding: pci_bridge_disable_base_limit()
	318	* If disable forwarding is wanted, call pci_bridge_disable_base_limit()
	319	* after this function.
	320	*/
	321	pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
	322	PCI_IO_RANGE_MASK & 0xff);
	323	pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
	324	PCI_IO_RANGE_MASK & 0xff);
	325	pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
	326	PCI_MEMORY_RANGE_MASK & 0xffff);
	327	pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
	328	PCI_MEMORY_RANGE_MASK & 0xffff);
	329	pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
	330	PCI_PREF_RANGE_MASK & 0xffff);
	331	pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
	332	PCI_PREF_RANGE_MASK & 0xffff);
cd7898f7 MT	333	pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
cd7898f7 MT	334	pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
68f79994 IY	335
	336	pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
	337	}
	338
68f79994	339	/* default qdev initialization function for PCI-to-PCI bridge */
9cfaa007	340	void pci_bridge_initfn(PCIDevice dev, const char typename)
68f79994	341	{
fd56e061	342	PCIBus *parent = pci_get_bus(dev);
f055e96b	343	PCIBridge *br = PCI_BRIDGE(dev);
68f79994	344	PCIBus *sec_bus = &br->sec_bus;
783753fd	345
95be1196 MT	346	pci_word_test_and_set_mask(dev->config + PCI_STATUS,
95be1196 MT	347	PCI_STATUS_66MHZ \| PCI_STATUS_FAST_BACK);
ba7d8515 AW	348
	349	/*
	350	* TODO: We implement VGA Enable in the Bridge Control Register
	351	* therefore per the PCI to PCI bridge spec we must also implement
	352	* VGA Palette Snooping. When done, set this bit writable:
	353	*
	354	* pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND,
	355	* PCI_COMMAND_VGA_PALETTE);
	356	*/
	357
783753fd IY	358	pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
	359	dev->config[PCI_HEADER_TYPE] =
	360	(dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) \|
	361	PCI_HEADER_TYPE_BRIDGE;
	362	pci_set_word(dev->config + PCI_SEC_STATUS,
	363	PCI_STATUS_66MHZ \| PCI_STATUS_FAST_BACK);
68f79994	364
8a3d80fa MT	365	/*
	366	* If we don't specify the name, the bus will be addressed as <id>.0, where
	367	* id is the device id.
	368	* Since PCI Bridge devices have a single bus each, we don't need the index:
	369	* let users address the bus using the device name.
	370	*/
	371	if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
7d37435b	372	br->bus_name = dev->qdev.id;
8a3d80fa MT	373	}
8a3d80fa MT	374
fb17dfe0 AF	375	qbus_create_inplace(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
fb17dfe0 AF	376	br->bus_name);
68f79994	377	sec_bus->parent_dev = dev;
659fefee	378	sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
336411ca	379	sec_bus->address_space_mem = &br->address_space_mem;
cf252e51	380	memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
336411ca	381	sec_bus->address_space_io = &br->address_space_io;
9cd1e97a MCA	382	memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
9cd1e97a MCA	383	UINT32_MAX);
b308c82c	384	br->windows = pci_bridge_region_init(br);
68f79994 IY	385	QLIST_INIT(&sec_bus->child);
68f79994 IY	386	QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
783753fd IY	387	}
783753fd IY	388
68f79994	389	/* default qdev clean up function for PCI-to-PCI bridge */
f90c2bcd	390	void pci_bridge_exitfn(PCIDevice *pci_dev)
783753fd	391	{
f055e96b	392	PCIBridge *s = PCI_BRIDGE(pci_dev);
51a92333 IY	393	assert(QLIST_EMPTY(&s->sec_bus.child));
51a92333 IY	394	QLIST_REMOVE(&s->sec_bus, sibling);
b308c82c AK	395	pci_bridge_region_del(s, s->windows);
b308c82c AK	396	pci_bridge_region_cleanup(s, s->windows);
6780a22c	397	/* object_unparent() is called automatically during device deletion */
783753fd IY	398	}
783753fd IY	399
68f79994 IY	400	/*
68f79994 IY	401	* before qdev initialization(qdev_init()), this function sets bus_name and
d05eec73	402	* map_irq callback which are necessary for pci_bridge_initfn() to
68f79994 IY	403	* initialize bus.
	404	*/
	405	void pci_bridge_map_irq(PCIBridge br, const char bus_name,
	406	pci_map_irq_fn map_irq)
783753fd	407	{
68f79994 IY	408	br->map_irq = map_irq;
68f79994 IY	409	br->bus_name = bus_name;
783753fd	410	}
f055e96b	411
70e1ee59 AB	412
70e1ee59 AB	413	int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
9e899399	414	PCIResReserve res_reserve, Error **errp)
70e1ee59	415	{
9e899399 JL	416	if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
9e899399 JL	417	res_reserve.mem_pref_64 != (uint64_t)-1) {
70e1ee59 AB	418	error_setg(errp,
	419	"PCI resource reserve cap: PREF32 and PREF64 conflict");
	420	return -EINVAL;
	421	}
	422
9e899399 JL	423	if (res_reserve.mem_non_pref != (uint64_t)-1 &&
9e899399 JL	424	res_reserve.mem_non_pref >= (1ULL << 32)) {
fc67208f MA	425	error_setg(errp,
	426	"PCI resource reserve cap: mem-reserve must be less than 4G");
	427	return -EINVAL;
	428	}
	429
9e899399 JL	430	if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
9e899399 JL	431	res_reserve.mem_pref_32 >= (1ULL << 32)) {
fc67208f MA	432	error_setg(errp,
	433	"PCI resource reserve cap: pref32-reserve must be less than 4G");
	434	return -EINVAL;
	435	}
	436
9e899399 JL	437	if (res_reserve.bus == (uint32_t)-1 &&
	438	res_reserve.io == (uint64_t)-1 &&
	439	res_reserve.mem_non_pref == (uint64_t)-1 &&
	440	res_reserve.mem_pref_32 == (uint64_t)-1 &&
	441	res_reserve.mem_pref_64 == (uint64_t)-1) {
70e1ee59 AB	442	return 0;
	443	}
	444
	445	size_t cap_len = sizeof(PCIBridgeQemuCap);
	446	PCIBridgeQemuCap cap = {
	447	.len = cap_len,
	448	.type = REDHAT_PCI_CAP_RESOURCE_RESERVE,
9e899399 JL	449	.bus_res = res_reserve.bus,
	450	.io = res_reserve.io,
	451	.mem = res_reserve.mem_non_pref,
	452	.mem_pref_32 = res_reserve.mem_pref_32,
	453	.mem_pref_64 = res_reserve.mem_pref_64
70e1ee59 AB	454	};
	455
	456	int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
	457	cap_offset, cap_len, errp);
	458	if (offset < 0) {
	459	return offset;
	460	}
	461
	462	memcpy(dev->config + offset + PCI_CAP_FLAGS,
	463	(char *)&cap + PCI_CAP_FLAGS,
	464	cap_len - PCI_CAP_FLAGS);
	465	return 0;
	466	}
	467
f055e96b AF	468	static const TypeInfo pci_bridge_type_info = {
	469	.name = TYPE_PCI_BRIDGE,
	470	.parent = TYPE_PCI_DEVICE,
	471	.instance_size = sizeof(PCIBridge),
	472	.abstract = true,
	473	};
	474
	475	static void pci_bridge_register_types(void)
	476	{
	477	type_register_static(&pci_bridge_type_info);
	478	}
	479
	480	type_init(pci_bridge_register_types)