[qemu.git] / target-alpha / cpu.h

/*
 *  Alpha emulation cpu definitions for qemu.
 *
 *  Copyright (c) 2007 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#if !defined (__CPU_ALPHA_H__)
#define __CPU_ALPHA_H__

#include "config.h"
#include "qemu-common.h"

#define TARGET_LONG_BITS 64

#define CPUArchState struct CPUAlphaState

#include "cpu-defs.h"

#include "softfloat.h"

#define TARGET_HAS_ICE 1

#define ELF_MACHINE     EM_ALPHA

#define ICACHE_LINE_SIZE 32
#define DCACHE_LINE_SIZE 32

#define TARGET_PAGE_BITS 13

#ifdef CONFIG_USER_ONLY
/* ??? The kernel likes to give addresses in high memory.  If the host has
   more virtual address space than the guest, this can lead to impossible
   allocations.  Honor the long-standing assumption that only kernel addrs
   are negative, but otherwise allow allocations anywhere.  This could lead
   to tricky emulation problems for programs doing tagged addressing, but
   that's far fewer than encounter the impossible allocation problem.  */
#define TARGET_PHYS_ADDR_SPACE_BITS  63
#define TARGET_VIRT_ADDR_SPACE_BITS  63
#else
/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44.  */
#define TARGET_PHYS_ADDR_SPACE_BITS  44
#define TARGET_VIRT_ADDR_SPACE_BITS  (30 + TARGET_PAGE_BITS)
#endif

/* Alpha major type */
enum {
    ALPHA_EV3  = 1,
    ALPHA_EV4  = 2,
    ALPHA_SIM  = 3,
    ALPHA_LCA  = 4,
    ALPHA_EV5  = 5, /* 21164 */
    ALPHA_EV45 = 6, /* 21064A */
    ALPHA_EV56 = 7, /* 21164A */
};

/* EV4 minor type */
enum {
    ALPHA_EV4_2 = 0,
    ALPHA_EV4_3 = 1,
};

/* LCA minor type */
enum {
    ALPHA_LCA_1 = 1, /* 21066 */
    ALPHA_LCA_2 = 2, /* 20166 */
    ALPHA_LCA_3 = 3, /* 21068 */
    ALPHA_LCA_4 = 4, /* 21068 */
    ALPHA_LCA_5 = 5, /* 21066A */
    ALPHA_LCA_6 = 6, /* 21068A */
};

/* EV5 minor type */
enum {
    ALPHA_EV5_1 = 1, /* Rev BA, CA */
    ALPHA_EV5_2 = 2, /* Rev DA, EA */
    ALPHA_EV5_3 = 3, /* Pass 3 */
    ALPHA_EV5_4 = 4, /* Pass 3.2 */
    ALPHA_EV5_5 = 5, /* Pass 4 */
};

/* EV45 minor type */
enum {
    ALPHA_EV45_1 = 1, /* Pass 1 */
    ALPHA_EV45_2 = 2, /* Pass 1.1 */
    ALPHA_EV45_3 = 3, /* Pass 2 */
};

/* EV56 minor type */
enum {
    ALPHA_EV56_1 = 1, /* Pass 1 */
    ALPHA_EV56_2 = 2, /* Pass 2 */
};

enum {
    IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
    IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
    IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
    IMPLVER_21364 = 3, /* EV7 & EV79 */
};

enum {
    AMASK_BWX      = 0x00000001,
    AMASK_FIX      = 0x00000002,
    AMASK_CIX      = 0x00000004,
    AMASK_MVI      = 0x00000100,
    AMASK_TRAP     = 0x00000200,
    AMASK_PREFETCH = 0x00001000,
};

enum {
    VAX_ROUND_NORMAL = 0,
    VAX_ROUND_CHOPPED,
};

enum {
    IEEE_ROUND_NORMAL = 0,
    IEEE_ROUND_DYNAMIC,
    IEEE_ROUND_PLUS,
    IEEE_ROUND_MINUS,
    IEEE_ROUND_CHOPPED,
};

/* IEEE floating-point operations encoding */
/* Trap mode */
enum {
    FP_TRAP_I   = 0x0,
    FP_TRAP_U   = 0x1,
    FP_TRAP_S  = 0x4,
    FP_TRAP_SU  = 0x5,
    FP_TRAP_SUI = 0x7,
};

/* Rounding mode */
enum {
    FP_ROUND_CHOPPED = 0x0,
    FP_ROUND_MINUS   = 0x1,
    FP_ROUND_NORMAL  = 0x2,
    FP_ROUND_DYNAMIC = 0x3,
};

/* FPCR bits */
#define FPCR_SUM		(1ULL << 63)
#define FPCR_INED		(1ULL << 62)
#define FPCR_UNFD		(1ULL << 61)
#define FPCR_UNDZ		(1ULL << 60)
#define FPCR_DYN_SHIFT		58
#define FPCR_DYN_CHOPPED	(0ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_MINUS		(1ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_NORMAL		(2ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_PLUS		(3ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_MASK		(3ULL << FPCR_DYN_SHIFT)
#define FPCR_IOV		(1ULL << 57)
#define FPCR_INE		(1ULL << 56)
#define FPCR_UNF		(1ULL << 55)
#define FPCR_OVF		(1ULL << 54)
#define FPCR_DZE		(1ULL << 53)
#define FPCR_INV		(1ULL << 52)
#define FPCR_OVFD		(1ULL << 51)
#define FPCR_DZED		(1ULL << 50)
#define FPCR_INVD		(1ULL << 49)
#define FPCR_DNZ		(1ULL << 48)
#define FPCR_DNOD		(1ULL << 47)
#define FPCR_STATUS_MASK	(FPCR_IOV | FPCR_INE | FPCR_UNF \
				 | FPCR_OVF | FPCR_DZE | FPCR_INV)

/* The silly software trap enables implemented by the kernel emulation.
   These are more or less architecturally required, since the real hardware
   has read-as-zero bits in the FPCR when the features aren't implemented.
   For the purposes of QEMU, we pretend the FPCR can hold everything.  */
#define SWCR_TRAP_ENABLE_INV	(1ULL << 1)
#define SWCR_TRAP_ENABLE_DZE	(1ULL << 2)
#define SWCR_TRAP_ENABLE_OVF	(1ULL << 3)
#define SWCR_TRAP_ENABLE_UNF	(1ULL << 4)
#define SWCR_TRAP_ENABLE_INE	(1ULL << 5)
#define SWCR_TRAP_ENABLE_DNO	(1ULL << 6)
#define SWCR_TRAP_ENABLE_MASK	((1ULL << 7) - (1ULL << 1))

#define SWCR_MAP_DMZ		(1ULL << 12)
#define SWCR_MAP_UMZ		(1ULL << 13)
#define SWCR_MAP_MASK		(SWCR_MAP_DMZ | SWCR_MAP_UMZ)

#define SWCR_STATUS_INV		(1ULL << 17)
#define SWCR_STATUS_DZE		(1ULL << 18)
#define SWCR_STATUS_OVF		(1ULL << 19)
#define SWCR_STATUS_UNF		(1ULL << 20)
#define SWCR_STATUS_INE		(1ULL << 21)
#define SWCR_STATUS_DNO		(1ULL << 22)
#define SWCR_STATUS_MASK	((1ULL << 23) - (1ULL << 17))

#define SWCR_MASK  (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)

/* MMU modes definitions */

/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
   The Unix PALcode only exposes the kernel and user modes; presumably
   executive and supervisor are used by VMS.

   PALcode itself uses physical mode for code and kernel mode for data;
   there are PALmode instructions that can access data via physical mode
   or via an os-installed "alternate mode", which is one of the 4 above.

   QEMU does not currently properly distinguish between code/data when
   looking up addresses.  To avoid having to address this issue, our
   emulated PALcode will cheat and use the KSEG mapping for its code+data
   rather than physical addresses.

   Moreover, we're only emulating Unix PALcode, and not attempting VMS.

   All of which allows us to drop all but kernel and user modes.
   Elide the unused MMU modes to save space.  */

#define NB_MMU_MODES 2

#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_KERNEL_IDX   0
#define MMU_USER_IDX     1

typedef struct CPUAlphaState CPUAlphaState;

struct CPUAlphaState {
    uint64_t ir[31];
    float64 fir[31];
    uint64_t pc;
    uint64_t unique;
    uint64_t lock_addr;
    uint64_t lock_st_addr;
    uint64_t lock_value;
    float_status fp_status;
    /* The following fields make up the FPCR, but in FP_STATUS format.  */
    uint8_t fpcr_exc_status;
    uint8_t fpcr_exc_mask;
    uint8_t fpcr_dyn_round;
    uint8_t fpcr_flush_to_zero;
    uint8_t fpcr_dnod;
    uint8_t fpcr_undz;

    /* The Internal Processor Registers.  Some of these we assume always
       exist for use in user-mode.  */
    uint8_t ps;
    uint8_t intr_flag;
    uint8_t pal_mode;
    uint8_t fen;

    uint32_t pcc_ofs;

    /* These pass data from the exception logic in the translator and
       helpers to the OS entry point.  This is used for both system
       emulation and user-mode.  */
    uint64_t trap_arg0;
    uint64_t trap_arg1;
    uint64_t trap_arg2;

#if !defined(CONFIG_USER_ONLY)
    /* The internal data required by our emulation of the Unix PALcode.  */
    uint64_t exc_addr;
    uint64_t palbr;
    uint64_t ptbr;
    uint64_t vptptr;
    uint64_t sysval;
    uint64_t usp;
    uint64_t shadow[8];
    uint64_t scratch[24];
#endif

    /* This alarm doesn't exist in real hardware; we wish it did.  */
    struct QEMUTimer *alarm_timer;
    uint64_t alarm_expire;

    /* Those resources are used only in QEMU core */
    CPU_COMMON

    int error_code;

    uint32_t features;
    uint32_t amask;
    int implver;
};

#define cpu_init cpu_alpha_init
#define cpu_exec cpu_alpha_exec
#define cpu_gen_code cpu_alpha_gen_code
#define cpu_signal_handler cpu_alpha_signal_handler

#include "cpu-all.h"
#include "cpu-qom.h"

enum {
    FEATURE_ASN    = 0x00000001,
    FEATURE_SPS    = 0x00000002,
    FEATURE_VIRBND = 0x00000004,
    FEATURE_TBCHK  = 0x00000008,
};

enum {
    EXCP_RESET,
    EXCP_MCHK,
    EXCP_SMP_INTERRUPT,
    EXCP_CLK_INTERRUPT,
    EXCP_DEV_INTERRUPT,
    EXCP_MMFAULT,
    EXCP_UNALIGN,
    EXCP_OPCDEC,
    EXCP_ARITH,
    EXCP_FEN,
    EXCP_CALL_PAL,
    /* For Usermode emulation.  */
    EXCP_STL_C,
    EXCP_STQ_C,
};

/* Alpha-specific interrupt pending bits.  */
#define CPU_INTERRUPT_TIMER	CPU_INTERRUPT_TGT_EXT_0
#define CPU_INTERRUPT_SMP	CPU_INTERRUPT_TGT_EXT_1
#define CPU_INTERRUPT_MCHK	CPU_INTERRUPT_TGT_EXT_2

/* OSF/1 Page table bits.  */
enum {
    PTE_VALID = 0x0001,
    PTE_FOR   = 0x0002,  /* used for page protection (fault on read) */
    PTE_FOW   = 0x0004,  /* used for page protection (fault on write) */
    PTE_FOE   = 0x0008,  /* used for page protection (fault on exec) */
    PTE_ASM   = 0x0010,
    PTE_KRE   = 0x0100,
    PTE_URE   = 0x0200,
    PTE_KWE   = 0x1000,
    PTE_UWE   = 0x2000
};

/* Hardware interrupt (entInt) constants.  */
enum {
    INT_K_IP,
    INT_K_CLK,
    INT_K_MCHK,
    INT_K_DEV,
    INT_K_PERF,
};

/* Memory management (entMM) constants.  */
enum {
    MM_K_TNV,
    MM_K_ACV,
    MM_K_FOR,
    MM_K_FOE,
    MM_K_FOW
};

/* Arithmetic exception (entArith) constants.  */
enum {
    EXC_M_SWC = 1,      /* Software completion */
    EXC_M_INV = 2,      /* Invalid operation */
    EXC_M_DZE = 4,      /* Division by zero */
    EXC_M_FOV = 8,      /* Overflow */
    EXC_M_UNF = 16,     /* Underflow */
    EXC_M_INE = 32,     /* Inexact result */
    EXC_M_IOV = 64      /* Integer Overflow */
};

/* Processor status constants.  */
enum {
    /* Low 3 bits are interrupt mask level.  */
    PS_INT_MASK = 7,

    /* Bits 4 and 5 are the mmu mode.  The VMS PALcode uses all 4 modes;
       The Unix PALcode only uses bit 4.  */
    PS_USER_MODE = 8
};

static inline int cpu_mmu_index(CPUAlphaState *env)
{
    if (env->pal_mode) {
        return MMU_KERNEL_IDX;
    } else if (env->ps & PS_USER_MODE) {
        return MMU_USER_IDX;
    } else {
        return MMU_KERNEL_IDX;
    }
}

enum {
    IR_V0   = 0,
    IR_T0   = 1,
    IR_T1   = 2,
    IR_T2   = 3,
    IR_T3   = 4,
    IR_T4   = 5,
    IR_T5   = 6,
    IR_T6   = 7,
    IR_T7   = 8,
    IR_S0   = 9,
    IR_S1   = 10,
    IR_S2   = 11,
    IR_S3   = 12,
    IR_S4   = 13,
    IR_S5   = 14,
    IR_S6   = 15,
    IR_FP   = IR_S6,
    IR_A0   = 16,
    IR_A1   = 17,
    IR_A2   = 18,
    IR_A3   = 19,
    IR_A4   = 20,
    IR_A5   = 21,
    IR_T8   = 22,
    IR_T9   = 23,
    IR_T10  = 24,
    IR_T11  = 25,
    IR_RA   = 26,
    IR_T12  = 27,
    IR_PV   = IR_T12,
    IR_AT   = 28,
    IR_GP   = 29,
    IR_SP   = 30,
    IR_ZERO = 31,
};

CPUAlphaState * cpu_alpha_init (const char *cpu_model);
int cpu_alpha_exec(CPUAlphaState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_alpha_signal_handler(int host_signum, void *pinfo,
                             void *puc);
int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw,
                                int mmu_idx);
#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
void do_interrupt (CPUAlphaState *env);
void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);

uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
#ifndef CONFIG_USER_ONLY
void swap_shadow_regs(CPUAlphaState *env);
QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1,
                                         hwaddr addr, int is_write,
                                         int is_exec, int unused, int size);
#endif

/* Bits in TB->FLAGS that control how translation is processed.  */
enum {
    TB_FLAGS_PAL_MODE = 1,
    TB_FLAGS_FEN = 2,
    TB_FLAGS_USER_MODE = 8,

    TB_FLAGS_AMASK_SHIFT = 4,
    TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
};

static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *pflags)
{
    int flags = 0;

    *pc = env->pc;
    *cs_base = 0;

    if (env->pal_mode) {
        flags = TB_FLAGS_PAL_MODE;
    } else {
        flags = env->ps & PS_USER_MODE;
    }
    if (env->fen) {
        flags |= TB_FLAGS_FEN;
    }
    flags |= env->amask << TB_FLAGS_AMASK_SHIFT;

    *pflags = flags;
}

#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUAlphaState *env, target_ulong newsp)
{
    if (newsp) {
        env->ir[IR_SP] = newsp;
    }
    env->ir[IR_V0] = 0;
    env->ir[IR_A3] = 0;
}

static inline void cpu_set_tls(CPUAlphaState *env, target_ulong newtls)
{
    env->unique = newtls;
}
#endif

static inline bool cpu_has_work(CPUState *cpu)
{
    CPUAlphaState *env = &ALPHA_CPU(cpu)->env;

    /* Here we are checking to see if the CPU should wake up from HALT.
       We will have gotten into this state only for WTINT from PALmode.  */
    /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
       asleep even if (some) interrupts have been asserted.  For now,
       assume that if a CPU really wants to stay asleep, it will mask
       interrupts at the chipset level, which will prevent these bits
       from being set in the first place.  */
    return env->interrupt_request & (CPU_INTERRUPT_HARD
                                     | CPU_INTERRUPT_TIMER
                                     | CPU_INTERRUPT_SMP
                                     | CPU_INTERRUPT_MCHK);
}

#include "exec-all.h"

static inline void cpu_pc_from_tb(CPUAlphaState *env, TranslationBlock *tb)
{
    env->pc = tb->pc;
}

#endif /* !defined (__CPU_ALPHA_H__) */
Commit	Line	Data
4c9649a9 JM	1	/*
4c9649a9 JM	2	* Alpha emulation cpu definitions for qemu.
5fafdf24	3	*
4c9649a9 JM	4	* Copyright (c) 2007 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4c9649a9 JM	18	*/
	19
	20	#if !defined (__CPU_ALPHA_H__)
	21	#define __CPU_ALPHA_H__
	22
	23	#include "config.h"
2c976297	24	#include "qemu-common.h"
4c9649a9 JM	25
	26	#define TARGET_LONG_BITS 64
	27
9349b4f9	28	#define CPUArchState struct CPUAlphaState
c2764719	29
4c9649a9 JM	30	#include "cpu-defs.h"
4c9649a9 JM	31
4c9649a9 JM	32	#include "softfloat.h"
4c9649a9 JM	33
4c9649a9 JM	34	#define TARGET_HAS_ICE 1
4c9649a9 JM	35
f071b4d3	36	#define ELF_MACHINE EM_ALPHA
4c9649a9 JM	37
	38	#define ICACHE_LINE_SIZE 32
	39	#define DCACHE_LINE_SIZE 32
	40
b09d9d46	41	#define TARGET_PAGE_BITS 13
4c9649a9	42
76393642 RH	43	#ifdef CONFIG_USER_ONLY
	44	/* ??? The kernel likes to give addresses in high memory. If the host has
	45	more virtual address space than the guest, this can lead to impossible
	46	allocations. Honor the long-standing assumption that only kernel addrs
	47	are negative, but otherwise allow allocations anywhere. This could lead
	48	to tricky emulation problems for programs doing tagged addressing, but
	49	that's far fewer than encounter the impossible allocation problem. */
	50	#define TARGET_PHYS_ADDR_SPACE_BITS 63
	51	#define TARGET_VIRT_ADDR_SPACE_BITS 63
	52	#else
52705890	53	/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
76393642 RH	54	#define TARGET_PHYS_ADDR_SPACE_BITS 44
	55	#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
	56	#endif
4c9649a9 JM	57
	58	/* Alpha major type */
	59	enum {
	60	ALPHA_EV3 = 1,
	61	ALPHA_EV4 = 2,
	62	ALPHA_SIM = 3,
	63	ALPHA_LCA = 4,
	64	ALPHA_EV5 = 5, /* 21164 */
	65	ALPHA_EV45 = 6, /* 21064A */
	66	ALPHA_EV56 = 7, /* 21164A */
	67	};
	68
	69	/* EV4 minor type */
	70	enum {
	71	ALPHA_EV4_2 = 0,
	72	ALPHA_EV4_3 = 1,
	73	};
	74
	75	/* LCA minor type */
	76	enum {
	77	ALPHA_LCA_1 = 1, /* 21066 */
	78	ALPHA_LCA_2 = 2, /* 20166 */
	79	ALPHA_LCA_3 = 3, /* 21068 */
	80	ALPHA_LCA_4 = 4, /* 21068 */
	81	ALPHA_LCA_5 = 5, /* 21066A */
	82	ALPHA_LCA_6 = 6, /* 21068A */
	83	};
	84
	85	/* EV5 minor type */
	86	enum {
	87	ALPHA_EV5_1 = 1, /* Rev BA, CA */
	88	ALPHA_EV5_2 = 2, /* Rev DA, EA */
	89	ALPHA_EV5_3 = 3, /* Pass 3 */
	90	ALPHA_EV5_4 = 4, /* Pass 3.2 */
	91	ALPHA_EV5_5 = 5, /* Pass 4 */
	92	};
	93
	94	/* EV45 minor type */
	95	enum {
	96	ALPHA_EV45_1 = 1, /* Pass 1 */
	97	ALPHA_EV45_2 = 2, /* Pass 1.1 */
	98	ALPHA_EV45_3 = 3, /* Pass 2 */
	99	};
	100
	101	/* EV56 minor type */
	102	enum {
	103	ALPHA_EV56_1 = 1, /* Pass 1 */
	104	ALPHA_EV56_2 = 2, /* Pass 2 */
	105	};
	106
	107	enum {
	108	IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
	109	IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
	110	IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
	111	IMPLVER_21364 = 3, /* EV7 & EV79 */
	112	};
	113
	114	enum {
	115	AMASK_BWX = 0x00000001,
	116	AMASK_FIX = 0x00000002,
	117	AMASK_CIX = 0x00000004,
	118	AMASK_MVI = 0x00000100,
	119	AMASK_TRAP = 0x00000200,
	120	AMASK_PREFETCH = 0x00001000,
121	};
122
123	enum {
124	VAX_ROUND_NORMAL = 0,
125	VAX_ROUND_CHOPPED,
126	};
127
128	enum {
129	IEEE_ROUND_NORMAL = 0,
130	IEEE_ROUND_DYNAMIC,
131	IEEE_ROUND_PLUS,
132	IEEE_ROUND_MINUS,
133	IEEE_ROUND_CHOPPED,
134	};
135
136	/* IEEE floating-point operations encoding */
137	/* Trap mode */
138	enum {
139	FP_TRAP_I = 0x0,
140	FP_TRAP_U = 0x1,
141	FP_TRAP_S = 0x4,
142	FP_TRAP_SU = 0x5,
143	FP_TRAP_SUI = 0x7,
144	};
145
146	/* Rounding mode */
147	enum {
148	FP_ROUND_CHOPPED = 0x0,
149	FP_ROUND_MINUS = 0x1,
150	FP_ROUND_NORMAL = 0x2,
151	FP_ROUND_DYNAMIC = 0x3,
152	};
153
ba0e276d RH	154	/* FPCR bits */
	155	#define FPCR_SUM (1ULL << 63)
	156	#define FPCR_INED (1ULL << 62)
	157	#define FPCR_UNFD (1ULL << 61)
	158	#define FPCR_UNDZ (1ULL << 60)
	159	#define FPCR_DYN_SHIFT 58
8443effb RH	160	#define FPCR_DYN_CHOPPED (0ULL << FPCR_DYN_SHIFT)
	161	#define FPCR_DYN_MINUS (1ULL << FPCR_DYN_SHIFT)
	162	#define FPCR_DYN_NORMAL (2ULL << FPCR_DYN_SHIFT)
	163	#define FPCR_DYN_PLUS (3ULL << FPCR_DYN_SHIFT)
ba0e276d RH	164	#define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT)
	165	#define FPCR_IOV (1ULL << 57)
	166	#define FPCR_INE (1ULL << 56)
	167	#define FPCR_UNF (1ULL << 55)
	168	#define FPCR_OVF (1ULL << 54)
	169	#define FPCR_DZE (1ULL << 53)
	170	#define FPCR_INV (1ULL << 52)
	171	#define FPCR_OVFD (1ULL << 51)
	172	#define FPCR_DZED (1ULL << 50)
	173	#define FPCR_INVD (1ULL << 49)
	174	#define FPCR_DNZ (1ULL << 48)
	175	#define FPCR_DNOD (1ULL << 47)
	176	#define FPCR_STATUS_MASK (FPCR_IOV \| FPCR_INE \| FPCR_UNF \
	177	\| FPCR_OVF \| FPCR_DZE \| FPCR_INV)
	178
	179	/* The silly software trap enables implemented by the kernel emulation.
	180	These are more or less architecturally required, since the real hardware
	181	has read-as-zero bits in the FPCR when the features aren't implemented.
	182	For the purposes of QEMU, we pretend the FPCR can hold everything. */
	183	#define SWCR_TRAP_ENABLE_INV (1ULL << 1)
	184	#define SWCR_TRAP_ENABLE_DZE (1ULL << 2)
	185	#define SWCR_TRAP_ENABLE_OVF (1ULL << 3)
	186	#define SWCR_TRAP_ENABLE_UNF (1ULL << 4)
	187	#define SWCR_TRAP_ENABLE_INE (1ULL << 5)
	188	#define SWCR_TRAP_ENABLE_DNO (1ULL << 6)
	189	#define SWCR_TRAP_ENABLE_MASK ((1ULL << 7) - (1ULL << 1))
	190
	191	#define SWCR_MAP_DMZ (1ULL << 12)
	192	#define SWCR_MAP_UMZ (1ULL << 13)
	193	#define SWCR_MAP_MASK (SWCR_MAP_DMZ \| SWCR_MAP_UMZ)
	194
	195	#define SWCR_STATUS_INV (1ULL << 17)
	196	#define SWCR_STATUS_DZE (1ULL << 18)
	197	#define SWCR_STATUS_OVF (1ULL << 19)
	198	#define SWCR_STATUS_UNF (1ULL << 20)
	199	#define SWCR_STATUS_INE (1ULL << 21)
	200	#define SWCR_STATUS_DNO (1ULL << 22)
	201	#define SWCR_STATUS_MASK ((1ULL << 23) - (1ULL << 17))
	202
	203	#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK \| SWCR_MAP_MASK \| SWCR_STATUS_MASK)
	204
8417845e RH	205	/* MMU modes definitions */
	206
	207	/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
	208	The Unix PALcode only exposes the kernel and user modes; presumably
	209	executive and supervisor are used by VMS.
	210
	211	PALcode itself uses physical mode for code and kernel mode for data;
	212	there are PALmode instructions that can access data via physical mode
	213	or via an os-installed "alternate mode", which is one of the 4 above.
	214
	215	QEMU does not currently properly distinguish between code/data when
	216	looking up addresses. To avoid having to address this issue, our
	217	emulated PALcode will cheat and use the KSEG mapping for its code+data
	218	rather than physical addresses.
	219
	220	Moreover, we're only emulating Unix PALcode, and not attempting VMS.
	221
	222	All of which allows us to drop all but kernel and user modes.
	223	Elide the unused MMU modes to save space. */
4c9649a9	224
8417845e RH	225	#define NB_MMU_MODES 2
	226
	227	#define MMU_MODE0_SUFFIX _kernel
	228	#define MMU_MODE1_SUFFIX _user
	229	#define MMU_KERNEL_IDX 0
	230	#define MMU_USER_IDX 1
	231
	232	typedef struct CPUAlphaState CPUAlphaState;
6ebbf390	233
4c9649a9 JM	234	struct CPUAlphaState {
4c9649a9 JM	235	uint64_t ir[31];
8443effb	236	float64 fir[31];
4c9649a9	237	uint64_t pc;
4c9649a9	238	uint64_t unique;
6910b8f6 RH	239	uint64_t lock_addr;
	240	uint64_t lock_st_addr;
	241	uint64_t lock_value;
8443effb RH	242	float_status fp_status;
	243	/* The following fields make up the FPCR, but in FP_STATUS format. */
	244	uint8_t fpcr_exc_status;
	245	uint8_t fpcr_exc_mask;
	246	uint8_t fpcr_dyn_round;
	247	uint8_t fpcr_flush_to_zero;
8443effb RH	248	uint8_t fpcr_dnod;
	249	uint8_t fpcr_undz;
	250
129d8aa5 RH	251	/* The Internal Processor Registers. Some of these we assume always
	252	exist for use in user-mode. */
	253	uint8_t ps;
8443effb	254	uint8_t intr_flag;
129d8aa5	255	uint8_t pal_mode;
26b46094 RH	256	uint8_t fen;
	257
	258	uint32_t pcc_ofs;
129d8aa5 RH	259
	260	/* These pass data from the exception logic in the translator and
	261	helpers to the OS entry point. This is used for both system
	262	emulation and user-mode. */
	263	uint64_t trap_arg0;
	264	uint64_t trap_arg1;
	265	uint64_t trap_arg2;
4c9649a9	266
26b46094 RH	267	#if !defined(CONFIG_USER_ONLY)
	268	/* The internal data required by our emulation of the Unix PALcode. */
	269	uint64_t exc_addr;
	270	uint64_t palbr;
	271	uint64_t ptbr;
	272	uint64_t vptptr;
	273	uint64_t sysval;
	274	uint64_t usp;
	275	uint64_t shadow[8];
	276	uint64_t scratch[24];
	277	#endif
	278
c781cf96 RH	279	/* This alarm doesn't exist in real hardware; we wish it did. */
	280	struct QEMUTimer *alarm_timer;
	281	uint64_t alarm_expire;
	282
5cbdb3a3	283	/* Those resources are used only in QEMU core */
4c9649a9 JM	284	CPU_COMMON
4c9649a9 JM	285
4c9649a9	286	int error_code;
4c9649a9 JM	287
	288	uint32_t features;
	289	uint32_t amask;
	290	int implver;
4c9649a9 JM	291	};
4c9649a9 JM	292
9467d44c TS	293	#define cpu_init cpu_alpha_init
	294	#define cpu_exec cpu_alpha_exec
	295	#define cpu_gen_code cpu_alpha_gen_code
	296	#define cpu_signal_handler cpu_alpha_signal_handler
	297
4c9649a9	298	#include "cpu-all.h"
25ebd80f	299	#include "cpu-qom.h"
4c9649a9 JM	300
	301	enum {
	302	FEATURE_ASN = 0x00000001,
	303	FEATURE_SPS = 0x00000002,
	304	FEATURE_VIRBND = 0x00000004,
	305	FEATURE_TBCHK = 0x00000008,
	306	};
	307
	308	enum {
07b6c13b RH	309	EXCP_RESET,
	310	EXCP_MCHK,
	311	EXCP_SMP_INTERRUPT,
	312	EXCP_CLK_INTERRUPT,
	313	EXCP_DEV_INTERRUPT,
	314	EXCP_MMFAULT,
	315	EXCP_UNALIGN,
	316	EXCP_OPCDEC,
	317	EXCP_ARITH,
	318	EXCP_FEN,
	319	EXCP_CALL_PAL,
	320	/* For Usermode emulation. */
	321	EXCP_STL_C,
	322	EXCP_STQ_C,
4c9649a9 JM	323	};
4c9649a9 JM	324
6a80e088 RH	325	/* Alpha-specific interrupt pending bits. */
	326	#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0
	327	#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
	328	#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
	329
a3b9af16 RH	330	/* OSF/1 Page table bits. */
	331	enum {
	332	PTE_VALID = 0x0001,
	333	PTE_FOR = 0x0002, /* used for page protection (fault on read) */
	334	PTE_FOW = 0x0004, /* used for page protection (fault on write) */
	335	PTE_FOE = 0x0008, /* used for page protection (fault on exec) */
	336	PTE_ASM = 0x0010,
	337	PTE_KRE = 0x0100,
	338	PTE_URE = 0x0200,
	339	PTE_KWE = 0x1000,
	340	PTE_UWE = 0x2000
	341	};
	342
ea879fc7 RH	343	/* Hardware interrupt (entInt) constants. */
	344	enum {
	345	INT_K_IP,
	346	INT_K_CLK,
	347	INT_K_MCHK,
	348	INT_K_DEV,
	349	INT_K_PERF,
	350	};
	351
	352	/* Memory management (entMM) constants. */
	353	enum {
	354	MM_K_TNV,
	355	MM_K_ACV,
	356	MM_K_FOR,
	357	MM_K_FOE,
	358	MM_K_FOW
	359	};
	360
	361	/* Arithmetic exception (entArith) constants. */
	362	enum {
	363	EXC_M_SWC = 1, /* Software completion */
	364	EXC_M_INV = 2, /* Invalid operation */
	365	EXC_M_DZE = 4, /* Division by zero */
	366	EXC_M_FOV = 8, /* Overflow */
	367	EXC_M_UNF = 16, /* Underflow */
	368	EXC_M_INE = 32, /* Inexact result */
	369	EXC_M_IOV = 64 /* Integer Overflow */
	370	};
	371
	372	/* Processor status constants. */
	373	enum {
	374	/* Low 3 bits are interrupt mask level. */
	375	PS_INT_MASK = 7,
	376
	377	/* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
	378	The Unix PALcode only uses bit 4. */
	379	PS_USER_MODE = 8
	380	};
	381
4d5712f1	382	static inline int cpu_mmu_index(CPUAlphaState *env)
ea879fc7	383	{
bba9bdce RH	384	if (env->pal_mode) {
	385	return MMU_KERNEL_IDX;
	386	} else if (env->ps & PS_USER_MODE) {
	387	return MMU_USER_IDX;
	388	} else {
	389	return MMU_KERNEL_IDX;
	390	}
ea879fc7	391	}
4c9649a9	392
4c9649a9 JM	393	enum {
	394	IR_V0 = 0,
	395	IR_T0 = 1,
	396	IR_T1 = 2,
	397	IR_T2 = 3,
	398	IR_T3 = 4,
	399	IR_T4 = 5,
	400	IR_T5 = 6,
	401	IR_T6 = 7,
	402	IR_T7 = 8,
	403	IR_S0 = 9,
	404	IR_S1 = 10,
	405	IR_S2 = 11,
	406	IR_S3 = 12,
	407	IR_S4 = 13,
	408	IR_S5 = 14,
	409	IR_S6 = 15,
a4b388ff	410	IR_FP = IR_S6,
4c9649a9 JM	411	IR_A0 = 16,
	412	IR_A1 = 17,
	413	IR_A2 = 18,
	414	IR_A3 = 19,
	415	IR_A4 = 20,
	416	IR_A5 = 21,
	417	IR_T8 = 22,
	418	IR_T9 = 23,
	419	IR_T10 = 24,
	420	IR_T11 = 25,
	421	IR_RA = 26,
	422	IR_T12 = 27,
a4b388ff	423	IR_PV = IR_T12,
4c9649a9 JM	424	IR_AT = 28,
	425	IR_GP = 29,
	426	IR_SP = 30,
	427	IR_ZERO = 31,
	428	};
	429
aaed909a	430	CPUAlphaState * cpu_alpha_init (const char *cpu_model);
e96efcfc JM	431	int cpu_alpha_exec(CPUAlphaState *s);
	432	/* you can call this signal handler from your SIGBUS and SIGSEGV
	433	signal handlers to inform the virtual CPU of exceptions. non zero
	434	is returned if the signal was handled by the virtual CPU. */
5fafdf24	435	int cpu_alpha_signal_handler(int host_signum, void *pinfo,
e96efcfc	436	void *puc);
4d5712f1	437	int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw,
97b348e7	438	int mmu_idx);
0b5c1ce8	439	#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
4d5712f1	440	void do_interrupt (CPUAlphaState *env);
20503968 BS	441	void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
	442	void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
	443	void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
95870356	444
4d5712f1 AF	445	uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
4d5712f1 AF	446	void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
5b450407	447	#ifndef CONFIG_USER_ONLY
4d5712f1 AF	448	void swap_shadow_regs(CPUAlphaState *env);
4d5712f1 AF	449	QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1,
a8170e5e	450	hwaddr addr, int is_write,
b14ef7c9	451	int is_exec, int unused, int size);
5b450407	452	#endif
4c9649a9	453
a18ad893 RH	454	/* Bits in TB->FLAGS that control how translation is processed. */
	455	enum {
	456	TB_FLAGS_PAL_MODE = 1,
	457	TB_FLAGS_FEN = 2,
	458	TB_FLAGS_USER_MODE = 8,
	459
	460	TB_FLAGS_AMASK_SHIFT = 4,
	461	TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT,
	462	TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT,
	463	TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT,
	464	TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT,
	465	TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT,
	466	TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
	467	};
	468
4d5712f1	469	static inline void cpu_get_tb_cpu_state(CPUAlphaState env, target_ulong pc,
a18ad893	470	target_ulong cs_base, int pflags)
6b917547	471	{
a18ad893 RH	472	int flags = 0;
a18ad893 RH	473
6b917547 AL	474	*pc = env->pc;
6b917547 AL	475	*cs_base = 0;
a18ad893 RH	476
	477	if (env->pal_mode) {
	478	flags = TB_FLAGS_PAL_MODE;
	479	} else {
	480	flags = env->ps & PS_USER_MODE;
	481	}
	482	if (env->fen) {
	483	flags \|= TB_FLAGS_FEN;
	484	}
	485	flags \|= env->amask << TB_FLAGS_AMASK_SHIFT;
	486
	487	*pflags = flags;
6b917547 AL	488	}
6b917547 AL	489
a4b388ff	490	#if defined(CONFIG_USER_ONLY)
4d5712f1	491	static inline void cpu_clone_regs(CPUAlphaState *env, target_ulong newsp)
a4b388ff RH	492	{
	493	if (newsp) {
	494	env->ir[IR_SP] = newsp;
	495	}
	496	env->ir[IR_V0] = 0;
	497	env->ir[IR_A3] = 0;
	498	}
	499
4d5712f1	500	static inline void cpu_set_tls(CPUAlphaState *env, target_ulong newtls)
a4b388ff RH	501	{
	502	env->unique = newtls;
	503	}
	504	#endif
	505
3993c6bd	506	static inline bool cpu_has_work(CPUState *cpu)
f081c76c	507	{
3993c6bd AF	508	CPUAlphaState *env = &ALPHA_CPU(cpu)->env;
3993c6bd AF	509
f081c76c BS	510	/* Here we are checking to see if the CPU should wake up from HALT.
	511	We will have gotten into this state only for WTINT from PALmode. */
	512	/* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
	513	asleep even if (some) interrupts have been asserted. For now,
	514	assume that if a CPU really wants to stay asleep, it will mask
	515	interrupts at the chipset level, which will prevent these bits
	516	from being set in the first place. */
	517	return env->interrupt_request & (CPU_INTERRUPT_HARD
	518	\| CPU_INTERRUPT_TIMER
	519	\| CPU_INTERRUPT_SMP
	520	\| CPU_INTERRUPT_MCHK);
	521	}
	522
	523	#include "exec-all.h"
	524
4d5712f1	525	static inline void cpu_pc_from_tb(CPUAlphaState env, TranslationBlock tb)
f081c76c BS	526	{
	527	env->pc = tb->pc;
	528	}
	529
4c9649a9	530	#endif /* !defined (__CPU_ALPHA_H__) */