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pc: acpi: create MADT.lapic entries only for valid lapics
[qemu.git] / hw / i386 / acpi-build.c
CommitLineData
72c194f7
MT		 1/* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <[email protected]>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <[email protected]>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
b6a0aa05 23#include "qemu/osdep.h"
72c194f7 24#include "acpi-build.h"
72c194f7
MT		 25#include <glib.h>
26#include "qemu-common.h"
27#include "qemu/bitmap.h"
07fb6176 28#include "qemu/error-report.h"
72c194f7
MT		 29#include "hw/pci/pci.h"
30#include "qom/cpu.h"
31#include "hw/i386/pc.h"
32#include "target-i386/cpu.h"
33#include "hw/timer/hpet.h"
395e5fb4 34#include "hw/acpi/acpi-defs.h"
72c194f7
MT		 35#include "hw/acpi/acpi.h"
36#include "hw/nvram/fw_cfg.h"
0058ae1d 37#include "hw/acpi/bios-linker-loader.h"
72c194f7 38#include "hw/loader.h"
15bce1b7 39#include "hw/isa/isa.h"
27b9fc54 40#include "hw/block/fdc.h"
bef3492d 41#include "hw/acpi/memory_hotplug.h"
711b20b4
SB		 42#include "sysemu/tpm.h"
43#include "hw/acpi/tpm.h"
5cb18b3d 44#include "sysemu/tpm_backend.h"
f070efa8 45#include "hw/timer/mc146818rtc_regs.h"
72c194f7
MT		 46
47/* Supported chipsets: */
48#include "hw/acpi/piix4.h"
99fd437d 49#include "hw/acpi/pcihp.h"
72c194f7
MT		 50#include "hw/i386/ich9.h"
51#include "hw/pci/pci_bus.h"
52#include "hw/pci-host/q35.h"
d4eb9119 53#include "hw/i386/intel_iommu.h"
a57d708d 54#include "hw/timer/hpet.h"
72c194f7 55
19934e0e
IM		 56#include "hw/acpi/aml-build.h"
57
72c194f7
MT		 58#include "qapi/qmp/qint.h"
59#include "qom/qom-qobject.h"
60
07fb6176
PB		 61/* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
62 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
63 * a little bit, there should be plenty of free space since the DSDT
64 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
65 */
66#define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
67#define ACPI_BUILD_ALIGN_SIZE 0x1000
68
868270f2 69#define ACPI_BUILD_TABLE_SIZE 0x20000
18045fb9 70
8b310fc4
GA		 71/* #define DEBUG_ACPI_BUILD */
72#ifdef DEBUG_ACPI_BUILD
73#define ACPI_BUILD_DPRINTF(fmt, ...) \
74 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
75#else
76#define ACPI_BUILD_DPRINTF(fmt, ...)
77#endif
78
72c194f7 79typedef struct AcpiCpuInfo {
798325ed 80 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
72c194f7
MT		 81} AcpiCpuInfo;
82
83typedef struct AcpiMcfgInfo {
84 uint64_t mcfg_base;
85 uint32_t mcfg_size;
86} AcpiMcfgInfo;
87
88typedef struct AcpiPmInfo {
89 bool s3_disabled;
90 bool s4_disabled;
133a2da4 91 bool pcihp_bridge_en;
72c194f7
MT		 92 uint8_t s4_val;
93 uint16_t sci_int;
94 uint8_t acpi_enable_cmd;
95 uint8_t acpi_disable_cmd;
96 uint32_t gpe0_blk;
97 uint32_t gpe0_blk_len;
98 uint32_t io_base;
ddf1ec2f
IM		 99 uint16_t cpu_hp_io_base;
100 uint16_t cpu_hp_io_len;
2c6b94d8
IM		 101 uint16_t mem_hp_io_base;
102 uint16_t mem_hp_io_len;
500b11ea
IM		 103 uint16_t pcihp_io_base;
104 uint16_t pcihp_io_len;
72c194f7
MT		 105} AcpiPmInfo;
106
107typedef struct AcpiMiscInfo {
e4db2798 108 bool is_piix4;
72c194f7 109 bool has_hpet;
5cb18b3d 110 TPMVersion tpm_version;
72c194f7
MT		 111 const unsigned char *dsdt_code;
112 unsigned dsdt_size;
113 uint16_t pvpanic_port;
8ac6f7a6 114 uint16_t applesmc_io_base;
72c194f7
MT		 115} AcpiMiscInfo;
116
99fd437d
MT		 117typedef struct AcpiBuildPciBusHotplugState {
118 GArray *device_table;
119 GArray *notify_table;
120 struct AcpiBuildPciBusHotplugState *parent;
133a2da4 121 bool pcihp_bridge_en;
99fd437d
MT		 122} AcpiBuildPciBusHotplugState;
123
72c194f7
MT		 124static
125int acpi_add_cpu_info(Object *o, void *opaque)
126{
127 AcpiCpuInfo *cpu = opaque;
128 uint64_t apic_id;
129
130 if (object_dynamic_cast(o, TYPE_CPU)) {
131 apic_id = object_property_get_int(o, "apic-id", NULL);
798325ed 132 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
72c194f7
MT		 133
134 set_bit(apic_id, cpu->found_cpus);
135 }
136
137 object_child_foreach(o, acpi_add_cpu_info, opaque);
138 return 0;
139}
140
141static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
142{
143 Object *root = object_get_root();
144
145 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
146 object_child_foreach(root, acpi_add_cpu_info, cpu);
147}
148
149static void acpi_get_pm_info(AcpiPmInfo *pm)
150{
151 Object *piix = piix4_pm_find();
152 Object *lpc = ich9_lpc_find();
153 Object *obj = NULL;
154 QObject *o;
155
94aaca64 156 pm->cpu_hp_io_base = 0;
500b11ea
IM		 157 pm->pcihp_io_base = 0;
158 pm->pcihp_io_len = 0;
72c194f7
MT		 159 if (piix) {
160 obj = piix;
ddf1ec2f 161 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
500b11ea
IM		 162 pm->pcihp_io_base =
163 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
164 pm->pcihp_io_len =
165 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
72c194f7
MT		 166 }
167 if (lpc) {
168 obj = lpc;
ddf1ec2f 169 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
72c194f7
MT		 170 }
171 assert(obj);
172
ddf1ec2f 173 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
2c6b94d8
IM		 174 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
175 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
176
72c194f7
MT		 177 /* Fill in optional s3/s4 related properties */
178 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
179 if (o) {
180 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
181 } else {
182 pm->s3_disabled = false;
183 }
097a97a6 184 qobject_decref(o);
72c194f7
MT		 185 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
186 if (o) {
187 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
188 } else {
189 pm->s4_disabled = false;
190 }
097a97a6 191 qobject_decref(o);
72c194f7
MT		 192 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
193 if (o) {
194 pm->s4_val = qint_get_int(qobject_to_qint(o));
195 } else {
196 pm->s4_val = false;
197 }
097a97a6 198 qobject_decref(o);
72c194f7
MT		 199
200 /* Fill in mandatory properties */
201 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
202
203 pm->acpi_enable_cmd = object_property_get_int(obj,
204 ACPI_PM_PROP_ACPI_ENABLE_CMD,
205 NULL);
206 pm->acpi_disable_cmd = object_property_get_int(obj,
207 ACPI_PM_PROP_ACPI_DISABLE_CMD,
208 NULL);
209 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
210 NULL);
211 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
212 NULL);
213 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
214 NULL);
133a2da4
IM		 215 pm->pcihp_bridge_en =
216 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
217 NULL);
72c194f7
MT		 218}
219
72c194f7
MT		 220static void acpi_get_misc_info(AcpiMiscInfo *info)
221{
3db119da
IM		 222 Object *piix = piix4_pm_find();
223 Object *lpc = ich9_lpc_find();
224 assert(!!piix != !!lpc);
225
226 if (piix) {
227 info->is_piix4 = true;
228 }
229 if (lpc) {
230 info->is_piix4 = false;
231 }
232
72c194f7 233 info->has_hpet = hpet_find();
5cb18b3d 234 info->tpm_version = tpm_get_version();
72c194f7 235 info->pvpanic_port = pvpanic_port();
8ac6f7a6 236 info->applesmc_io_base = applesmc_port();
72c194f7
MT		 237}
238
ca6c1855
MA		 239/*
240 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
241 * On i386 arch we only have two pci hosts, so we can look only for them.
242 */
243static Object *acpi_get_i386_pci_host(void)
244{
245 PCIHostState *host;
246
247 host = OBJECT_CHECK(PCIHostState,
248 object_resolve_path("/machine/i440fx", NULL),
249 TYPE_PCI_HOST_BRIDGE);
250 if (!host) {
251 host = OBJECT_CHECK(PCIHostState,
252 object_resolve_path("/machine/q35", NULL),
253 TYPE_PCI_HOST_BRIDGE);
254 }
255
256 return OBJECT(host);
257}
258
72c194f7
MT		 259static void acpi_get_pci_info(PcPciInfo *info)
260{
261 Object *pci_host;
72c194f7 262
ca6c1855
MA		 263
264 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 265 g_assert(pci_host);
266
267 info->w32.begin = object_property_get_int(pci_host,
268 PCI_HOST_PROP_PCI_HOLE_START,
269 NULL);
270 info->w32.end = object_property_get_int(pci_host,
271 PCI_HOST_PROP_PCI_HOLE_END,
272 NULL);
273 info->w64.begin = object_property_get_int(pci_host,
274 PCI_HOST_PROP_PCI_HOLE64_START,
275 NULL);
276 info->w64.end = object_property_get_int(pci_host,
277 PCI_HOST_PROP_PCI_HOLE64_END,
278 NULL);
279}
280
72c194f7
MT		 281#define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
282
72c194f7
MT		 283static void acpi_align_size(GArray *blob, unsigned align)
284{
285 /* Align size to multiple of given size. This reduces the chance
286 * we need to change size in the future (breaking cross version migration).
287 */
134d42d6 288 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
72c194f7
MT		 289}
290
72c194f7
MT		 291/* FACS */
292static void
fb306ffe 293build_facs(GArray *table_data, GArray *linker)
72c194f7
MT		 294{
295 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
821e3227 296 memcpy(&facs->signature, "FACS", 4);
72c194f7
MT		 297 facs->length = cpu_to_le32(sizeof(*facs));
298}
299
300/* Load chipset information in FADT */
301static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
302{
303 fadt->model = 1;
304 fadt->reserved1 = 0;
305 fadt->sci_int = cpu_to_le16(pm->sci_int);
306 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
307 fadt->acpi_enable = pm->acpi_enable_cmd;
308 fadt->acpi_disable = pm->acpi_disable_cmd;
309 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
310 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
311 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
312 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
313 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
314 /* EVT, CNT, TMR length matches hw/acpi/core.c */
315 fadt->pm1_evt_len = 4;
316 fadt->pm1_cnt_len = 2;
317 fadt->pm_tmr_len = 4;
318 fadt->gpe0_blk_len = pm->gpe0_blk_len;
319 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
320 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
321 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
322 (1 << ACPI_FADT_F_PROC_C1) |
323 (1 << ACPI_FADT_F_SLP_BUTTON) |
324 (1 << ACPI_FADT_F_RTC_S4));
325 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
07b81ed9
HZ		 326 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
327 * For more than 8 CPUs, "Clustered Logical" mode has to be used
328 */
329 if (max_cpus > 8) {
330 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
331 }
f070efa8 332 fadt->century = RTC_CENTURY;
72c194f7
MT		 333}
334
335
336/* FADT */
337static void
338build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
ae123749
LE		 339 unsigned facs, unsigned dsdt,
340 const char *oem_id, const char *oem_table_id)
72c194f7
MT		 341{
342 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
343
344 fadt->firmware_ctrl = cpu_to_le32(facs);
345 /* FACS address to be filled by Guest linker */
346 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
347 ACPI_BUILD_TABLE_FILE,
348 table_data, &fadt->firmware_ctrl,
349 sizeof fadt->firmware_ctrl);
350
351 fadt->dsdt = cpu_to_le32(dsdt);
352 /* DSDT address to be filled by Guest linker */
353 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
354 ACPI_BUILD_TABLE_FILE,
355 table_data, &fadt->dsdt,
356 sizeof fadt->dsdt);
357
358 fadt_setup(fadt, pm);
359
360 build_header(linker, table_data,
ae123749 361 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
72c194f7
MT		 362}
363
364static void
907e7c94 365build_madt(GArray *table_data, GArray *linker, PCMachineState *pcms)
72c194f7 366{
907e7c94
IM		 367 MachineClass *mc = MACHINE_GET_CLASS(pcms);
368 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
72c194f7
MT		 369 int madt_start = table_data->len;
370
371 AcpiMultipleApicTable *madt;
372 AcpiMadtIoApic *io_apic;
373 AcpiMadtIntsrcovr *intsrcovr;
374 AcpiMadtLocalNmi *local_nmi;
375 int i;
376
377 madt = acpi_data_push(table_data, sizeof *madt);
378 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
379 madt->flags = cpu_to_le32(1);
380
907e7c94 381 for (i = 0; i < apic_ids->len; i++) {
72c194f7 382 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
907e7c94
IM		 383 int apic_id = apic_ids->cpus[i].arch_id;
384
72c194f7
MT		 385 apic->type = ACPI_APIC_PROCESSOR;
386 apic->length = sizeof(*apic);
907e7c94
IM		 387 apic->processor_id = apic_id;
388 apic->local_apic_id = apic_id;
389 if (apic_ids->cpus[i].cpu != NULL) {
72c194f7
MT		 390 apic->flags = cpu_to_le32(1);
391 } else {
392 apic->flags = cpu_to_le32(0);
393 }
394 }
907e7c94
IM		 395 g_free(apic_ids);
396
72c194f7
MT		 397 io_apic = acpi_data_push(table_data, sizeof *io_apic);
398 io_apic->type = ACPI_APIC_IO;
399 io_apic->length = sizeof(*io_apic);
400#define ACPI_BUILD_IOAPIC_ID 0x0
401 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
402 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
403 io_apic->interrupt = cpu_to_le32(0);
404
dd4c2f01 405 if (pcms->apic_xrupt_override) {
72c194f7
MT		 406 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
407 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
408 intsrcovr->length = sizeof(*intsrcovr);
409 intsrcovr->source = 0;
410 intsrcovr->gsi = cpu_to_le32(2);
411 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
412 }
413 for (i = 1; i < 16; i++) {
414#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
415 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
416 /* No need for a INT source override structure. */
417 continue;
418 }
419 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
420 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
421 intsrcovr->length = sizeof(*intsrcovr);
422 intsrcovr->source = i;
423 intsrcovr->gsi = cpu_to_le32(i);
424 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
425 }
426
427 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
428 local_nmi->type = ACPI_APIC_LOCAL_NMI;
429 local_nmi->length = sizeof(*local_nmi);
430 local_nmi->processor_id = 0xff; /* all processors */
431 local_nmi->flags = cpu_to_le16(0);
432 local_nmi->lint = 1; /* ACPI_LINT1 */
433
434 build_header(linker, table_data,
821e3227 435 (void *)(table_data->data + madt_start), "APIC",
37ad223c 436 table_data->len - madt_start, 1, NULL, NULL);
72c194f7
MT		 437}
438
99fd437d
MT		 439/* Assign BSEL property to all buses. In the future, this can be changed
440 * to only assign to buses that support hotplug.
441 */
442static void *acpi_set_bsel(PCIBus *bus, void *opaque)
443{
444 unsigned *bsel_alloc = opaque;
445 unsigned *bus_bsel;
446
39b888bd 447 if (qbus_is_hotpluggable(BUS(bus))) {
99fd437d
MT		 448 bus_bsel = g_malloc(sizeof *bus_bsel);
449
450 *bus_bsel = (*bsel_alloc)++;
451 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
452 bus_bsel, NULL);
453 }
454
455 return bsel_alloc;
456}
457
458static void acpi_set_pci_info(void)
459{
460 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
461 unsigned bsel_alloc = 0;
462
463 if (bus) {
464 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
465 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
466 }
467}
468
62b52c26 469static void build_append_pcihp_notify_entry(Aml *method, int slot)
99fd437d 470{
62b52c26
IM		 471 Aml *if_ctx;
472 int32_t devfn = PCI_DEVFN(slot, 0);
473
5530427f 474 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
62b52c26
IM		 475 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
476 aml_append(method, if_ctx);
99fd437d
MT		 477}
478
62b52c26 479static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
b23046ab 480 bool pcihp_bridge_en)
99fd437d 481{
62b52c26 482 Aml *dev, *notify_method, *method;
99fd437d 483 QObject *bsel;
b23046ab
IM		 484 PCIBus *sec;
485 int i;
133a2da4 486
99fd437d
MT		 487 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
488 if (bsel) {
62b52c26
IM		 489 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
490
491 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
4dbfc881 492 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
8dcf525a 493 }
99fd437d 494
8dcf525a
MT		 495 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
496 DeviceClass *dc;
497 PCIDeviceClass *pc;
498 PCIDevice *pdev = bus->devices[i];
499 int slot = PCI_SLOT(i);
b23046ab 500 bool hotplug_enabled_dev;
093a35e5 501 bool bridge_in_acpi;
99fd437d 502
8dcf525a 503 if (!pdev) {
b23046ab 504 if (bsel) { /* add hotplug slots for non present devices */
62b52c26
IM		 505 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
506 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
507 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
4dbfc881 508 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 509 aml_append(method,
510 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
511 );
512 aml_append(dev, method);
513 aml_append(parent_scope, dev);
514
515 build_append_pcihp_notify_entry(notify_method, slot);
b23046ab 516 }
8dcf525a
MT		 517 continue;
518 }
99fd437d 519
8dcf525a
MT		 520 pc = PCI_DEVICE_GET_CLASS(pdev);
521 dc = DEVICE_GET_CLASS(pdev);
99fd437d 522
093a35e5
MT		 523 /* When hotplug for bridges is enabled, bridges are
524 * described in ACPI separately (see build_pci_bus_end).
525 * In this case they aren't themselves hot-pluggable.
a20275fa 526 * Hotplugged bridges *are* hot-pluggable.
093a35e5 527 */
b23046ab
IM		 528 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
529 !DEVICE(pdev)->hotplugged;
530
531 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
093a35e5 532
b23046ab
IM		 533 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
534 continue;
99fd437d
MT		 535 }
536
62b52c26
IM		 537 /* start to compose PCI slot descriptor */
538 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
539 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
540
8dcf525a 541 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
62b52c26
IM		 542 /* add VGA specific AML methods */
543 int s3d;
544
8dcf525a 545 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
62b52c26 546 s3d = 3;
b23046ab 547 } else {
62b52c26 548 s3d = 0;
99fd437d 549 }
62b52c26 550
4dbfc881 551 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 552 aml_append(method, aml_return(aml_int(0)));
553 aml_append(dev, method);
554
4dbfc881 555 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 556 aml_append(method, aml_return(aml_int(0)));
557 aml_append(dev, method);
558
4dbfc881 559 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
62b52c26
IM		 560 aml_append(method, aml_return(aml_int(s3d)));
561 aml_append(dev, method);
b23046ab 562 } else if (hotplug_enabled_dev) {
62b52c26
IM		 563 /* add _SUN/_EJ0 to make slot hotpluggable */
564 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
99fd437d 565
4dbfc881 566 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
62b52c26
IM		 567 aml_append(method,
568 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
569 );
570 aml_append(dev, method);
571
572 if (bsel) {
573 build_append_pcihp_notify_entry(notify_method, slot);
574 }
b23046ab 575 } else if (bridge_in_acpi) {
62b52c26
IM		 576 /*
577 * device is coldplugged bridge,
578 * add child device descriptions into its scope
579 */
b23046ab 580 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
b23046ab 581
62b52c26 582 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
8dcf525a 583 }
62b52c26
IM		 584 /* slot descriptor has been composed, add it into parent context */
585 aml_append(parent_scope, dev);
8dcf525a
MT		 586 }
587
588 if (bsel) {
62b52c26 589 aml_append(parent_scope, notify_method);
99fd437d
MT		 590 }
591
592 /* Append PCNT method to notify about events on local and child buses.
593 * Add unconditionally for root since DSDT expects it.
72c194f7 594 */
4dbfc881 595 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
99fd437d 596
b23046ab
IM		 597 /* If bus supports hotplug select it and notify about local events */
598 if (bsel) {
62b52c26
IM		 599 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
600 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
601 aml_append(method,
602 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
603 );
604 aml_append(method,
605 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
606 );
b23046ab 607 }
99fd437d 608
b23046ab
IM		 609 /* Notify about child bus events in any case */
610 if (pcihp_bridge_en) {
611 QLIST_FOREACH(sec, &bus->child, sibling) {
62b52c26
IM		 612 int32_t devfn = sec->parent_dev->devfn;
613
614 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
99fd437d 615 }
72c194f7 616 }
62b52c26 617 aml_append(parent_scope, method);
d370dfa9 618 qobject_decref(bsel);
72c194f7
MT		 619}
620
196e2137
IM		 621/**
622 * build_prt_entry:
623 * @link_name: link name for PCI route entry
624 *
625 * build AML package containing a PCI route entry for @link_name
626 */
627static Aml *build_prt_entry(const char *link_name)
628{
629 Aml *a_zero = aml_int(0);
630 Aml *pkg = aml_package(4);
631 aml_append(pkg, a_zero);
632 aml_append(pkg, a_zero);
633 aml_append(pkg, aml_name("%s", link_name));
634 aml_append(pkg, a_zero);
635 return pkg;
636}
637
0d8935e3
MA		 638/*
639 * initialize_route - Initialize the interrupt routing rule
640 * through a specific LINK:
641 * if (lnk_idx == idx)
642 * route using link 'link_name'
643 */
644static Aml *initialize_route(Aml *route, const char *link_name,
645 Aml *lnk_idx, int idx)
646{
647 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
196e2137 648 Aml *pkg = build_prt_entry(link_name);
0d8935e3 649
0d8935e3
MA		 650 aml_append(if_ctx, aml_store(pkg, route));
651
652 return if_ctx;
653}
654
655/*
656 * build_prt - Define interrupt rounting rules
657 *
658 * Returns an array of 128 routes, one for each device,
659 * based on device location.
660 * The main goal is to equaly distribute the interrupts
661 * over the 4 existing ACPI links (works only for i440fx).
662 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
663 *
664 */
196e2137 665static Aml *build_prt(bool is_pci0_prt)
0d8935e3
MA		 666{
667 Aml *method, *while_ctx, *pin, *res;
668
4dbfc881 669 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
0d8935e3
MA		 670 res = aml_local(0);
671 pin = aml_local(1);
672 aml_append(method, aml_store(aml_package(128), res));
673 aml_append(method, aml_store(aml_int(0), pin));
674
675 /* while (pin < 128) */
676 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
677 {
678 Aml *slot = aml_local(2);
679 Aml *lnk_idx = aml_local(3);
680 Aml *route = aml_local(4);
681
682 /* slot = pin >> 2 */
683 aml_append(while_ctx,
c360639a 684 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
0d8935e3
MA		 685 /* lnk_idx = (slot + pin) & 3 */
686 aml_append(while_ctx,
5530427f
IM		 687 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
688 lnk_idx));
0d8935e3
MA		 689
690 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
691 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
196e2137
IM		 692 if (is_pci0_prt) {
693 Aml *if_device_1, *if_pin_4, *else_pin_4;
694
695 /* device 1 is the power-management device, needs SCI */
696 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
697 {
698 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
699 {
700 aml_append(if_pin_4,
701 aml_store(build_prt_entry("LNKS"), route));
702 }
703 aml_append(if_device_1, if_pin_4);
704 else_pin_4 = aml_else();
705 {
706 aml_append(else_pin_4,
707 aml_store(build_prt_entry("LNKA"), route));
708 }
709 aml_append(if_device_1, else_pin_4);
710 }
711 aml_append(while_ctx, if_device_1);
712 } else {
713 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
714 }
0d8935e3
MA		 715 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
716 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
717
718 /* route[0] = 0x[slot]FFFF */
719 aml_append(while_ctx,
ca3df95d
IM		 720 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
721 NULL),
0d8935e3
MA		 722 aml_index(route, aml_int(0))));
723 /* route[1] = pin & 3 */
724 aml_append(while_ctx,
5530427f
IM		 725 aml_store(aml_and(pin, aml_int(3), NULL),
726 aml_index(route, aml_int(1))));
0d8935e3
MA		 727 /* res[pin] = route */
728 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
729 /* pin++ */
730 aml_append(while_ctx, aml_increment(pin));
731 }
732 aml_append(method, while_ctx);
733 /* return res*/
734 aml_append(method, aml_return(res));
735
736 return method;
737}
738
a43c6e27
MA		 739typedef struct CrsRangeEntry {
740 uint64_t base;
741 uint64_t limit;
742} CrsRangeEntry;
743
744static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
745{
746 CrsRangeEntry *entry;
747
748 entry = g_malloc(sizeof(*entry));
749 entry->base = base;
750 entry->limit = limit;
751
752 g_ptr_array_add(ranges, entry);
753}
754
755static void crs_range_free(gpointer data)
756{
757 CrsRangeEntry *entry = (CrsRangeEntry *)data;
758 g_free(entry);
759}
760
dcdca296
MA		 761static gint crs_range_compare(gconstpointer a, gconstpointer b)
762{
763 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
764 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
765
766 return (int64_t)entry_a->base - (int64_t)entry_b->base;
767}
768
769/*
770 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
771 * interval, computes the 'free' ranges from the same interval.
772 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
773 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
774 */
775static void crs_replace_with_free_ranges(GPtrArray *ranges,
776 uint64_t start, uint64_t end)
777{
778 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
779 uint64_t free_base = start;
780 int i;
781
782 g_ptr_array_sort(ranges, crs_range_compare);
783 for (i = 0; i < ranges->len; i++) {
784 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
785
786 if (free_base < used->base) {
787 crs_range_insert(free_ranges, free_base, used->base - 1);
788 }
789
790 free_base = used->limit + 1;
791 }
792
793 if (free_base < end) {
794 crs_range_insert(free_ranges, free_base, end);
795 }
796
797 g_ptr_array_set_size(ranges, 0);
798 for (i = 0; i < free_ranges->len; i++) {
799 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
800 }
801
802 g_ptr_array_free(free_ranges, false);
803}
804
d7fd0e69
MA		 805/*
806 * crs_range_merge - merges adjacent ranges in the given array.
807 * Array elements are deleted and replaced with the merged ranges.
808 */
809static void crs_range_merge(GPtrArray *range)
810{
811 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
812 CrsRangeEntry *entry;
813 uint64_t range_base, range_limit;
814 int i;
815
816 if (!range->len) {
817 return;
818 }
819
820 g_ptr_array_sort(range, crs_range_compare);
821
822 entry = g_ptr_array_index(range, 0);
823 range_base = entry->base;
824 range_limit = entry->limit;
825 for (i = 1; i < range->len; i++) {
826 entry = g_ptr_array_index(range, i);
827 if (entry->base - 1 == range_limit) {
828 range_limit = entry->limit;
829 } else {
830 crs_range_insert(tmp, range_base, range_limit);
831 range_base = entry->base;
832 range_limit = entry->limit;
833 }
834 }
835 crs_range_insert(tmp, range_base, range_limit);
836
837 g_ptr_array_set_size(range, 0);
838 for (i = 0; i < tmp->len; i++) {
839 entry = g_ptr_array_index(tmp, i);
840 crs_range_insert(range, entry->base, entry->limit);
841 }
842 g_ptr_array_free(tmp, true);
843}
844
a43c6e27
MA		 845static Aml *build_crs(PCIHostState *host,
846 GPtrArray *io_ranges, GPtrArray *mem_ranges)
847{
848 Aml *crs = aml_resource_template();
d7fd0e69
MA		 849 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
850 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
851 CrsRangeEntry *entry;
a43c6e27
MA		 852 uint8_t max_bus = pci_bus_num(host->bus);
853 uint8_t type;
854 int devfn;
d7fd0e69 855 int i;
a43c6e27
MA		 856
857 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
a43c6e27
MA		 858 uint64_t range_base, range_limit;
859 PCIDevice *dev = host->bus->devices[devfn];
860
861 if (!dev) {
862 continue;
863 }
864
865 for (i = 0; i < PCI_NUM_REGIONS; i++) {
866 PCIIORegion *r = &dev->io_regions[i];
867
868 range_base = r->addr;
869 range_limit = r->addr + r->size - 1;
870
0f6dd8e1
MA		 871 /*
872 * Work-around for old bioses
873 * that do not support multiple root buses
874 */
875 if (!range_base || range_base > range_limit) {
876 continue;
877 }
878
a43c6e27 879 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
d7fd0e69 880 crs_range_insert(host_io_ranges, range_base, range_limit);
a43c6e27 881 } else { /* "memory" */
d7fd0e69 882 crs_range_insert(host_mem_ranges, range_base, range_limit);
a43c6e27
MA		 883 }
884 }
885
886 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
887 if (type == PCI_HEADER_TYPE_BRIDGE) {
888 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
889 if (subordinate > max_bus) {
890 max_bus = subordinate;
891 }
892
893 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
894 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
0f6dd8e1
MA		 895
896 /*
897 * Work-around for old bioses
898 * that do not support multiple root buses
899 */
4ebc736e 900 if (range_base && range_base <= range_limit) {
d7fd0e69 901 crs_range_insert(host_io_ranges, range_base, range_limit);
0f6dd8e1 902 }
a43c6e27
MA		 903
904 range_base =
905 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
906 range_limit =
907 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
0f6dd8e1
MA		 908
909 /*
910 * Work-around for old bioses
911 * that do not support multiple root buses
912 */
4ebc736e 913 if (range_base && range_base <= range_limit) {
d7fd0e69 914 crs_range_insert(host_mem_ranges, range_base, range_limit);
4ebc736e 915 }
a43c6e27
MA		 916
917 range_base =
918 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
919 range_limit =
920 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
0f6dd8e1
MA		 921
922 /*
923 * Work-around for old bioses
924 * that do not support multiple root buses
925 */
4ebc736e 926 if (range_base && range_base <= range_limit) {
d7fd0e69 927 crs_range_insert(host_mem_ranges, range_base, range_limit);
0f6dd8e1 928 }
a43c6e27
MA		 929 }
930 }
931
d7fd0e69
MA		 932 crs_range_merge(host_io_ranges);
933 for (i = 0; i < host_io_ranges->len; i++) {
934 entry = g_ptr_array_index(host_io_ranges, i);
935 aml_append(crs,
936 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
937 AML_POS_DECODE, AML_ENTIRE_RANGE,
938 0, entry->base, entry->limit, 0,
939 entry->limit - entry->base + 1));
940 crs_range_insert(io_ranges, entry->base, entry->limit);
941 }
942 g_ptr_array_free(host_io_ranges, true);
943
944 crs_range_merge(host_mem_ranges);
945 for (i = 0; i < host_mem_ranges->len; i++) {
946 entry = g_ptr_array_index(host_mem_ranges, i);
947 aml_append(crs,
948 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
949 AML_MAX_FIXED, AML_NON_CACHEABLE,
950 AML_READ_WRITE,
951 0, entry->base, entry->limit, 0,
952 entry->limit - entry->base + 1));
953 crs_range_insert(mem_ranges, entry->base, entry->limit);
954 }
955 g_ptr_array_free(host_mem_ranges, true);
956
a43c6e27 957 aml_append(crs,
dcdca296 958 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
a43c6e27
MA		 959 0,
960 pci_bus_num(host->bus),
961 max_bus,
962 0,
963 max_bus - pci_bus_num(host->bus) + 1));
964
965 return crs;
966}
967
5ca5efa4
IM		 968static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus,
969 AcpiCpuInfo *cpu, AcpiPmInfo *pm)
970{
971 int i;
972 Aml *dev;
973 Aml *crs;
974 Aml *pkg;
975 Aml *field;
976 Aml *ifctx;
977 Aml *method;
978
979 /* The current AML generator can cover the APIC ID range [0..255],
980 * inclusive, for VCPU hotplug. */
981 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
982 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
983
984 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
985 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
986 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
987 aml_append(dev,
988 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
989 );
990 /* device present, functioning, decoding, not shown in UI */
991 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
992 crs = aml_resource_template();
993 aml_append(crs,
994 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
995 pm->cpu_hp_io_len)
996 );
997 aml_append(dev, aml_name_decl("_CRS", crs));
998 aml_append(sb_scope, dev);
999 /* declare CPU hotplug MMIO region and PRS field to access it */
1000 aml_append(sb_scope, aml_operation_region(
3f3009c0 1001 "PRST", AML_SYSTEM_IO, aml_int(pm->cpu_hp_io_base), pm->cpu_hp_io_len));
5ca5efa4
IM		 1002 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1003 aml_append(field, aml_named_field("PRS", 256));
1004 aml_append(sb_scope, field);
1005
1006 /* build Processor object for each processor */
1007 for (i = 0; i < acpi_cpus; i++) {
1008 dev = aml_processor(i, 0, 0, "CP%.02X", i);
1009
1010 method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
1011 aml_append(method,
1012 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i))));
1013 aml_append(dev, method);
1014
1015 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1016 aml_append(method,
1017 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i))));
1018 aml_append(dev, method);
1019
1020 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1021 aml_append(method,
1022 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0)))
1023 );
1024 aml_append(dev, method);
1025
1026 aml_append(sb_scope, dev);
1027 }
1028
1029 /* build this code:
1030 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1031 */
1032 /* Arg0 = Processor ID = APIC ID */
1033 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1034 for (i = 0; i < acpi_cpus; i++) {
1035 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1036 aml_append(ifctx,
1037 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1038 );
1039 aml_append(method, ifctx);
1040 }
1041 aml_append(sb_scope, method);
1042
1043 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1044 *
1045 * Note: The ability to create variable-sized packages was first
1046 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1047 * ith up to 255 elements. Windows guests up to win2k8 fail when
1048 * VarPackageOp is used.
1049 */
1050 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1051 aml_varpackage(acpi_cpus);
1052
1053 for (i = 0; i < acpi_cpus; i++) {
1054 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1055 aml_append(pkg, aml_int(b));
1056 }
1057 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg));
1058}
1059
f177d40a
IM		 1060static void build_memory_devices(Aml *sb_scope, int nr_mem,
1061 uint16_t io_base, uint16_t io_len)
1062{
1063 int i;
1064 Aml *scope;
1065 Aml *crs;
1066 Aml *field;
1067 Aml *dev;
1068 Aml *method;
1069 Aml *ifctx;
1070
1071 /* build memory devices */
1072 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
f84548dd 1073 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
f177d40a 1074 aml_append(scope,
f84548dd 1075 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
f177d40a
IM		 1076 );
1077
1078 crs = aml_resource_template();
1079 aml_append(crs,
1080 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
1081 );
1082 aml_append(scope, aml_name_decl("_CRS", crs));
1083
1084 aml_append(scope, aml_operation_region(
f84548dd 1085 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
3f3009c0 1086 aml_int(io_base), io_len)
f177d40a
IM		 1087 );
1088
f84548dd 1089 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
f177d40a
IM		 1090 AML_NOLOCK, AML_PRESERVE);
1091 aml_append(field, /* read only */
f84548dd 1092 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
f177d40a 1093 aml_append(field, /* read only */
f84548dd 1094 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
f177d40a 1095 aml_append(field, /* read only */
f84548dd 1096 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
f177d40a 1097 aml_append(field, /* read only */
f84548dd 1098 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
f177d40a 1099 aml_append(field, /* read only */
f84548dd 1100 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
f177d40a
IM		 1101 aml_append(scope, field);
1102
f84548dd 1103 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
f177d40a
IM		 1104 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1105 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1106 aml_append(field, /* 1 if enabled, read only */
f84548dd 1107 aml_named_field(MEMORY_SLOT_ENABLED, 1));
f177d40a
IM		 1108 aml_append(field,
1109 /*(read) 1 if has a insert event. (write) 1 to clear event */
f84548dd 1110 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
f177d40a
IM		 1111 aml_append(field,
1112 /* (read) 1 if has a remove event. (write) 1 to clear event */
f84548dd 1113 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
f177d40a
IM		 1114 aml_append(field,
1115 /* initiates device eject, write only */
f84548dd 1116 aml_named_field(MEMORY_SLOT_EJECT, 1));
f177d40a
IM		 1117 aml_append(scope, field);
1118
f84548dd 1119 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
f177d40a
IM		 1120 AML_NOLOCK, AML_PRESERVE);
1121 aml_append(field, /* DIMM selector, write only */
f84548dd 1122 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
f177d40a 1123 aml_append(field, /* _OST event code, write only */
f84548dd 1124 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
f177d40a 1125 aml_append(field, /* _OST status code, write only */
f84548dd 1126 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
f177d40a
IM		 1127 aml_append(scope, field);
1128 aml_append(sb_scope, scope);
1129
1130 for (i = 0; i < nr_mem; i++) {
f84548dd 1131 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
f177d40a
IM		 1132 const char *s;
1133
1134 dev = aml_device("MP%02X", i);
1135 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1136 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1137
1138 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
f84548dd 1139 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
f177d40a
IM		 1140 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1141 aml_append(dev, method);
1142
1143 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
f84548dd 1144 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
f177d40a
IM		 1145 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1146 aml_append(dev, method);
1147
1148 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
f84548dd 1149 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
f177d40a
IM		 1150 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1151 aml_append(dev, method);
1152
1153 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
f84548dd
IM		 1154 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1155
f177d40a
IM		 1156 aml_append(method, aml_return(aml_call4(
1157 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1158 )));
1159 aml_append(dev, method);
1160
1161 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
f84548dd 1162 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
f177d40a
IM		 1163 aml_append(method, aml_return(aml_call2(
1164 s, aml_name("_UID"), aml_arg(0))));
1165 aml_append(dev, method);
1166
1167 aml_append(sb_scope, dev);
1168 }
1169
1170 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1171 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1172 */
f84548dd 1173 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
f177d40a
IM		 1174 for (i = 0; i < nr_mem; i++) {
1175 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1176 aml_append(ifctx,
1177 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1178 );
1179 aml_append(method, ifctx);
1180 }
1181 aml_append(sb_scope, method);
1182}
1183
a57d708d
IM		 1184static void build_hpet_aml(Aml *table)
1185{
1186 Aml *crs;
1187 Aml *field;
1188 Aml *method;
1189 Aml *if_ctx;
1190 Aml *scope = aml_scope("_SB");
1191 Aml *dev = aml_device("HPET");
1192 Aml *zero = aml_int(0);
1193 Aml *id = aml_local(0);
1194 Aml *period = aml_local(1);
1195
1196 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1197 aml_append(dev, aml_name_decl("_UID", zero));
1198
1199 aml_append(dev,
3f3009c0
XG		 1200 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1201 HPET_LEN));
a57d708d
IM		 1202 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1203 aml_append(field, aml_named_field("VEND", 32));
1204 aml_append(field, aml_named_field("PRD", 32));
1205 aml_append(dev, field);
1206
1207 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1208 aml_append(method, aml_store(aml_name("VEND"), id));
1209 aml_append(method, aml_store(aml_name("PRD"), period));
1210 aml_append(method, aml_shiftright(id, aml_int(16), id));
1211 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1212 aml_equal(id, aml_int(0xffff))));
1213 {
1214 aml_append(if_ctx, aml_return(zero));
1215 }
1216 aml_append(method, if_ctx);
1217
1218 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1219 aml_lgreater(period, aml_int(100000000))));
1220 {
1221 aml_append(if_ctx, aml_return(zero));
1222 }
1223 aml_append(method, if_ctx);
1224
1225 aml_append(method, aml_return(aml_int(0x0F)));
1226 aml_append(dev, method);
1227
1228 crs = aml_resource_template();
1229 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1230 aml_append(dev, aml_name_decl("_CRS", crs));
1231
1232 aml_append(scope, dev);
1233 aml_append(table, scope);
1234}
1235
27b9fc54 1236static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
95ed7e97 1237{
27b9fc54
RK		 1238 Aml *dev, *fdi;
1239 uint8_t maxc, maxh, maxs;
1240
1241 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1242
1243 dev = aml_device("FLP%c", 'A' + idx);
1244
1245 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1246
1247 fdi = aml_package(16);
1248 aml_append(fdi, aml_int(idx)); /* Drive Number */
1249 aml_append(fdi,
1250 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1251 /*
1252 * the values below are the limits of the drive, and are thus independent
1253 * of the inserted media
1254 */
1255 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1256 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1257 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1258 /*
1259 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1260 * the drive type, so shall we
1261 */
1262 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1263 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1264 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1265 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1266 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1267 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1268 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1269 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1270 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1271 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1272 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1273
1274 aml_append(dev, aml_name_decl("_FDI", fdi));
1275 return dev;
1276}
1277
1278static Aml *build_fdc_device_aml(ISADevice *fdc)
1279{
1280 int i;
95ed7e97
IM		 1281 Aml *dev;
1282 Aml *crs;
95ed7e97 1283
27b9fc54
RK		 1284#define ACPI_FDE_MAX_FD 4
1285 uint32_t fde_buf[5] = {
1286 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1287 cpu_to_le32(2) /* tape presence (2 == never present) */
1288 };
1289
95ed7e97
IM		 1290 dev = aml_device("FDC0");
1291 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1292
95ed7e97
IM		 1293 crs = aml_resource_template();
1294 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1295 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1296 aml_append(crs, aml_irq_no_flags(6));
1297 aml_append(crs,
1298 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1299 aml_append(dev, aml_name_decl("_CRS", crs));
1300
27b9fc54
RK		 1301 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1302 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1303
1304 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1305 fde_buf[i] = cpu_to_le32(1); /* drive present */
1306 aml_append(dev, build_fdinfo_aml(i, type));
1307 }
1308 }
1309 aml_append(dev, aml_name_decl("_FDE",
1310 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1311
95ed7e97
IM		 1312 return dev;
1313}
1314
ee135849
IM		 1315static Aml *build_rtc_device_aml(void)
1316{
1317 Aml *dev;
1318 Aml *crs;
1319
1320 dev = aml_device("RTC");
1321 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1322 crs = aml_resource_template();
1323 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1324 aml_append(crs, aml_irq_no_flags(8));
1325 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
95ed7e97 1326 aml_append(dev, aml_name_decl("_CRS", crs));
f58190e2
IM		 1327
1328 return dev;
1329}
1330
1331static Aml *build_kbd_device_aml(void)
1332{
1333 Aml *dev;
1334 Aml *crs;
1335 Aml *method;
1336
1337 dev = aml_device("KBD");
1338 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1339
1340 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1341 aml_append(method, aml_return(aml_int(0x0f)));
1342 aml_append(dev, method);
1343
1344 crs = aml_resource_template();
1345 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1346 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1347 aml_append(crs, aml_irq_no_flags(1));
ee135849
IM		 1348 aml_append(dev, aml_name_decl("_CRS", crs));
1349
1350 return dev;
1351}
1352
c355cb2c
IM		 1353static Aml *build_mouse_device_aml(void)
1354{
1355 Aml *dev;
1356 Aml *crs;
1357 Aml *method;
1358
1359 dev = aml_device("MOU");
1360 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1361
1362 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1363 aml_append(method, aml_return(aml_int(0x0f)));
1364 aml_append(dev, method);
1365
1366 crs = aml_resource_template();
1367 aml_append(crs, aml_irq_no_flags(12));
1368 aml_append(dev, aml_name_decl("_CRS", crs));
1369
1370 return dev;
1371}
1372
8b1da5f8
IM		 1373static Aml *build_lpt_device_aml(void)
1374{
1375 Aml *dev;
1376 Aml *crs;
1377 Aml *method;
1378 Aml *if_ctx;
1379 Aml *else_ctx;
1380 Aml *zero = aml_int(0);
1381 Aml *is_present = aml_local(0);
1382
1383 dev = aml_device("LPT");
1384 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1385
1386 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1387 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1388 if_ctx = aml_if(aml_equal(is_present, zero));
1389 {
1390 aml_append(if_ctx, aml_return(aml_int(0x00)));
1391 }
1392 aml_append(method, if_ctx);
1393 else_ctx = aml_else();
1394 {
1395 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1396 }
1397 aml_append(method, else_ctx);
1398 aml_append(dev, method);
1399
1400 crs = aml_resource_template();
1401 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1402 aml_append(crs, aml_irq_no_flags(7));
1403 aml_append(dev, aml_name_decl("_CRS", crs));
1404
1405 return dev;
1406}
1407
28f1f0e9
IM		 1408static Aml *build_com_device_aml(uint8_t uid)
1409{
1410 Aml *dev;
1411 Aml *crs;
1412 Aml *method;
1413 Aml *if_ctx;
1414 Aml *else_ctx;
1415 Aml *zero = aml_int(0);
1416 Aml *is_present = aml_local(0);
1417 const char *enabled_field = "CAEN";
1418 uint8_t irq = 4;
1419 uint16_t io_port = 0x03F8;
1420
1421 assert(uid == 1 || uid == 2);
1422 if (uid == 2) {
1423 enabled_field = "CBEN";
1424 irq = 3;
1425 io_port = 0x02F8;
1426 }
1427
1428 dev = aml_device("COM%d", uid);
1429 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1430 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1431
1432 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1433 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1434 if_ctx = aml_if(aml_equal(is_present, zero));
1435 {
1436 aml_append(if_ctx, aml_return(aml_int(0x00)));
1437 }
1438 aml_append(method, if_ctx);
1439 else_ctx = aml_else();
1440 {
1441 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1442 }
1443 aml_append(method, else_ctx);
1444 aml_append(dev, method);
1445
1446 crs = aml_resource_template();
1447 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1448 aml_append(crs, aml_irq_no_flags(irq));
1449 aml_append(dev, aml_name_decl("_CRS", crs));
1450
1451 return dev;
1452}
1453
ee135849
IM		 1454static void build_isa_devices_aml(Aml *table)
1455{
27b9fc54
RK		 1456 ISADevice *fdc = pc_find_fdc0();
1457
ee135849
IM		 1458 Aml *scope = aml_scope("_SB.PCI0.ISA");
1459
1460 aml_append(scope, build_rtc_device_aml());
f58190e2 1461 aml_append(scope, build_kbd_device_aml());
c355cb2c 1462 aml_append(scope, build_mouse_device_aml());
27b9fc54
RK		 1463 if (fdc) {
1464 aml_append(scope, build_fdc_device_aml(fdc));
9b613f4e 1465 }
8b1da5f8 1466 aml_append(scope, build_lpt_device_aml());
28f1f0e9
IM		 1467 aml_append(scope, build_com_device_aml(1));
1468 aml_append(scope, build_com_device_aml(2));
ee135849
IM		 1469
1470 aml_append(table, scope);
1471}
1472
3892a2b7
IM		 1473static void build_dbg_aml(Aml *table)
1474{
1475 Aml *field;
1476 Aml *method;
1477 Aml *while_ctx;
1478 Aml *scope = aml_scope("\\");
1479 Aml *buf = aml_local(0);
1480 Aml *len = aml_local(1);
1481 Aml *idx = aml_local(2);
1482
1483 aml_append(scope,
3f3009c0 1484 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
3892a2b7
IM		 1485 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1486 aml_append(field, aml_named_field("DBGB", 8));
1487 aml_append(scope, field);
1488
1489 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1490
1491 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1492 aml_append(method, aml_to_buffer(buf, buf));
1493 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1494 aml_append(method, aml_store(aml_int(0), idx));
1495
1496 while_ctx = aml_while(aml_lless(idx, len));
1497 aml_append(while_ctx,
1498 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1499 aml_append(while_ctx, aml_increment(idx));
1500 aml_append(method, while_ctx);
1501
1502 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1503 aml_append(scope, method);
1504
1505 aml_append(table, scope);
1506}
1507
c35b6e80
IM		 1508static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1509{
1510 Aml *dev;
1511 Aml *crs;
1512 Aml *method;
1513 uint32_t irqs[] = {5, 10, 11};
1514
1515 dev = aml_device("%s", name);
1516 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1517 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1518
1519 crs = aml_resource_template();
1520 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1521 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1522 aml_append(dev, aml_name_decl("_PRS", crs));
1523
1524 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1525 aml_append(method, aml_return(aml_call1("IQST", reg)));
1526 aml_append(dev, method);
1527
1528 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1529 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1530 aml_append(dev, method);
1531
1532 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1533 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1534 aml_append(dev, method);
1535
1536 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1537 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1538 aml_append(method, aml_store(aml_name("PRRI"), reg));
1539 aml_append(dev, method);
1540
1541 return dev;
1542 }
1543
80b32df5
IM		 1544static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1545{
1546 Aml *dev;
1547 Aml *crs;
1548 Aml *method;
1549 uint32_t irqs;
1550
1551 dev = aml_device("%s", name);
1552 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1553 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1554
1555 crs = aml_resource_template();
1556 irqs = gsi;
1557 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1558 AML_SHARED, &irqs, 1));
1559 aml_append(dev, aml_name_decl("_PRS", crs));
1560
1561 aml_append(dev, aml_name_decl("_CRS", crs));
1562
c82f503d
MA		 1563 /*
1564 * _DIS can be no-op because the interrupt cannot be disabled.
1565 */
1566 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1567 aml_append(dev, method);
1568
80b32df5
IM		 1569 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1570 aml_append(dev, method);
1571
1572 return dev;
1573}
1574
16682a9d
IM		 1575/* _CRS method - get current settings */
1576static Aml *build_iqcr_method(bool is_piix4)
1577{
1578 Aml *if_ctx;
1579 uint32_t irqs;
1580 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1581 Aml *crs = aml_resource_template();
1582
1583 irqs = 0;
1584 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1585 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1586 aml_append(method, aml_name_decl("PRR0", crs));
1587
1588 aml_append(method,
1589 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1590
1591 if (is_piix4) {
1592 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1593 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1594 aml_append(method, if_ctx);
1595 } else {
1596 aml_append(method,
1597 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1598 aml_name("PRRI")));
1599 }
1600
1601 aml_append(method, aml_return(aml_name("PRR0")));
1602 return method;
1603}
1604
78e1ad05
IM		 1605/* _STA method - get status */
1606static Aml *build_irq_status_method(void)
1607{
1608 Aml *if_ctx;
1609 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1610
1611 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1612 aml_append(if_ctx, aml_return(aml_int(0x09)));
1613 aml_append(method, if_ctx);
1614 aml_append(method, aml_return(aml_int(0x0B)));
1615 return method;
1616}
1617
e4db2798
IM		 1618static void build_piix4_pci0_int(Aml *table)
1619{
c35b6e80
IM		 1620 Aml *dev;
1621 Aml *crs;
e4db2798 1622 Aml *field;
c35b6e80
IM		 1623 Aml *method;
1624 uint32_t irqs;
e4db2798 1625 Aml *sb_scope = aml_scope("_SB");
196e2137
IM		 1626 Aml *pci0_scope = aml_scope("PCI0");
1627
1628 aml_append(pci0_scope, build_prt(true));
1629 aml_append(sb_scope, pci0_scope);
e4db2798
IM		 1630
1631 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1632 aml_append(field, aml_named_field("PRQ0", 8));
1633 aml_append(field, aml_named_field("PRQ1", 8));
1634 aml_append(field, aml_named_field("PRQ2", 8));
1635 aml_append(field, aml_named_field("PRQ3", 8));
1636 aml_append(sb_scope, field);
1637
78e1ad05 1638 aml_append(sb_scope, build_irq_status_method());
16682a9d 1639 aml_append(sb_scope, build_iqcr_method(true));
100681cc 1640
c35b6e80
IM		 1641 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1642 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1643 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1644 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1645
1646 dev = aml_device("LNKS");
1647 {
1648 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1649 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1650
1651 crs = aml_resource_template();
1652 irqs = 9;
1653 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1654 AML_ACTIVE_HIGH, AML_SHARED,
1655 &irqs, 1));
1656 aml_append(dev, aml_name_decl("_PRS", crs));
1657
1658 /* The SCI cannot be disabled and is always attached to GSI 9,
1659 * so these are no-ops. We only need this link to override the
1660 * polarity to active high and match the content of the MADT.
1661 */
1662 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1663 aml_append(method, aml_return(aml_int(0x0b)));
1664 aml_append(dev, method);
1665
1666 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1667 aml_append(dev, method);
1668
1669 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1670 aml_append(method, aml_return(aml_name("_PRS")));
1671 aml_append(dev, method);
1672
1673 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1674 aml_append(dev, method);
1675 }
1676 aml_append(sb_scope, dev);
1677
e4db2798
IM		 1678 aml_append(table, sb_scope);
1679}
1680
22b5b8bf
IM		 1681static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1682{
1683 int i;
1684 int head;
1685 Aml *pkg;
1686 char base = name[3] < 'E' ? 'A' : 'E';
1687 char *s = g_strdup(name);
1688 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1689
1690 assert(strlen(s) == 4);
1691
1692 head = name[3] - base;
1693 for (i = 0; i < 4; i++) {
1694 if (head + i > 3) {
1695 head = i * -1;
1696 }
1697 s[3] = base + head + i;
1698 pkg = aml_package(4);
1699 aml_append(pkg, a_nr);
1700 aml_append(pkg, aml_int(i));
1701 aml_append(pkg, aml_name("%s", s));
1702 aml_append(pkg, aml_int(0));
1703 aml_append(ctx, pkg);
1704 }
1705 g_free(s);
1706}
1707
1708static Aml *build_q35_routing_table(const char *str)
1709{
1710 int i;
1711 Aml *pkg;
1712 char *name = g_strdup_printf("%s ", str);
1713
1714 pkg = aml_package(128);
1715 for (i = 0; i < 0x18; i++) {
1716 name[3] = 'E' + (i & 0x3);
1717 append_q35_prt_entry(pkg, i, name);
1718 }
1719
1720 name[3] = 'E';
1721 append_q35_prt_entry(pkg, 0x18, name);
1722
1723 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1724 for (i = 0x0019; i < 0x1e; i++) {
1725 name[3] = 'A';
1726 append_q35_prt_entry(pkg, i, name);
1727 }
1728
1729 /* PCIe->PCI bridge. use PIRQ[E-H] */
1730 name[3] = 'E';
1731 append_q35_prt_entry(pkg, 0x1e, name);
1732 name[3] = 'A';
1733 append_q35_prt_entry(pkg, 0x1f, name);
1734
1735 g_free(name);
1736 return pkg;
1737}
1738
80b32df5
IM		 1739static void build_q35_pci0_int(Aml *table)
1740{
41f95a52 1741 Aml *field;
0dafe3b3 1742 Aml *method;
80b32df5 1743 Aml *sb_scope = aml_scope("_SB");
0dafe3b3
IM		 1744 Aml *pci0_scope = aml_scope("PCI0");
1745
e9fce798
IM		 1746 /* Zero => PIC mode, One => APIC Mode */
1747 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1748 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1749 {
1750 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1751 }
1752 aml_append(table, method);
1753
65aef4de
IM		 1754 aml_append(pci0_scope,
1755 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
22b5b8bf
IM		 1756 aml_append(pci0_scope,
1757 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1758
0dafe3b3
IM		 1759 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1760 {
1761 Aml *if_ctx;
1762 Aml *else_ctx;
1763
1764 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1765 section 6.2.8.1 */
1766 /* Note: we provide the same info as the PCI routing
1767 table of the Bochs BIOS */
1768 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1769 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1770 aml_append(method, if_ctx);
1771 else_ctx = aml_else();
1772 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1773 aml_append(method, else_ctx);
1774 }
1775 aml_append(pci0_scope, method);
1776 aml_append(sb_scope, pci0_scope);
80b32df5 1777
41f95a52
IM		 1778 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1779 aml_append(field, aml_named_field("PRQA", 8));
1780 aml_append(field, aml_named_field("PRQB", 8));
1781 aml_append(field, aml_named_field("PRQC", 8));
1782 aml_append(field, aml_named_field("PRQD", 8));
1783 aml_append(field, aml_reserved_field(0x20));
1784 aml_append(field, aml_named_field("PRQE", 8));
1785 aml_append(field, aml_named_field("PRQF", 8));
1786 aml_append(field, aml_named_field("PRQG", 8));
1787 aml_append(field, aml_named_field("PRQH", 8));
1788 aml_append(sb_scope, field);
1789
78e1ad05 1790 aml_append(sb_scope, build_irq_status_method());
16682a9d
IM		 1791 aml_append(sb_scope, build_iqcr_method(false));
1792
12e3b1f7
IM		 1793 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1794 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1795 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1796 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1797 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1798 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1799 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1800 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1801
80b32df5
IM		 1802 /*
1803 * TODO: UID probably shouldn't be the same for GSIx devices
1804 * but that's how it was in original ASL so keep it for now
1805 */
1806 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10));
1807 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11));
1808 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12));
1809 aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13));
1810 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14));
1811 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15));
1812 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16));
1813 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17));
1814
1815 aml_append(table, sb_scope);
1816}
1817
41f95a52
IM		 1818static void build_q35_isa_bridge(Aml *table)
1819{
1820 Aml *dev;
1821 Aml *scope;
1822 Aml *field;
1823
1824 scope = aml_scope("_SB.PCI0");
1825 dev = aml_device("ISA");
1826 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1827
1828 /* ICH9 PCI to ISA irq remapping */
1829 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
3f3009c0 1830 aml_int(0x60), 0x0C));
41f95a52
IM		 1831
1832 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
3f3009c0 1833 aml_int(0x80), 0x02));
41f95a52
IM		 1834 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1835 aml_append(field, aml_named_field("COMA", 3));
1836 aml_append(field, aml_reserved_field(1));
1837 aml_append(field, aml_named_field("COMB", 3));
1838 aml_append(field, aml_reserved_field(1));
1839 aml_append(field, aml_named_field("LPTD", 2));
41f95a52
IM		 1840 aml_append(dev, field);
1841
1842 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
3f3009c0 1843 aml_int(0x82), 0x02));
41f95a52
IM		 1844 /* enable bits */
1845 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1846 aml_append(field, aml_named_field("CAEN", 1));
1847 aml_append(field, aml_named_field("CBEN", 1));
1848 aml_append(field, aml_named_field("LPEN", 1));
41f95a52
IM		 1849 aml_append(dev, field);
1850
1851 aml_append(scope, dev);
1852 aml_append(table, scope);
1853}
1854
e4db2798
IM		 1855static void build_piix4_pm(Aml *table)
1856{
1857 Aml *dev;
1858 Aml *scope;
1859
1860 scope = aml_scope("_SB.PCI0");
1861 dev = aml_device("PX13");
1862 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1863
1864 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
3f3009c0 1865 aml_int(0x00), 0xff));
e4db2798
IM		 1866 aml_append(scope, dev);
1867 aml_append(table, scope);
1868}
1869
1870static void build_piix4_isa_bridge(Aml *table)
1871{
1872 Aml *dev;
1873 Aml *scope;
1874 Aml *field;
1875
1876 scope = aml_scope("_SB.PCI0");
1877 dev = aml_device("ISA");
1878 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1879
1880 /* PIIX PCI to ISA irq remapping */
1881 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
3f3009c0 1882 aml_int(0x60), 0x04));
e4db2798
IM		 1883 /* enable bits */
1884 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1885 /* Offset(0x5f),, 7, */
1886 aml_append(field, aml_reserved_field(0x2f8));
1887 aml_append(field, aml_reserved_field(7));
1888 aml_append(field, aml_named_field("LPEN", 1));
1889 /* Offset(0x67),, 3, */
1890 aml_append(field, aml_reserved_field(0x38));
1891 aml_append(field, aml_reserved_field(3));
1892 aml_append(field, aml_named_field("CAEN", 1));
1893 aml_append(field, aml_reserved_field(3));
1894 aml_append(field, aml_named_field("CBEN", 1));
1895 aml_append(dev, field);
e4db2798
IM		 1896
1897 aml_append(scope, dev);
1898 aml_append(table, scope);
1899}
1900
b616ec4d
IM		 1901static void build_piix4_pci_hotplug(Aml *table)
1902{
1903 Aml *scope;
1904 Aml *field;
1905 Aml *method;
1906
1907 scope = aml_scope("_SB.PCI0");
1908
1909 aml_append(scope,
3f3009c0 1910 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
b616ec4d
IM		 1911 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1912 aml_append(field, aml_named_field("PCIU", 32));
1913 aml_append(field, aml_named_field("PCID", 32));
1914 aml_append(scope, field);
1915
1916 aml_append(scope,
3f3009c0 1917 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
b616ec4d
IM		 1918 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1919 aml_append(field, aml_named_field("B0EJ", 32));
1920 aml_append(scope, field);
1921
1922 aml_append(scope,
3f3009c0 1923 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
b616ec4d
IM		 1924 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1925 aml_append(field, aml_named_field("BNUM", 32));
1926 aml_append(scope, field);
1927
1928 aml_append(scope, aml_mutex("BLCK", 0));
1929
1930 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1931 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1932 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1933 aml_append(method,
1934 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1935 aml_append(method, aml_release(aml_name("BLCK")));
1936 aml_append(method, aml_return(aml_int(0)));
1937 aml_append(scope, method);
1938
1939 aml_append(table, scope);
1940}
1941
f97a88a8
IM		 1942static Aml *build_q35_osc_method(void)
1943{
1944 Aml *if_ctx;
1945 Aml *if_ctx2;
1946 Aml *else_ctx;
1947 Aml *method;
1948 Aml *a_cwd1 = aml_name("CDW1");
1949 Aml *a_ctrl = aml_name("CTRL");
1950
1951 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1952 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1953
1954 if_ctx = aml_if(aml_equal(
1955 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1956 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1957 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1958
1959 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1960 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1961
1962 /*
1963 * Always allow native PME, AER (no dependencies)
1964 * Never allow SHPC (no SHPC controller in this system)
1965 */
1966 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1967
1968 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1969 /* Unknown revision */
1970 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1971 aml_append(if_ctx, if_ctx2);
1972
1973 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1974 /* Capabilities bits were masked */
1975 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1976 aml_append(if_ctx, if_ctx2);
1977
1978 /* Update DWORD3 in the buffer */
1979 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1980 aml_append(method, if_ctx);
1981
1982 else_ctx = aml_else();
1983 /* Unrecognized UUID */
1984 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1985 aml_append(method, else_ctx);
1986
1987 aml_append(method, aml_return(aml_arg(3)));
1988 return method;
1989}
b616ec4d 1990
72c194f7 1991static void
41fa5c04 1992build_dsdt(GArray *table_data, GArray *linker,
72c194f7 1993 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
3d3ebcad 1994 PcPciInfo *pci, MachineState *machine)
72c194f7 1995{
41fa5c04
IM		 1996 CrsRangeEntry *entry;
1997 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1998 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1999 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
fb306ffe 2000 PCMachineState *pcms = PC_MACHINE(machine);
bef3492d 2001 uint32_t nr_mem = machine->ram_slots;
dcdca296 2002 int root_bus_limit = 0xFF;
41fa5c04 2003 PCIBus *bus = NULL;
72c194f7
MT		 2004 int i;
2005
41fa5c04 2006 dsdt = init_aml_allocator();
2fd71f1b 2007
4ec8d2b3 2008 /* Reserve space for header */
41fa5c04
IM		 2009 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
2010
2011 build_dbg_aml(dsdt);
2012 if (misc->is_piix4) {
2013 sb_scope = aml_scope("_SB");
2014 dev = aml_device("PCI0");
2015 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2016 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2017 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2018 aml_append(sb_scope, dev);
2019 aml_append(dsdt, sb_scope);
2020
2021 build_hpet_aml(dsdt);
2022 build_piix4_pm(dsdt);
2023 build_piix4_isa_bridge(dsdt);
2024 build_isa_devices_aml(dsdt);
2025 build_piix4_pci_hotplug(dsdt);
2026 build_piix4_pci0_int(dsdt);
2027 } else {
2028 sb_scope = aml_scope("_SB");
2029 aml_append(sb_scope,
3f3009c0 2030 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
41fa5c04 2031 aml_append(sb_scope,
3f3009c0 2032 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
41fa5c04
IM		 2033 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
2034 aml_append(field, aml_named_field("PCIB", 8));
2035 aml_append(sb_scope, field);
2036 aml_append(dsdt, sb_scope);
2037
2038 sb_scope = aml_scope("_SB");
2039 dev = aml_device("PCI0");
2040 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
2041 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
2042 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
2043 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
2044 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
2045 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
2046 aml_append(dev, build_q35_osc_method());
2047 aml_append(sb_scope, dev);
2048 aml_append(dsdt, sb_scope);
2049
2050 build_hpet_aml(dsdt);
2051 build_q35_isa_bridge(dsdt);
2052 build_isa_devices_aml(dsdt);
2053 build_q35_pci0_int(dsdt);
2054 }
2055
2056 build_cpu_hotplug_aml(dsdt);
2057 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
2058 pm->mem_hp_io_len);
2059
2060 scope = aml_scope("_GPE");
2061 {
2062 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
2063
2064 aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED));
2065
2066 if (misc->is_piix4) {
2067 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
2068 aml_append(method,
2069 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
2070 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
2071 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
2072 aml_append(scope, method);
2073 } else {
2074 aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED));
2075 }
2076
2077 method = aml_method("_E02", 0, AML_NOTSERIALIZED);
2078 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD));
2079 aml_append(scope, method);
2080
2081 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
2082 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
2083 aml_append(scope, method);
2084
2085 aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED));
2086 aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED));
2087 aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED));
2088 aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED));
2089 aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED));
2090 aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED));
2091 aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED));
2092 aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED));
2093 aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED));
2094 aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED));
2095 aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED));
2096 aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED));
2097 }
2098 aml_append(dsdt, scope);
72c194f7 2099
81ed6482 2100 bus = PC_MACHINE(machine)->bus;
a4894206
MA		 2101 if (bus) {
2102 QLIST_FOREACH(bus, &bus->child, sibling) {
2103 uint8_t bus_num = pci_bus_num(bus);
0e79e51a 2104 uint8_t numa_node = pci_bus_numa_node(bus);
a4894206
MA		 2105
2106 /* look only for expander root buses */
2107 if (!pci_bus_is_root(bus)) {
2108 continue;
2109 }
2110
dcdca296
MA		 2111 if (bus_num < root_bus_limit) {
2112 root_bus_limit = bus_num - 1;
2113 }
2114
a4894206
MA		 2115 scope = aml_scope("\\_SB");
2116 dev = aml_device("PC%.02X", bus_num);
c96d9286
LE		 2117 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
2118 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
a4894206 2119 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
0e79e51a
MA		 2120
2121 if (numa_node != NUMA_NODE_UNASSIGNED) {
2122 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2123 }
2124
196e2137 2125 aml_append(dev, build_prt(false));
a43c6e27
MA		 2126 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
2127 io_ranges, mem_ranges);
2128 aml_append(dev, aml_name_decl("_CRS", crs));
a4894206 2129 aml_append(scope, dev);
41fa5c04 2130 aml_append(dsdt, scope);
a4894206
MA		 2131 }
2132 }
2133
500b11ea 2134 scope = aml_scope("\\_SB.PCI0");
60efd429
IM		 2135 /* build PCI0._CRS */
2136 crs = aml_resource_template();
2137 aml_append(crs,
ff80dc7f 2138 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
dcdca296
MA		 2139 0x0000, 0x0, root_bus_limit,
2140 0x0000, root_bus_limit + 1));
ff80dc7f 2141 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
60efd429
IM		 2142
2143 aml_append(crs,
ff80dc7f
SZ		 2144 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2145 AML_POS_DECODE, AML_ENTIRE_RANGE,
60efd429 2146 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
dcdca296
MA		 2147
2148 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
2149 for (i = 0; i < io_ranges->len; i++) {
2150 entry = g_ptr_array_index(io_ranges, i);
2151 aml_append(crs,
2152 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2153 AML_POS_DECODE, AML_ENTIRE_RANGE,
2154 0x0000, entry->base, entry->limit,
2155 0x0000, entry->limit - entry->base + 1));
2156 }
2157
60efd429 2158 aml_append(crs,
ff80dc7f
SZ		 2159 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2160 AML_CACHEABLE, AML_READ_WRITE,
60efd429 2161 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
dcdca296
MA		 2162
2163 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
2164 for (i = 0; i < mem_ranges->len; i++) {
2165 entry = g_ptr_array_index(mem_ranges, i);
2166 aml_append(crs,
2167 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2168 AML_NON_CACHEABLE, AML_READ_WRITE,
2169 0, entry->base, entry->limit,
2170 0, entry->limit - entry->base + 1));
2171 }
2172
60efd429
IM		 2173 if (pci->w64.begin) {
2174 aml_append(crs,
ff80dc7f
SZ		 2175 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2176 AML_CACHEABLE, AML_READ_WRITE,
60efd429
IM		 2177 0, pci->w64.begin, pci->w64.end - 1, 0,
2178 pci->w64.end - pci->w64.begin));
2179 }
2180 aml_append(scope, aml_name_decl("_CRS", crs));
2181
d31c909e
IM		 2182 /* reserve GPE0 block resources */
2183 dev = aml_device("GPE0");
2184 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2185 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2186 /* device present, functioning, decoding, not shown in UI */
2187 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2188 crs = aml_resource_template();
2189 aml_append(crs,
ff80dc7f 2190 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
d31c909e
IM		 2191 );
2192 aml_append(dev, aml_name_decl("_CRS", crs));
2193 aml_append(scope, dev);
2194
dcdca296
MA		 2195 g_ptr_array_free(io_ranges, true);
2196 g_ptr_array_free(mem_ranges, true);
2197
500b11ea
IM		 2198 /* reserve PCIHP resources */
2199 if (pm->pcihp_io_len) {
2200 dev = aml_device("PHPR");
2201 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2202 aml_append(dev,
2203 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2204 /* device present, functioning, decoding, not shown in UI */
2205 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2206 crs = aml_resource_template();
2207 aml_append(crs,
ff80dc7f 2208 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
500b11ea
IM		 2209 pm->pcihp_io_len)
2210 );
2211 aml_append(dev, aml_name_decl("_CRS", crs));
2212 aml_append(scope, dev);
2213 }
41fa5c04 2214 aml_append(dsdt, scope);
500b11ea 2215
ebc3028f
IM		 2216 /* create S3_ / S4_ / S5_ packages if necessary */
2217 scope = aml_scope("\\");
2218 if (!pm->s3_disabled) {
2219 pkg = aml_package(4);
2220 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2221 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2222 aml_append(pkg, aml_int(0)); /* reserved */
2223 aml_append(pkg, aml_int(0)); /* reserved */
2224 aml_append(scope, aml_name_decl("_S3", pkg));
2225 }
2226
2227 if (!pm->s4_disabled) {
2228 pkg = aml_package(4);
2229 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2230 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2231 aml_append(pkg, aml_int(pm->s4_val));
2232 aml_append(pkg, aml_int(0)); /* reserved */
2233 aml_append(pkg, aml_int(0)); /* reserved */
2234 aml_append(scope, aml_name_decl("_S4", pkg));
2235 }
2236
2237 pkg = aml_package(4);
2238 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2239 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2240 aml_append(pkg, aml_int(0)); /* reserved */
2241 aml_append(pkg, aml_int(0)); /* reserved */
2242 aml_append(scope, aml_name_decl("_S5", pkg));
41fa5c04 2243 aml_append(dsdt, scope);
ebc3028f 2244
e2ec7568
GS		 2245 /* create fw_cfg node, unconditionally */
2246 {
2247 /* when using port i/o, the 8-bit data register *always* overlaps
2248 * with half of the 16-bit control register. Hence, the total size
2249 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2250 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2251 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2252 "dma_enabled", NULL) ?
2253 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2254 FW_CFG_CTL_SIZE;
2255
2256 scope = aml_scope("\\_SB.PCI0");
2257 dev = aml_device("FWCF");
2258
2259 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2260
2261 /* device present, functioning, decoding, not shown in UI */
2262 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2263
2264 crs = aml_resource_template();
2265 aml_append(crs,
2266 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2267 );
2268 aml_append(dev, aml_name_decl("_CRS", crs));
2269
2270 aml_append(scope, dev);
2271 aml_append(dsdt, scope);
2272 }
2273
8ac6f7a6
IM		 2274 if (misc->applesmc_io_base) {
2275 scope = aml_scope("\\_SB.PCI0.ISA");
2276 dev = aml_device("SMC");
2277
2278 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2279 /* device present, functioning, decoding, not shown in UI */
2280 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2281
2282 crs = aml_resource_template();
2283 aml_append(crs,
ff80dc7f 2284 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
8ac6f7a6
IM		 2285 0x01, APPLESMC_MAX_DATA_LENGTH)
2286 );
2287 aml_append(crs, aml_irq_no_flags(6));
2288 aml_append(dev, aml_name_decl("_CRS", crs));
2289
2290 aml_append(scope, dev);
41fa5c04 2291 aml_append(dsdt, scope);
8ac6f7a6
IM		 2292 }
2293
cd61cb2e
IM		 2294 if (misc->pvpanic_port) {
2295 scope = aml_scope("\\_SB.PCI0.ISA");
2296
2332333c 2297 dev = aml_device("PEVT");
e65bef69 2298 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
cd61cb2e
IM		 2299
2300 crs = aml_resource_template();
2301 aml_append(crs,
ff80dc7f 2302 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
cd61cb2e
IM		 2303 );
2304 aml_append(dev, aml_name_decl("_CRS", crs));
2305
ff80dc7f 2306 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
3f3009c0 2307 aml_int(misc->pvpanic_port), 1));
36de884a 2308 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
cd61cb2e
IM		 2309 aml_append(field, aml_named_field("PEPT", 8));
2310 aml_append(dev, field);
2311
8ef3ea25
GH		 2312 /* device present, functioning, decoding, shown in UI */
2313 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2332333c 2314
4dbfc881 2315 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
cd61cb2e
IM		 2316 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2317 aml_append(method, aml_return(aml_local(0)));
2318 aml_append(dev, method);
2319
4dbfc881 2320 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
cd61cb2e
IM		 2321 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2322 aml_append(dev, method);
2323
2324 aml_append(scope, dev);
41fa5c04 2325 aml_append(dsdt, scope);
cd61cb2e
IM		 2326 }
2327
7824df38 2328 sb_scope = aml_scope("\\_SB");
72c194f7 2329 {
dd4c2f01 2330 build_processor_devices(sb_scope, pcms->apic_id_limit, cpu, pm);
72c194f7 2331
f177d40a
IM		 2332 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2333 pm->mem_hp_io_len);
8698c0c0 2334
72c194f7 2335 {
8dcf525a
MT		 2336 Object *pci_host;
2337 PCIBus *bus = NULL;
8dcf525a 2338
ca6c1855
MA		 2339 pci_host = acpi_get_i386_pci_host();
2340 if (pci_host) {
8dcf525a
MT		 2341 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2342 }
72c194f7 2343
99fd437d 2344 if (bus) {
62b52c26 2345 Aml *scope = aml_scope("PCI0");
99fd437d 2346 /* Scan all PCI buses. Generate tables to support hotplug. */
62b52c26 2347 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
72d97b3a
IM		 2348
2349 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2350 dev = aml_device("ISA.TPM");
2351 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2352 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2353 crs = aml_resource_template();
2354 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2355 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2356 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
2357 aml_append(dev, aml_name_decl("_CRS", crs));
2358 aml_append(scope, dev);
2359 }
2360
62b52c26 2361 aml_append(sb_scope, scope);
72c194f7 2362 }
72c194f7 2363 }
41fa5c04 2364 aml_append(dsdt, sb_scope);
72c194f7
MT		 2365 }
2366
011bb749 2367 /* copy AML table into ACPI tables blob and patch header there */
41fa5c04 2368 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
72c194f7 2369 build_header(linker, table_data,
41fa5c04 2370 (void *)(table_data->data + table_data->len - dsdt->buf->len),
37ad223c 2371 "DSDT", dsdt->buf->len, 1, NULL, NULL);
011bb749 2372 free_aml_allocator();
72c194f7
MT		 2373}
2374
2375static void
2376build_hpet(GArray *table_data, GArray *linker)
2377{
2378 Acpi20Hpet *hpet;
2379
2380 hpet = acpi_data_push(table_data, sizeof(*hpet));
2381 /* Note timer_block_id value must be kept in sync with value advertised by
2382 * emulated hpet
2383 */
2384 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2385 hpet->addr.address = cpu_to_le64(HPET_BASE);
2386 build_header(linker, table_data,
37ad223c 2387 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
72c194f7
MT		 2388}
2389
711b20b4 2390static void
42a5b308 2391build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
711b20b4
SB		 2392{
2393 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
42a5b308 2394 uint64_t log_area_start_address = acpi_data_len(tcpalog);
711b20b4
SB		 2395
2396 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2397 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2398 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
2399
42a5b308
SB		 2400 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
2401 false /* high memory */);
2402
711b20b4
SB		 2403 /* log area start address to be filled by Guest linker */
2404 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
42a5b308 2405 ACPI_BUILD_TPMLOG_FILE,
711b20b4
SB		 2406 table_data, &tcpa->log_area_start_address,
2407 sizeof(tcpa->log_area_start_address));
2408
2409 build_header(linker, table_data,
37ad223c 2410 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
711b20b4 2411
42a5b308 2412 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
711b20b4
SB		 2413}
2414
5cb18b3d
SB		 2415static void
2416build_tpm2(GArray *table_data, GArray *linker)
2417{
2418 Acpi20TPM2 *tpm2_ptr;
5cb18b3d
SB		 2419
2420 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2421
2422 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2423 tpm2_ptr->control_area_address = cpu_to_le64(0);
2424 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2425
2426 build_header(linker, table_data,
37ad223c 2427 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
5cb18b3d
SB		 2428}
2429
04ed3ea8
IM		 2430typedef enum {
2431 MEM_AFFINITY_NOFLAGS = 0,
2432 MEM_AFFINITY_ENABLED = (1 << 0),
2433 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
2434 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
2435} MemoryAffinityFlags;
2436
72c194f7 2437static void
04ed3ea8
IM		 2438acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
2439 uint64_t len, int node, MemoryAffinityFlags flags)
72c194f7
MT		 2440{
2441 numamem->type = ACPI_SRAT_MEMORY;
2442 numamem->length = sizeof(*numamem);
2443 memset(numamem->proximity, 0, 4);
2444 numamem->proximity[0] = node;
04ed3ea8 2445 numamem->flags = cpu_to_le32(flags);
72c194f7
MT		 2446 numamem->base_addr = cpu_to_le64(base);
2447 numamem->range_length = cpu_to_le64(len);
2448}
2449
2450static void
3d3ebcad 2451build_srat(GArray *table_data, GArray *linker, MachineState *machine)
72c194f7
MT		 2452{
2453 AcpiSystemResourceAffinityTable *srat;
2454 AcpiSratProcessorAffinity *core;
2455 AcpiSratMemoryAffinity *numamem;
2456
2457 int i;
2458 uint64_t curnode;
2459 int srat_start, numa_start, slots;
2460 uint64_t mem_len, mem_base, next_base;
5803fce3
IM		 2461 MachineClass *mc = MACHINE_GET_CLASS(machine);
2462 CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
3d3ebcad 2463 PCMachineState *pcms = PC_MACHINE(machine);
cec65193
IM		 2464 ram_addr_t hotplugabble_address_space_size =
2465 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2466 NULL);
72c194f7
MT		 2467
2468 srat_start = table_data->len;
2469
2470 srat = acpi_data_push(table_data, sizeof *srat);
2471 srat->reserved1 = cpu_to_le32(1);
72c194f7 2472
5803fce3
IM		 2473 for (i = 0; i < apic_ids->len; i++) {
2474 int apic_id = apic_ids->cpus[i].arch_id;
2475
72c194f7
MT		 2476 core = acpi_data_push(table_data, sizeof *core);
2477 core->type = ACPI_SRAT_PROCESSOR;
2478 core->length = sizeof(*core);
5803fce3
IM		 2479 core->local_apic_id = apic_id;
2480 curnode = pcms->node_cpu[apic_id];
72c194f7
MT		 2481 core->proximity_lo = curnode;
2482 memset(core->proximity_hi, 0, 3);
2483 core->local_sapic_eid = 0;
dd0247e0 2484 core->flags = cpu_to_le32(1);
72c194f7
MT		 2485 }
2486
2487
2488 /* the memory map is a bit tricky, it contains at least one hole
2489 * from 640k-1M and possibly another one from 3.5G-4G.
2490 */
2491 next_base = 0;
2492 numa_start = table_data->len;
2493
2494 numamem = acpi_data_push(table_data, sizeof *numamem);
04ed3ea8 2495 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
72c194f7 2496 next_base = 1024 * 1024;
dd4c2f01 2497 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
72c194f7 2498 mem_base = next_base;
dd4c2f01 2499 mem_len = pcms->node_mem[i - 1];
72c194f7
MT		 2500 if (i == 1) {
2501 mem_len -= 1024 * 1024;
2502 }
2503 next_base = mem_base + mem_len;
2504
2505 /* Cut out the ACPI_PCI hole */
5299f1c7
EH		 2506 if (mem_base <= pcms->below_4g_mem_size &&
2507 next_base > pcms->below_4g_mem_size) {
2508 mem_len -= next_base - pcms->below_4g_mem_size;
72c194f7
MT		 2509 if (mem_len > 0) {
2510 numamem = acpi_data_push(table_data, sizeof *numamem);
04ed3ea8
IM		 2511 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2512 MEM_AFFINITY_ENABLED);
72c194f7
MT		 2513 }
2514 mem_base = 1ULL << 32;
5299f1c7
EH		 2515 mem_len = next_base - pcms->below_4g_mem_size;
2516 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
72c194f7
MT		 2517 }
2518 numamem = acpi_data_push(table_data, sizeof *numamem);
04ed3ea8
IM		 2519 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2520 MEM_AFFINITY_ENABLED);
72c194f7
MT		 2521 }
2522 slots = (table_data->len - numa_start) / sizeof *numamem;
dd4c2f01 2523 for (; slots < pcms->numa_nodes + 2; slots++) {
72c194f7 2524 numamem = acpi_data_push(table_data, sizeof *numamem);
04ed3ea8 2525 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
72c194f7
MT		 2526 }
2527
cec65193
IM		 2528 /*
2529 * Entry is required for Windows to enable memory hotplug in OS.
2530 * Memory devices may override proximity set by this entry,
2531 * providing _PXM method if necessary.
2532 */
2533 if (hotplugabble_address_space_size) {
2534 numamem = acpi_data_push(table_data, sizeof *numamem);
a7d69ff1 2535 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
cec65193
IM		 2536 hotplugabble_address_space_size, 0,
2537 MEM_AFFINITY_HOTPLUGGABLE |
2538 MEM_AFFINITY_ENABLED);
2539 }
2540
72c194f7
MT		 2541 build_header(linker, table_data,
2542 (void *)(table_data->data + srat_start),
821e3227 2543 "SRAT",
37ad223c 2544 table_data->len - srat_start, 1, NULL, NULL);
5803fce3 2545 g_free(apic_ids);
72c194f7
MT		 2546}
2547
2548static void
2549build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
2550{
2551 AcpiTableMcfg *mcfg;
821e3227 2552 const char *sig;
72c194f7
MT		 2553 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2554
2555 mcfg = acpi_data_push(table_data, len);
2556 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2557 /* Only a single allocation so no need to play with segments */
2558 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2559 mcfg->allocation[0].start_bus_number = 0;
2560 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2561
2562 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2563 * To avoid table size changes (which create migration issues),
2564 * always create the table even if there are no allocations,
2565 * but set the signature to a reserved value in this case.
2566 * ACPI spec requires OSPMs to ignore such tables.
2567 */
2568 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
821e3227
MT		 2569 /* Reserved signature: ignored by OSPM */
2570 sig = "QEMU";
72c194f7 2571 } else {
821e3227 2572 sig = "MCFG";
72c194f7 2573 }
37ad223c 2574 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
72c194f7
MT		 2575}
2576
d4eb9119
LT		 2577static void
2578build_dmar_q35(GArray *table_data, GArray *linker)
2579{
2580 int dmar_start = table_data->len;
2581
2582 AcpiTableDmar *dmar;
2583 AcpiDmarHardwareUnit *drhd;
2584
2585 dmar = acpi_data_push(table_data, sizeof(*dmar));
2586 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2587 dmar->flags = 0; /* No intr_remap for now */
2588
2589 /* DMAR Remapping Hardware Unit Definition structure */
2590 drhd = acpi_data_push(table_data, sizeof(*drhd));
2591 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2592 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
2593 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2594 drhd->pci_segment = cpu_to_le16(0);
2595 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2596
2597 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
37ad223c 2598 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
d4eb9119
LT		 2599}
2600
72c194f7
MT		 2601static GArray *
2602build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
2603{
2604 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2605
d67aadcc 2606 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
72c194f7
MT		 2607 true /* fseg memory */);
2608
821e3227 2609 memcpy(&rsdp->signature, "RSD PTR ", 8);
72c194f7
MT		 2610 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2611 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
2612 /* Address to be filled by Guest linker */
2613 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
2614 ACPI_BUILD_TABLE_FILE,
2615 rsdp_table, &rsdp->rsdt_physical_address,
2616 sizeof rsdp->rsdt_physical_address);
2617 rsdp->checksum = 0;
2618 /* Checksum to be filled by Guest linker */
2619 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
b54ca0c3
MT		 2620 rsdp_table, rsdp, sizeof *rsdp,
2621 &rsdp->checksum);
72c194f7
MT		 2622
2623 return rsdp_table;
2624}
2625
72c194f7
MT		 2626typedef
2627struct AcpiBuildState {
2628 /* Copy of table in RAM (for patching). */
339240b5 2629 MemoryRegion *table_mr;
72c194f7
MT		 2630 /* Is table patched? */
2631 uint8_t patched;
d70414a5 2632 void *rsdp;
339240b5
PB		 2633 MemoryRegion *rsdp_mr;
2634 MemoryRegion *linker_mr;
72c194f7
MT		 2635} AcpiBuildState;
2636
2637static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2638{
2639 Object *pci_host;
2640 QObject *o;
72c194f7 2641
ca6c1855 2642 pci_host = acpi_get_i386_pci_host();
72c194f7
MT		 2643 g_assert(pci_host);
2644
2645 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2646 if (!o) {
2647 return false;
2648 }
2649 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
097a97a6 2650 qobject_decref(o);
72c194f7
MT		 2651
2652 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2653 assert(o);
2654 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
097a97a6 2655 qobject_decref(o);
72c194f7
MT		 2656 return true;
2657}
2658
d4eb9119
LT		 2659static bool acpi_has_iommu(void)
2660{
2661 bool ambiguous;
2662 Object *intel_iommu;
2663
2664 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
2665 &ambiguous);
2666 return intel_iommu && !ambiguous;
2667}
2668
72c194f7 2669static
3d3ebcad 2670void acpi_build(AcpiBuildTables *tables, MachineState *machine)
72c194f7 2671{
3d3ebcad 2672 PCMachineState *pcms = PC_MACHINE(machine);
bb292f5a 2673 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72c194f7 2674 GArray *table_offsets;
41fa5c04 2675 unsigned facs, dsdt, rsdt, fadt;
72c194f7
MT		 2676 AcpiCpuInfo cpu;
2677 AcpiPmInfo pm;
2678 AcpiMiscInfo misc;
2679 AcpiMcfgInfo mcfg;
2680 PcPciInfo pci;
2681 uint8_t *u;
07fb6176 2682 size_t aml_len = 0;
7c2c1fa5 2683 GArray *tables_blob = tables->table_data;
ae123749 2684 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
72c194f7
MT		 2685
2686 acpi_get_cpu_info(&cpu);
2687 acpi_get_pm_info(&pm);
72c194f7
MT		 2688 acpi_get_misc_info(&misc);
2689 acpi_get_pci_info(&pci);
ae123749 2690 acpi_get_slic_oem(&slic_oem);
72c194f7
MT		 2691
2692 table_offsets = g_array_new(false, true /* clear */,
2693 sizeof(uint32_t));
8b310fc4 2694 ACPI_BUILD_DPRINTF("init ACPI tables\n");
72c194f7
MT		 2695
2696 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
2697 64 /* Ensure FACS is aligned */,
2698 false /* high memory */);
2699
2700 /*
2701 * FACS is pointed to by FADT.
2702 * We place it first since it's the only table that has alignment
2703 * requirements.
2704 */
7c2c1fa5 2705 facs = tables_blob->len;
fb306ffe 2706 build_facs(tables_blob, tables->linker);
72c194f7
MT		 2707
2708 /* DSDT is pointed to by FADT */
7c2c1fa5 2709 dsdt = tables_blob->len;
3d3ebcad 2710 build_dsdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci, machine);
72c194f7 2711
07fb6176
PB		 2712 /* Count the size of the DSDT and SSDT, we will need it for legacy
2713 * sizing of ACPI tables.
2714 */
7c2c1fa5 2715 aml_len += tables_blob->len - dsdt;
07fb6176 2716
72c194f7 2717 /* ACPI tables pointed to by RSDT */
41fa5c04 2718 fadt = tables_blob->len;
7c2c1fa5 2719 acpi_add_table(table_offsets, tables_blob);
ae123749
LE		 2720 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2721 slic_oem.id, slic_oem.table_id);
41fa5c04 2722 aml_len += tables_blob->len - fadt;
72c194f7 2723
7c2c1fa5 2724 acpi_add_table(table_offsets, tables_blob);
907e7c94 2725 build_madt(tables_blob, tables->linker, pcms);
9ac1c4c0 2726
72c194f7 2727 if (misc.has_hpet) {
7c2c1fa5
IM		 2728 acpi_add_table(table_offsets, tables_blob);
2729 build_hpet(tables_blob, tables->linker);
711b20b4 2730 }
5cb18b3d 2731 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
7c2c1fa5
IM		 2732 acpi_add_table(table_offsets, tables_blob);
2733 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
711b20b4 2734
72d97b3a
IM		 2735 if (misc.tpm_version == TPM_VERSION_2_0) {
2736 acpi_add_table(table_offsets, tables_blob);
5cb18b3d 2737 build_tpm2(tables_blob, tables->linker);
5cb18b3d 2738 }
72c194f7 2739 }
dd4c2f01 2740 if (pcms->numa_nodes) {
7c2c1fa5 2741 acpi_add_table(table_offsets, tables_blob);
3d3ebcad 2742 build_srat(tables_blob, tables->linker, machine);
72c194f7
MT		 2743 }
2744 if (acpi_get_mcfg(&mcfg)) {
7c2c1fa5
IM		 2745 acpi_add_table(table_offsets, tables_blob);
2746 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
72c194f7 2747 }
d4eb9119 2748 if (acpi_has_iommu()) {
7c2c1fa5
IM		 2749 acpi_add_table(table_offsets, tables_blob);
2750 build_dmar_q35(tables_blob, tables->linker);
d4eb9119 2751 }
5fe79386 2752 if (pcms->acpi_nvdimm_state.is_enabled) {
87252e1b
XG		 2753 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
2754 }
2755
72c194f7
MT		 2756 /* Add tables supplied by user (if any) */
2757 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2758 unsigned len = acpi_table_len(u);
2759
7c2c1fa5
IM		 2760 acpi_add_table(table_offsets, tables_blob);
2761 g_array_append_vals(tables_blob, u, len);
72c194f7
MT		 2762 }
2763
2764 /* RSDT is pointed to by RSDP */
7c2c1fa5 2765 rsdt = tables_blob->len;
ae123749
LE		 2766 build_rsdt(tables_blob, tables->linker, table_offsets,
2767 slic_oem.id, slic_oem.table_id);
72c194f7
MT		 2768
2769 /* RSDP is in FSEG memory, so allocate it separately */
2770 build_rsdp(tables->rsdp, tables->linker, rsdt);
2771
07fb6176 2772 /* We'll expose it all to Guest so we want to reduce
72c194f7 2773 * chance of size changes.
07fb6176
PB		 2774 *
2775 * We used to align the tables to 4k, but of course this would
2776 * too simple to be enough. 4k turned out to be too small an
2777 * alignment very soon, and in fact it is almost impossible to
2778 * keep the table size stable for all (max_cpus, max_memory_slots)
2779 * combinations. So the table size is always 64k for pc-i440fx-2.1
2780 * and we give an error if the table grows beyond that limit.
2781 *
2782 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2783 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2784 * than 2.0 and we can always pad the smaller tables with zeros. We can
2785 * then use the exact size of the 2.0 tables.
2786 *
2787 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
72c194f7 2788 */
bb292f5a 2789 if (pcmc->legacy_acpi_table_size) {
07fb6176
PB		 2790 /* Subtracting aml_len gives the size of fixed tables. Then add the
2791 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2792 */
2793 int legacy_aml_len =
bb292f5a 2794 pcmc->legacy_acpi_table_size +
07fb6176
PB		 2795 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2796 int legacy_table_size =
7c2c1fa5 2797 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
07fb6176 2798 ACPI_BUILD_ALIGN_SIZE);
7c2c1fa5 2799 if (tables_blob->len > legacy_table_size) {
07fb6176 2800 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
868270f2 2801 error_report("Warning: migration may not work.");
07fb6176 2802 }
7c2c1fa5 2803 g_array_set_size(tables_blob, legacy_table_size);
07fb6176 2804 } else {
868270f2 2805 /* Make sure we have a buffer in case we need to resize the tables. */
7c2c1fa5 2806 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
18045fb9 2807 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
868270f2
MT		 2808 error_report("Warning: ACPI tables are larger than 64k.");
2809 error_report("Warning: migration may not work.");
2810 error_report("Warning: please remove CPUs, NUMA nodes, "
2811 "memory slots or PCI bridges.");
18045fb9 2812 }
7c2c1fa5 2813 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
07fb6176 2814 }
72c194f7 2815
07fb6176 2816 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
72c194f7
MT		 2817
2818 /* Cleanup memory that's no longer used. */
2819 g_array_free(table_offsets, true);
2820}
2821
339240b5 2822static void acpi_ram_update(MemoryRegion *mr, GArray *data)
42d85900
MT		 2823{
2824 uint32_t size = acpi_data_len(data);
2825
2826 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
339240b5 2827 memory_region_ram_resize(mr, size, &error_abort);
42d85900 2828
339240b5
PB		 2829 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2830 memory_region_set_dirty(mr, 0, size);
42d85900
MT		 2831}
2832
3f8752b4 2833static void acpi_build_update(void *build_opaque)
72c194f7
MT		 2834{
2835 AcpiBuildState *build_state = build_opaque;
2836 AcpiBuildTables tables;
2837
2838 /* No state to update or already patched? Nothing to do. */
2839 if (!build_state || build_state->patched) {
2840 return;
2841 }
2842 build_state->patched = 1;
2843
2844 acpi_build_tables_init(&tables);
2845
3d3ebcad 2846 acpi_build(&tables, MACHINE(qdev_get_machine()));
72c194f7 2847
339240b5 2848 acpi_ram_update(build_state->table_mr, tables.table_data);
a1666142 2849
42d85900
MT		 2850 if (build_state->rsdp) {
2851 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2852 } else {
339240b5 2853 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
42d85900 2854 }
ad5b88b1 2855
339240b5 2856 acpi_ram_update(build_state->linker_mr, tables.linker);
72c194f7
MT		 2857 acpi_build_tables_cleanup(&tables, true);
2858}
2859
2860static void acpi_build_reset(void *build_opaque)
2861{
2862 AcpiBuildState *build_state = build_opaque;
2863 build_state->patched = 0;
2864}
2865
339240b5
PB		 2866static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2867 GArray *blob, const char *name,
2868 uint64_t max_size)
72c194f7 2869{
a1666142
MT		 2870 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2871 name, acpi_build_update, build_state);
72c194f7
MT		 2872}
2873
2874static const VMStateDescription vmstate_acpi_build = {
2875 .name = "acpi_build",
2876 .version_id = 1,
2877 .minimum_version_id = 1,
d49805ae 2878 .fields = (VMStateField[]) {
72c194f7
MT		 2879 VMSTATE_UINT8(patched, AcpiBuildState),
2880 VMSTATE_END_OF_LIST()
2881 },
2882};
2883
fb306ffe 2884void acpi_setup(void)
72c194f7 2885{
fb306ffe 2886 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
bb292f5a 2887 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
72c194f7
MT		 2888 AcpiBuildTables tables;
2889 AcpiBuildState *build_state;
2890
f264d360 2891 if (!pcms->fw_cfg) {
8b310fc4 2892 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
72c194f7
MT		 2893 return;
2894 }
2895
bb292f5a 2896 if (!pcmc->has_acpi_build) {
8b310fc4 2897 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
72c194f7
MT		 2898 return;
2899 }
2900
81adc513 2901 if (!acpi_enabled) {
8b310fc4 2902 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
81adc513
MT		 2903 return;
2904 }
2905
72c194f7
MT		 2906 build_state = g_malloc0(sizeof *build_state);
2907
99fd437d
MT		 2908 acpi_set_pci_info();
2909
72c194f7 2910 acpi_build_tables_init(&tables);
3d3ebcad 2911 acpi_build(&tables, MACHINE(pcms));
72c194f7
MT		 2912
2913 /* Now expose it all to Guest */
339240b5 2914 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
a1666142
MT		 2915 ACPI_BUILD_TABLE_FILE,
2916 ACPI_BUILD_TABLE_MAX_SIZE);
339240b5 2917 assert(build_state->table_mr != NULL);
72c194f7 2918
339240b5 2919 build_state->linker_mr =
6e00619b 2920 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
72c194f7 2921
f264d360 2922 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
42a5b308
SB		 2923 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2924
bb292f5a 2925 if (!pcmc->rsdp_in_ram) {
358774d7
IM		 2926 /*
2927 * Keep for compatibility with old machine types.
2928 * Though RSDP is small, its contents isn't immutable, so
afaa2e4b 2929 * we'll update it along with the rest of tables on guest access.
358774d7 2930 */
afaa2e4b
MT		 2931 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2932
2933 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
f264d360 2934 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
358774d7 2935 acpi_build_update, build_state,
afaa2e4b 2936 build_state->rsdp, rsdp_size);
339240b5 2937 build_state->rsdp_mr = NULL;
358774d7 2938 } else {
42d85900 2939 build_state->rsdp = NULL;
339240b5 2940 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
42d85900 2941 ACPI_BUILD_RSDP_FILE, 0);
358774d7 2942 }
72c194f7
MT		 2943
2944 qemu_register_reset(acpi_build_reset, build_state);
2945 acpi_build_reset(build_state);
2946 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2947
2948 /* Cleanup tables but don't free the memory: we track it
2949 * in build_state.
2950 */
2951 acpi_build_tables_cleanup(&tables, false);
2952}
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