[qemu.git] / hw / ppc / spapr_cpu_core.c

/*
 * sPAPR CPU core device, acts as container of CPU thread devices.
 *
 * Copyright (C) 2016 Bharata B Rao <[email protected]>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */
#include "qemu/osdep.h"
#include "hw/cpu/core.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "target/ppc/cpu.h"
#include "hw/ppc/spapr.h"
#include "hw/boards.h"
#include "qapi/error.h"
#include "sysemu/cpus.h"
#include "sysemu/kvm.h"
#include "target/ppc/kvm_ppc.h"
#include "hw/ppc/ppc.h"
#include "target/ppc/mmu-hash64.h"
#include "sysemu/numa.h"
#include "sysemu/hw_accel.h"
#include "qemu/error-report.h"

static void spapr_cpu_reset(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUState *cs = CPU(cpu);
    CPUPPCState *env = &cpu->env;
    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
    sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
    target_ulong lpcr;

    cpu_reset(cs);

    /* All CPUs start halted.  CPU0 is unhalted from the machine level
     * reset code and the rest are explicitly started up by the guest
     * using an RTAS call */
    cs->halted = 1;

    /* Set compatibility mode to match the boot CPU, which was either set
     * by the machine reset code or by CAS. This should never fail.
     */
    ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);

    env->spr[SPR_HIOR] = 0;

    lpcr = env->spr[SPR_LPCR];

    /* Set emulated LPCR to not send interrupts to hypervisor. Note that
     * under KVM, the actual HW LPCR will be set differently by KVM itself,
     * the settings below ensure proper operations with TCG in absence of
     * a real hypervisor.
     *
     * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
     * real mode accesses, which thankfully defaults to 0 and isn't
     * accessible in guest mode.
     *
     * Disable Power-saving mode Exit Cause exceptions for the CPU, so
     * we don't get spurious wakups before an RTAS start-cpu call.
     */
    lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
    lpcr |= LPCR_LPES0 | LPCR_LPES1;

    /* Set RMLS to the max (ie, 16G) */
    lpcr &= ~LPCR_RMLS;
    lpcr |= 1ull << LPCR_RMLS_SHIFT;

    ppc_store_lpcr(cpu, lpcr);

    /* Set a full AMOR so guest can use the AMR as it sees fit */
    env->spr[SPR_AMOR] = 0xffffffffffffffffull;

    spapr_cpu->vpa_addr = 0;
    spapr_cpu->slb_shadow_addr = 0;
    spapr_cpu->slb_shadow_size = 0;
    spapr_cpu->dtl_addr = 0;
    spapr_cpu->dtl_size = 0;

    spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu);

    kvm_check_mmu(cpu, &error_fatal);
}

void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
{
    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
    CPUPPCState *env = &cpu->env;

    env->nip = nip;
    env->gpr[3] = r3;
    kvmppc_set_reg_ppc_online(cpu, 1);
    CPU(cpu)->halted = 0;
    /* Enable Power-saving mode Exit Cause exceptions */
    ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
}

/*
 * Return the sPAPR CPU core type for @model which essentially is the CPU
 * model specified with -cpu cmdline option.
 */
const char *spapr_get_cpu_core_type(const char *cpu_type)
{
    int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
    char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
                                      len, cpu_type);
    ObjectClass *oc = object_class_by_name(core_type);

    g_free(core_type);
    if (!oc) {
        return NULL;
    }

    return object_class_get_name(oc);
}

static bool slb_shadow_needed(void *opaque)
{
    sPAPRCPUState *spapr_cpu = opaque;

    return spapr_cpu->slb_shadow_addr != 0;
}

static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
    .name = "spapr_cpu/vpa/slb_shadow",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = slb_shadow_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(slb_shadow_addr, sPAPRCPUState),
        VMSTATE_UINT64(slb_shadow_size, sPAPRCPUState),
        VMSTATE_END_OF_LIST()
    }
};

static bool dtl_needed(void *opaque)
{
    sPAPRCPUState *spapr_cpu = opaque;

    return spapr_cpu->dtl_addr != 0;
}

static const VMStateDescription vmstate_spapr_cpu_dtl = {
    .name = "spapr_cpu/vpa/dtl",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = dtl_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(dtl_addr, sPAPRCPUState),
        VMSTATE_UINT64(dtl_size, sPAPRCPUState),
        VMSTATE_END_OF_LIST()
    }
};

static bool vpa_needed(void *opaque)
{
    sPAPRCPUState *spapr_cpu = opaque;

    return spapr_cpu->vpa_addr != 0;
}

static const VMStateDescription vmstate_spapr_cpu_vpa = {
    .name = "spapr_cpu/vpa",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = vpa_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(vpa_addr, sPAPRCPUState),
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription * []) {
        &vmstate_spapr_cpu_slb_shadow,
        &vmstate_spapr_cpu_dtl,
        NULL
    }
};

static const VMStateDescription vmstate_spapr_cpu_state = {
    .name = "spapr_cpu",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_END_OF_LIST()
    },
    .subsections = (const VMStateDescription * []) {
        &vmstate_spapr_cpu_vpa,
        NULL
    }
};

static void spapr_unrealize_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc)
{
    if (!sc->pre_3_0_migration) {
        vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
    }
    qemu_unregister_reset(spapr_cpu_reset, cpu);
    object_unparent(cpu->intc);
    cpu_remove_sync(CPU(cpu));
    object_unparent(OBJECT(cpu));
}

static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp)
{
    sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
    CPUCore *cc = CPU_CORE(dev);
    int i;

    for (i = 0; i < cc->nr_threads; i++) {
        spapr_unrealize_vcpu(sc->threads[i], sc);
    }
    g_free(sc->threads);
}

static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr,
                               sPAPRCPUCore *sc, Error **errp)
{
    CPUPPCState *env = &cpu->env;
    CPUState *cs = CPU(cpu);
    Error *local_err = NULL;

    object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
    if (local_err) {
        goto error;
    }

    /* Set time-base frequency to 512 MHz */
    cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);

    cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
    kvmppc_set_papr(cpu);

    qemu_register_reset(spapr_cpu_reset, cpu);
    spapr_cpu_reset(cpu);

    spapr->irq->cpu_intc_create(spapr, cpu, &local_err);
    if (local_err) {
        goto error_unregister;
    }

    if (!sc->pre_3_0_migration) {
        vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
                         cpu->machine_data);
    }

    return;

error_unregister:
    qemu_unregister_reset(spapr_cpu_reset, cpu);
    cpu_remove_sync(CPU(cpu));
error:
    error_propagate(errp, local_err);
}

static PowerPCCPU *spapr_create_vcpu(sPAPRCPUCore *sc, int i, Error **errp)
{
    sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
    CPUCore *cc = CPU_CORE(sc);
    Object *obj;
    char *id;
    CPUState *cs;
    PowerPCCPU *cpu;
    Error *local_err = NULL;

    obj = object_new(scc->cpu_type);

    cs = CPU(obj);
    cpu = POWERPC_CPU(obj);
    cs->cpu_index = cc->core_id + i;
    spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
    if (local_err) {
        goto err;
    }

    cpu->node_id = sc->node_id;

    id = g_strdup_printf("thread[%d]", i);
    object_property_add_child(OBJECT(sc), id, obj, &local_err);
    g_free(id);
    if (local_err) {
        goto err;
    }

    cpu->machine_data = g_new0(sPAPRCPUState, 1);

    object_unref(obj);
    return cpu;

err:
    object_unref(obj);
    error_propagate(errp, local_err);
    return NULL;
}

static void spapr_delete_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc)
{
    sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);

    cpu->machine_data = NULL;
    g_free(spapr_cpu);
    object_unparent(OBJECT(cpu));
}

static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
{
    /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
     * tries to add a sPAPR CPU core to a non-pseries machine.
     */
    sPAPRMachineState *spapr =
        (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(),
                                                  TYPE_SPAPR_MACHINE);
    sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
    CPUCore *cc = CPU_CORE(OBJECT(dev));
    Error *local_err = NULL;
    int i, j;

    if (!spapr) {
        error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
        return;
    }

    sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
    for (i = 0; i < cc->nr_threads; i++) {
        sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
        if (local_err) {
            goto err;
        }
    }

    for (j = 0; j < cc->nr_threads; j++) {
        spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err);
        if (local_err) {
            goto err_unrealize;
        }
    }
    return;

err_unrealize:
    while (--j >= 0) {
        spapr_unrealize_vcpu(sc->threads[j], sc);
    }
err:
    while (--i >= 0) {
        spapr_delete_vcpu(sc->threads[i], sc);
    }
    g_free(sc->threads);
    error_propagate(errp, local_err);
}

static Property spapr_cpu_core_properties[] = {
    DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID),
    DEFINE_PROP_BOOL("pre-3.0-migration", sPAPRCPUCore, pre_3_0_migration,
                     false),
    DEFINE_PROP_END_OF_LIST()
};

static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);
    sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);

    dc->realize = spapr_cpu_core_realize;
    dc->unrealize = spapr_cpu_core_unrealize;
    dc->props = spapr_cpu_core_properties;
    scc->cpu_type = data;
}

#define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
    {                                                   \
        .parent = TYPE_SPAPR_CPU_CORE,                  \
        .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
        .class_init = spapr_cpu_core_class_init,        \
        .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model),    \
    }

static const TypeInfo spapr_cpu_core_type_infos[] = {
    {
        .name = TYPE_SPAPR_CPU_CORE,
        .parent = TYPE_CPU_CORE,
        .abstract = true,
        .instance_size = sizeof(sPAPRCPUCore),
        .class_size = sizeof(sPAPRCPUCoreClass),
    },
    DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
    DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
    DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
    DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
    DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
    DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
    DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
    DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
    DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
    DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
    DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
#ifdef CONFIG_KVM
    DEFINE_SPAPR_CPU_CORE_TYPE("host"),
#endif
};

DEFINE_TYPES(spapr_cpu_core_type_infos)
Commit	Line	Data
3b542549 BR	1	/*
	2	* sPAPR CPU core device, acts as container of CPU thread devices.
	3	*
	4	* Copyright (C) 2016 Bharata B Rao <[email protected]>
	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	7	* See the COPYING file in the top-level directory.
	8	*/
e9808d09	9	#include "qemu/osdep.h"
3b542549 BR	10	#include "hw/cpu/core.h"
3b542549 BR	11	#include "hw/ppc/spapr_cpu_core.h"
fcf5ef2a	12	#include "target/ppc/cpu.h"
3b542549 BR	13	#include "hw/ppc/spapr.h"
	14	#include "hw/boards.h"
	15	#include "qapi/error.h"
a9c94277	16	#include "sysemu/cpus.h"
e57ca75c	17	#include "sysemu/kvm.h"
fcf5ef2a	18	#include "target/ppc/kvm_ppc.h"
afd10a0f	19	#include "hw/ppc/ppc.h"
fcf5ef2a	20	#include "target/ppc/mmu-hash64.h"
a9c94277	21	#include "sysemu/numa.h"
1ec26c75	22	#include "sysemu/hw_accel.h"
e57ca75c	23	#include "qemu/error-report.h"
afd10a0f BR	24
	25	static void spapr_cpu_reset(void *opaque)
	26	{
afd10a0f BR	27	PowerPCCPU *cpu = opaque;
	28	CPUState *cs = CPU(cpu);
	29	CPUPPCState *env = &cpu->env;
d6322252	30	PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7388efaf	31	sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
da20aed1	32	target_ulong lpcr;
afd10a0f BR	33
	34	cpu_reset(cs);
	35
	36	/* All CPUs start halted. CPU0 is unhalted from the machine level
	37	* reset code and the rest are explicitly started up by the guest
	38	* using an RTAS call */
	39	cs->halted = 1;
	40
b12a4efb JRZ	41	/* Set compatibility mode to match the boot CPU, which was either set
	42	* by the machine reset code or by CAS. This should never fail.
	43	*/
	44	ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
	45
afd10a0f	46	env->spr[SPR_HIOR] = 0;
d6322252	47
da20aed1 DG	48	lpcr = env->spr[SPR_LPCR];
	49
	50	/* Set emulated LPCR to not send interrupts to hypervisor. Note that
	51	* under KVM, the actual HW LPCR will be set differently by KVM itself,
	52	* the settings below ensure proper operations with TCG in absence of
	53	* a real hypervisor.
	54	*
	55	* Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
	56	* real mode accesses, which thankfully defaults to 0 and isn't
	57	* accessible in guest mode.
47a9b551 DG	58	*
	59	* Disable Power-saving mode Exit Cause exceptions for the CPU, so
	60	* we don't get spurious wakups before an RTAS start-cpu call.
da20aed1	61	*/
47a9b551	62	lpcr &= ~(LPCR_VPM0 \| LPCR_VPM1 \| LPCR_ISL \| LPCR_KBV \| pcc->lpcr_pm);
da20aed1 DG	63	lpcr \|= LPCR_LPES0 \| LPCR_LPES1;
	64
	65	/* Set RMLS to the max (ie, 16G) */
	66	lpcr &= ~LPCR_RMLS;
	67	lpcr \|= 1ull << LPCR_RMLS_SHIFT;
	68
da20aed1 DG	69	ppc_store_lpcr(cpu, lpcr);
	70
	71	/* Set a full AMOR so guest can use the AMR as it sees fit */
	72	env->spr[SPR_AMOR] = 0xffffffffffffffffull;
7388efaf DG	73
	74	spapr_cpu->vpa_addr = 0;
	75	spapr_cpu->slb_shadow_addr = 0;
	76	spapr_cpu->slb_shadow_size = 0;
	77	spapr_cpu->dtl_addr = 0;
	78	spapr_cpu->dtl_size = 0;
e2e4f641 DG	79
e2e4f641 DG	80	spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu);
e5ca28ec DG	81
e5ca28ec DG	82	kvm_check_mmu(cpu, &error_fatal);
afd10a0f BR	83	}
afd10a0f BR	84
84369f63 DG	85	void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
84369f63 DG	86	{
47a9b551	87	PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
84369f63 DG	88	CPUPPCState *env = &cpu->env;
	89
	90	env->nip = nip;
	91	env->gpr[3] = r3;
a84f7179	92	kvmppc_set_reg_ppc_online(cpu, 1);
84369f63	93	CPU(cpu)->halted = 0;
47a9b551 DG	94	/* Enable Power-saving mode Exit Cause exceptions */
47a9b551 DG	95	ppc_store_lpcr(cpu, env->spr[SPR_LPCR] \| pcc->lpcr_pm);
84369f63 DG	96	}
84369f63 DG	97
94a94e4c BR	98	/*
	99	* Return the sPAPR CPU core type for @model which essentially is the CPU
	100	* model specified with -cpu cmdline option.
	101	*/
2e9c10eb	102	const char spapr_get_cpu_core_type(const char cpu_type)
94a94e4c	103	{
2e9c10eb IM	104	int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
	105	char core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.s"),
	106	len, cpu_type);
	107	ObjectClass *oc = object_class_by_name(core_type);
	108
	109	g_free(core_type);
	110	if (!oc) {
	111	return NULL;
4babfaf0 TH	112	}
4babfaf0 TH	113
2e9c10eb	114	return object_class_get_name(oc);
94a94e4c BR	115	}
94a94e4c BR	116
7f9fe3f0 GK	117	static bool slb_shadow_needed(void *opaque)
	118	{
	119	sPAPRCPUState *spapr_cpu = opaque;
	120
	121	return spapr_cpu->slb_shadow_addr != 0;
	122	}
	123
	124	static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
	125	.name = "spapr_cpu/vpa/slb_shadow",
	126	.version_id = 1,
	127	.minimum_version_id = 1,
	128	.needed = slb_shadow_needed,
	129	.fields = (VMStateField[]) {
	130	VMSTATE_UINT64(slb_shadow_addr, sPAPRCPUState),
	131	VMSTATE_UINT64(slb_shadow_size, sPAPRCPUState),
	132	VMSTATE_END_OF_LIST()
	133	}
	134	};
	135
	136	static bool dtl_needed(void *opaque)
	137	{
	138	sPAPRCPUState *spapr_cpu = opaque;
	139
	140	return spapr_cpu->dtl_addr != 0;
	141	}
	142
	143	static const VMStateDescription vmstate_spapr_cpu_dtl = {
	144	.name = "spapr_cpu/vpa/dtl",
	145	.version_id = 1,
	146	.minimum_version_id = 1,
	147	.needed = dtl_needed,
	148	.fields = (VMStateField[]) {
	149	VMSTATE_UINT64(dtl_addr, sPAPRCPUState),
	150	VMSTATE_UINT64(dtl_size, sPAPRCPUState),
	151	VMSTATE_END_OF_LIST()
	152	}
	153	};
	154
	155	static bool vpa_needed(void *opaque)
	156	{
	157	sPAPRCPUState *spapr_cpu = opaque;
	158
	159	return spapr_cpu->vpa_addr != 0;
	160	}
	161
	162	static const VMStateDescription vmstate_spapr_cpu_vpa = {
	163	.name = "spapr_cpu/vpa",
	164	.version_id = 1,
	165	.minimum_version_id = 1,
	166	.needed = vpa_needed,
	167	.fields = (VMStateField[]) {
	168	VMSTATE_UINT64(vpa_addr, sPAPRCPUState),
	169	VMSTATE_END_OF_LIST()
	170	},
	171	.subsections = (const VMStateDescription * []) {
	172	&vmstate_spapr_cpu_slb_shadow,
	173	&vmstate_spapr_cpu_dtl,
	174	NULL
	175	}
	176	};
	177
b9402026 GK	178	static const VMStateDescription vmstate_spapr_cpu_state = {
	179	.name = "spapr_cpu",
	180	.version_id = 1,
	181	.minimum_version_id = 1,
	182	.fields = (VMStateField[]) {
	183	VMSTATE_END_OF_LIST()
	184	},
7f9fe3f0 GK	185	.subsections = (const VMStateDescription * []) {
	186	&vmstate_spapr_cpu_vpa,
	187	NULL
	188	}
b9402026 GK	189	};
b9402026 GK	190
cc71c776 BR	191	static void spapr_unrealize_vcpu(PowerPCCPU cpu, sPAPRCPUCore sc)
	192	{
	193	if (!sc->pre_3_0_migration) {
	194	vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
	195	}
	196	qemu_unregister_reset(spapr_cpu_reset, cpu);
	197	object_unparent(cpu->intc);
	198	cpu_remove_sync(CPU(cpu));
	199	object_unparent(OBJECT(cpu));
	200	}
	201
	202	static void spapr_cpu_core_unrealize(DeviceState dev, Error *errp)
	203	{
	204	sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
	205	CPUCore *cc = CPU_CORE(dev);
	206	int i;
	207
	208	for (i = 0; i < cc->nr_threads; i++) {
	209	spapr_unrealize_vcpu(sc->threads[i], sc);
	210	}
	211	g_free(sc->threads);
	212	}
	213
b1d40d6e	214	static void spapr_realize_vcpu(PowerPCCPU cpu, sPAPRMachineState spapr,
cc71c776	215	sPAPRCPUCore sc, Error *errp)
3b542549	216	{
b1d40d6e	217	CPUPPCState *env = &cpu->env;
cc71c776	218	CPUState *cs = CPU(cpu);
7093645a	219	Error *local_err = NULL;
5bc8d26d	220
b1d40d6e	221	object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
5bc8d26d	222	if (local_err) {
c8a98293	223	goto error;
5bc8d26d	224	}
3b542549	225
b1d40d6e DG	226	/* Set time-base frequency to 512 MHz */
	227	cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
	228
	229	cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
	230	kvmppc_set_papr(cpu);
3b542549	231
b1d40d6e DG	232	qemu_register_reset(spapr_cpu_reset, cpu);
	233	spapr_cpu_reset(cpu);
	234
8fa1f4ef	235	spapr->irq->cpu_intc_create(spapr, cpu, &local_err);
f11235b9	236	if (local_err) {
9986ddec	237	goto error_unregister;
3b542549	238	}
5bc8d26d	239
cc71c776 BR	240	if (!sc->pre_3_0_migration) {
	241	vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
	242	cpu->machine_data);
	243	}
	244
c8a98293 GK	245	return;
c8a98293 GK	246
9986ddec GK	247	error_unregister:
	248	qemu_unregister_reset(spapr_cpu_reset, cpu);
	249	cpu_remove_sync(CPU(cpu));
6595ab31	250	error:
c8a98293	251	error_propagate(errp, local_err);
3b542549 BR	252	}
3b542549 BR	253
d9f0e34c GK	254	static PowerPCCPU spapr_create_vcpu(sPAPRCPUCore sc, int i, Error **errp)
	255	{
	256	sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
	257	CPUCore *cc = CPU_CORE(sc);
	258	Object *obj;
	259	char *id;
	260	CPUState *cs;
	261	PowerPCCPU *cpu;
	262	Error *local_err = NULL;
	263
	264	obj = object_new(scc->cpu_type);
	265
	266	cs = CPU(obj);
	267	cpu = POWERPC_CPU(obj);
	268	cs->cpu_index = cc->core_id + i;
	269	spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
	270	if (local_err) {
	271	goto err;
	272	}
	273
	274	cpu->node_id = sc->node_id;
	275
	276	id = g_strdup_printf("thread[%d]", i);
	277	object_property_add_child(OBJECT(sc), id, obj, &local_err);
	278	g_free(id);
	279	if (local_err) {
	280	goto err;
	281	}
	282
7388efaf DG	283	cpu->machine_data = g_new0(sPAPRCPUState, 1);
7388efaf DG	284
d9f0e34c GK	285	object_unref(obj);
	286	return cpu;
	287
	288	err:
	289	object_unref(obj);
	290	error_propagate(errp, local_err);
	291	return NULL;
	292	}
	293
b9402026	294	static void spapr_delete_vcpu(PowerPCCPU cpu, sPAPRCPUCore sc)
d9f0e34c	295	{
7388efaf DG	296	sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
	297
	298	cpu->machine_data = NULL;
	299	g_free(spapr_cpu);
d9f0e34c GK	300	object_unparent(OBJECT(cpu));
	301	}
	302
3b542549 BR	303	static void spapr_cpu_core_realize(DeviceState dev, Error *errp)
3b542549 BR	304	{
e7cca3e9 GK	305	/* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
	306	* tries to add a sPAPR CPU core to a non-pseries machine.
	307	*/
	308	sPAPRMachineState *spapr =
	309	(sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(),
	310	TYPE_SPAPR_MACHINE);
3b542549 BR	311	sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3b542549 BR	312	CPUCore *cc = CPU_CORE(OBJECT(dev));
3b542549	313	Error *local_err = NULL;
7093645a	314	int i, j;
3b542549	315
e7cca3e9 GK	316	if (!spapr) {
e7cca3e9 GK	317	error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
2363d5ee TH	318	return;
	319	}
	320
94ad93bd	321	sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
3b542549	322	for (i = 0; i < cc->nr_threads; i++) {
d9f0e34c	323	sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
3b542549 BR	324	if (local_err) {
	325	goto err;
	326	}
	327	}
7093645a BR	328
7093645a BR	329	for (j = 0; j < cc->nr_threads; j++) {
cc71c776	330	spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err);
7093645a	331	if (local_err) {
9986ddec	332	goto err_unrealize;
7093645a	333	}
3b542549	334	}
7093645a	335	return;
3b542549	336
9986ddec GK	337	err_unrealize:
9986ddec GK	338	while (--j >= 0) {
cc71c776	339	spapr_unrealize_vcpu(sc->threads[j], sc);
9986ddec	340	}
3b542549	341	err:
dde35bc9	342	while (--i >= 0) {
b9402026	343	spapr_delete_vcpu(sc->threads[i], sc);
3b542549 BR	344	}
	345	g_free(sc->threads);
	346	error_propagate(errp, local_err);
	347	}
	348
0b8497f0 IM	349	static Property spapr_cpu_core_properties[] = {
0b8497f0 IM	350	DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID),
b9402026 GK	351	DEFINE_PROP_BOOL("pre-3.0-migration", sPAPRCPUCore, pre_3_0_migration,
b9402026 GK	352	false),
0b8497f0 IM	353	DEFINE_PROP_END_OF_LIST()
	354	};
	355
5bbb2641	356	static void spapr_cpu_core_class_init(ObjectClass oc, void data)
3b542549	357	{
7ebaf795 BR	358	DeviceClass *dc = DEVICE_CLASS(oc);
	359	sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
	360
	361	dc->realize = spapr_cpu_core_realize;
b1d40d6e	362	dc->unrealize = spapr_cpu_core_unrealize;
0b8497f0	363	dc->props = spapr_cpu_core_properties;
b51d3c88	364	scc->cpu_type = data;
3b542549 BR	365	}
3b542549 BR	366
44cd95e3 IM	367	#define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
	368	{ \
	369	.parent = TYPE_SPAPR_CPU_CORE, \
b51d3c88	370	.class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
44cd95e3 IM	371	.class_init = spapr_cpu_core_class_init, \
44cd95e3 IM	372	.name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \
3b542549	373	}
3b542549	374
44cd95e3 IM	375	static const TypeInfo spapr_cpu_core_type_infos[] = {
	376	{
	377	.name = TYPE_SPAPR_CPU_CORE,
	378	.parent = TYPE_CPU_CORE,
	379	.abstract = true,
	380	.instance_size = sizeof(sPAPRCPUCore),
	381	.class_size = sizeof(sPAPRCPUCoreClass),
	382	},
	383	DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
	384	DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
	385	DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
	386	DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
	387	DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
	388	DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
	389	DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
	390	DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
	391	DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
	392	DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
	393	DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
5bbb2641 IM	394	#ifdef CONFIG_KVM
	395	DEFINE_SPAPR_CPU_CORE_TYPE("host"),
	396	#endif
44cd95e3 IM	397	};
	398
	399	DEFINE_TYPES(spapr_cpu_core_type_infos)