[qemu.git] / hw / ppc / ppc_booke.c

/*
 * QEMU PowerPC Booke hardware System Emulator
 *
 * Copyright (c) 2011 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/ppc/ppc.h"
#include "qemu/timer.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "qemu/log.h"
#include "hw/loader.h"
#include "kvm_ppc.h"


/* Timer Control Register */

#define TCR_WP_SHIFT  30        /* Watchdog Timer Period */
#define TCR_WP_MASK   (0x3U << TCR_WP_SHIFT)
#define TCR_WRC_SHIFT 28        /* Watchdog Timer Reset Control */
#define TCR_WRC_MASK  (0x3U << TCR_WRC_SHIFT)
#define TCR_WIE       (1U << 27) /* Watchdog Timer Interrupt Enable */
#define TCR_DIE       (1U << 26) /* Decrementer Interrupt Enable */
#define TCR_FP_SHIFT  24        /* Fixed-Interval Timer Period */
#define TCR_FP_MASK   (0x3U << TCR_FP_SHIFT)
#define TCR_FIE       (1U << 23) /* Fixed-Interval Timer Interrupt Enable */
#define TCR_ARE       (1U << 22) /* Auto-Reload Enable */

/* Timer Control Register (e500 specific fields) */

#define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
#define TCR_E500_FPEXT_MASK  (0xf << TCR_E500_FPEXT_SHIFT)
#define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
#define TCR_E500_WPEXT_MASK  (0xf << TCR_E500_WPEXT_SHIFT)

/* Timer Status Register  */

#define TSR_FIS       (1U << 26) /* Fixed-Interval Timer Interrupt Status */
#define TSR_DIS       (1U << 27) /* Decrementer Interrupt Status */
#define TSR_WRS_SHIFT 28        /* Watchdog Timer Reset Status */
#define TSR_WRS_MASK  (0x3U << TSR_WRS_SHIFT)
#define TSR_WIS       (1U << 30) /* Watchdog Timer Interrupt Status */
#define TSR_ENW       (1U << 31) /* Enable Next Watchdog Timer */

typedef struct booke_timer_t booke_timer_t;
struct booke_timer_t {

    uint64_t fit_next;
    QEMUTimer *fit_timer;

    uint64_t wdt_next;
    QEMUTimer *wdt_timer;

    uint32_t flags;
};

static void booke_update_irq(PowerPCCPU *cpu)
{
    CPUPPCState *env = &cpu->env;

    ppc_set_irq(cpu, PPC_INTERRUPT_DECR,
                (env->spr[SPR_BOOKE_TSR] & TSR_DIS
                 && env->spr[SPR_BOOKE_TCR] & TCR_DIE));

    ppc_set_irq(cpu, PPC_INTERRUPT_WDT,
                (env->spr[SPR_BOOKE_TSR] & TSR_WIS
                 && env->spr[SPR_BOOKE_TCR] & TCR_WIE));

    ppc_set_irq(cpu, PPC_INTERRUPT_FIT,
                (env->spr[SPR_BOOKE_TSR] & TSR_FIS
                 && env->spr[SPR_BOOKE_TCR] & TCR_FIE));
}

/* Return the location of the bit of time base at which the FIT will raise an
   interrupt */
static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env)
{
    uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;

    if (tb_env->flags & PPC_TIMER_E500) {
        /* e500 Fixed-interval timer period extension */
        uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK)
            >> TCR_E500_FPEXT_SHIFT;
        fp = 63 - (fp | fpext << 2);
    } else {
        fp = env->fit_period[fp];
    }

    return fp;
}

/* Return the location of the bit of time base at which the WDT will raise an
   interrupt */
static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env)
{
    uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;

    if (tb_env->flags & PPC_TIMER_E500) {
        /* e500 Watchdog timer period extension */
        uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK)
            >> TCR_E500_WPEXT_SHIFT;
        wp = 63 - (wp | wpext << 2);
    } else {
        wp = env->wdt_period[wp];
    }

    return wp;
}

static void booke_update_fixed_timer(CPUPPCState         *env,
                                     uint8_t           target_bit,
                                     uint64_t          *next,
                                     QEMUTimer         *timer,
                                     int               tsr_bit)
{
    ppc_tb_t *tb_env = env->tb_env;
    uint64_t delta_tick, ticks = 0;
    uint64_t tb;
    uint64_t period;
    uint64_t now;

    if (!(env->spr[SPR_BOOKE_TSR] & tsr_bit)) {
        /*
         * Don't arm the timer again when the guest has the current
         * interrupt still pending. Wait for it to ack it.
         */
        return;
    }

    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
    tb  = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);
    period = 1ULL << target_bit;
    delta_tick = period - (tb & (period - 1));

    /* the timer triggers only when the selected bit toggles from 0 to 1 */
    if (tb & period) {
        ticks = period;
    }

    if (ticks + delta_tick < ticks) {
        /* Overflow, so assume the biggest number we can express. */
        ticks = UINT64_MAX;
    } else {
        ticks += delta_tick;
    }

    *next = now + muldiv64(ticks, NANOSECONDS_PER_SECOND, tb_env->tb_freq);
    if ((*next < now) || (*next > INT64_MAX)) {
        /* Overflow, so assume the biggest number the qemu timer supports. */
        *next = INT64_MAX;
    }

    /* XXX: If expire time is now. We can't run the callback because we don't
     * have access to it. So we just set the timer one nanosecond later.
     */

    if (*next == now) {
        (*next)++;
    } else {
        /*
         * There's no point to fake any granularity that's more fine grained
         * than milliseconds. Anything beyond that just overloads the system.
         */
        *next = MAX(*next, now + SCALE_MS);
    }

    /* Fire the next timer */
    timer_mod(timer, *next);
}

static void booke_decr_cb(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
    booke_update_irq(cpu);

    if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
        /* Do not reload 0, it is already there. It would just trigger
         * the timer again and lead to infinite loop */
        if (env->spr[SPR_BOOKE_DECAR] != 0) {
            /* Auto Reload */
            cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
        }
    }
}

static void booke_fit_cb(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    ppc_tb_t *tb_env;
    booke_timer_t *booke_timer;

    tb_env = env->tb_env;
    booke_timer = tb_env->opaque;
    env->spr[SPR_BOOKE_TSR] |= TSR_FIS;

    booke_update_irq(cpu);

    booke_update_fixed_timer(env,
                             booke_get_fit_target(env, tb_env),
                             &booke_timer->fit_next,
                             booke_timer->fit_timer,
                             TSR_FIS);
}

static void booke_wdt_cb(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;
    ppc_tb_t *tb_env;
    booke_timer_t *booke_timer;

    tb_env = env->tb_env;
    booke_timer = tb_env->opaque;

    /* TODO: There's lots of complicated stuff to do here */

    booke_update_irq(cpu);

    booke_update_fixed_timer(env,
                             booke_get_wdt_target(env, tb_env),
                             &booke_timer->wdt_next,
                             booke_timer->wdt_timer,
                             TSR_WIS);
}

void store_booke_tsr(CPUPPCState *env, target_ulong val)
{
    PowerPCCPU *cpu = env_archcpu(env);
    ppc_tb_t *tb_env = env->tb_env;
    booke_timer_t *booke_timer = tb_env->opaque;

    env->spr[SPR_BOOKE_TSR] &= ~val;
    kvmppc_clear_tsr_bits(cpu, val);

    if (val & TSR_FIS) {
        booke_update_fixed_timer(env,
                                 booke_get_fit_target(env, tb_env),
                                 &booke_timer->fit_next,
                                 booke_timer->fit_timer,
                                 TSR_FIS);
    }

    if (val & TSR_WIS) {
        booke_update_fixed_timer(env,
                                 booke_get_wdt_target(env, tb_env),
                                 &booke_timer->wdt_next,
                                 booke_timer->wdt_timer,
                                 TSR_WIS);
    }

    booke_update_irq(cpu);
}

void store_booke_tcr(CPUPPCState *env, target_ulong val)
{
    PowerPCCPU *cpu = env_archcpu(env);
    ppc_tb_t *tb_env = env->tb_env;
    booke_timer_t *booke_timer = tb_env->opaque;

    env->spr[SPR_BOOKE_TCR] = val;
    kvmppc_set_tcr(cpu);

    booke_update_irq(cpu);

    booke_update_fixed_timer(env,
                             booke_get_fit_target(env, tb_env),
                             &booke_timer->fit_next,
                             booke_timer->fit_timer,
                             TSR_FIS);

    booke_update_fixed_timer(env,
                             booke_get_wdt_target(env, tb_env),
                             &booke_timer->wdt_next,
                             booke_timer->wdt_timer,
                             TSR_WIS);
}

static void ppc_booke_timer_reset_handle(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    store_booke_tcr(env, 0);
    store_booke_tsr(env, -1);
}

/*
 * This function will be called whenever the CPU state changes.
 * CPU states are defined "typedef enum RunState".
 * Regarding timer, When CPU state changes to running after debug halt
 * or similar cases which takes time then in between final watchdog
 * expiry happenes. This will cause exit to QEMU and configured watchdog
 * action will be taken. To avoid this we always clear the watchdog state when
 * state changes to running.
 */
static void cpu_state_change_handler(void *opaque, bool running, RunState state)
{
    PowerPCCPU *cpu = opaque;
    CPUPPCState *env = &cpu->env;

    if (!running) {
        return;
    }

    /*
     * Clear watchdog interrupt condition by clearing TSR.
     */
    store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK);
}

void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
{
    ppc_tb_t *tb_env;
    booke_timer_t *booke_timer;
    int ret = 0;

    tb_env      = g_malloc0(sizeof(ppc_tb_t));
    booke_timer = g_malloc0(sizeof(booke_timer_t));

    cpu->env.tb_env = tb_env;
    tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;

    tb_env->tb_freq    = freq;
    tb_env->decr_freq  = freq;
    tb_env->opaque     = booke_timer;
    tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu);

    booke_timer->fit_timer =
        timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu);
    booke_timer->wdt_timer =
        timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu);

    ret = kvmppc_booke_watchdog_enable(cpu);

    if (ret) {
        /* TODO: Start the QEMU emulated watchdog if not running on KVM.
         * Also start the QEMU emulated watchdog if KVM does not support
         * emulated watchdog or somehow it is not enabled (supported but
         * not enabled is though some bug and requires debugging :)).
         */
    }

    qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu);

    qemu_register_reset(ppc_booke_timer_reset_handle, cpu);
}
Commit	Line	Data
ddd1055b FC	1	/*
	2	* QEMU PowerPC Booke hardware System Emulator
	3	*
	4	* Copyright (c) 2011 AdaCore
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
71e8a915	24
0d75590d	25	#include "qemu/osdep.h"
4771d756	26	#include "cpu.h"
0d09e41a	27	#include "hw/ppc/ppc.h"
1de7afc9	28	#include "qemu/timer.h"
71e8a915	29	#include "sysemu/reset.h"
54d31236	30	#include "sysemu/runstate.h"
1de7afc9	31	#include "qemu/log.h"
83c9f4ca	32	#include "hw/loader.h"
31f2cb8f	33	#include "kvm_ppc.h"
ddd1055b FC	34
	35
	36	/* Timer Control Register */
	37
	38	#define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
a1f7f97b	39	#define TCR_WP_MASK (0x3U << TCR_WP_SHIFT)
ddd1055b	40	#define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
a1f7f97b PM	41	#define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT)
	42	#define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */
	43	#define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */
ddd1055b	44	#define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
a1f7f97b PM	45	#define TCR_FP_MASK (0x3U << TCR_FP_SHIFT)
	46	#define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */
	47	#define TCR_ARE (1U << 22) /* Auto-Reload Enable */
ddd1055b FC	48
	49	/* Timer Control Register (e500 specific fields) */
	50
	51	#define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
	52	#define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT)
	53	#define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
	54	#define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT)
	55
	56	/* Timer Status Register */
	57
a1f7f97b PM	58	#define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */
a1f7f97b PM	59	#define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */
ddd1055b	60	#define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
a1f7f97b PM	61	#define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT)
	62	#define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */
	63	#define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */
ddd1055b FC	64
	65	typedef struct booke_timer_t booke_timer_t;
	66	struct booke_timer_t {
	67
	68	uint64_t fit_next;
1246b259	69	QEMUTimer *fit_timer;
ddd1055b FC	70
ddd1055b FC	71	uint64_t wdt_next;
1246b259	72	QEMUTimer *wdt_timer;
ddd1055b FC	73
	74	uint32_t flags;
	75	};
	76
7058581a	77	static void booke_update_irq(PowerPCCPU *cpu)
ddd1055b	78	{
7058581a AF	79	CPUPPCState *env = &cpu->env;
	80
	81	ppc_set_irq(cpu, PPC_INTERRUPT_DECR,
ddd1055b FC	82	(env->spr[SPR_BOOKE_TSR] & TSR_DIS
	83	&& env->spr[SPR_BOOKE_TCR] & TCR_DIE));
	84
7058581a	85	ppc_set_irq(cpu, PPC_INTERRUPT_WDT,
ddd1055b FC	86	(env->spr[SPR_BOOKE_TSR] & TSR_WIS
	87	&& env->spr[SPR_BOOKE_TCR] & TCR_WIE));
	88
7058581a	89	ppc_set_irq(cpu, PPC_INTERRUPT_FIT,
ddd1055b FC	90	(env->spr[SPR_BOOKE_TSR] & TSR_FIS
	91	&& env->spr[SPR_BOOKE_TCR] & TCR_FIE));
	92	}
	93
	94	/* Return the location of the bit of time base at which the FIT will raise an
	95	interrupt */
e2684c0b	96	static uint8_t booke_get_fit_target(CPUPPCState env, ppc_tb_t tb_env)
ddd1055b FC	97	{
	98	uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;
	99
	100	if (tb_env->flags & PPC_TIMER_E500) {
	101	/* e500 Fixed-interval timer period extension */
	102	uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK)
	103	>> TCR_E500_FPEXT_SHIFT;
	104	fp = 63 - (fp \| fpext << 2);
	105	} else {
	106	fp = env->fit_period[fp];
	107	}
	108
	109	return fp;
	110	}
	111
	112	/* Return the location of the bit of time base at which the WDT will raise an
	113	interrupt */
e2684c0b	114	static uint8_t booke_get_wdt_target(CPUPPCState env, ppc_tb_t tb_env)
ddd1055b FC	115	{
	116	uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;
	117
	118	if (tb_env->flags & PPC_TIMER_E500) {
	119	/* e500 Watchdog timer period extension */
	120	uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK)
	121	>> TCR_E500_WPEXT_SHIFT;
	122	wp = 63 - (wp \| wpext << 2);
	123	} else {
	124	wp = env->wdt_period[wp];
	125	}
	126
	127	return wp;
	128	}
	129
e2684c0b	130	static void booke_update_fixed_timer(CPUPPCState *env,
ddd1055b FC	131	uint8_t target_bit,
ddd1055b FC	132	uint64_t *next,
455df3f3 AG	133	QEMUTimer *timer,
455df3f3 AG	134	int tsr_bit)
ddd1055b FC	135	{
ddd1055b FC	136	ppc_tb_t *tb_env = env->tb_env;
ab8131af	137	uint64_t delta_tick, ticks = 0;
ddd1055b	138	uint64_t tb;
ab8131af	139	uint64_t period;
ddd1055b FC	140	uint64_t now;
ddd1055b FC	141
455df3f3 AG	142	if (!(env->spr[SPR_BOOKE_TSR] & tsr_bit)) {
	143	/*
	144	* Don't arm the timer again when the guest has the current
	145	* interrupt still pending. Wait for it to ack it.
	146	*/
	147	return;
	148	}
	149
bc72ad67	150	now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
ddd1055b	151	tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);
ab8131af BB	152	period = 1ULL << target_bit;
ab8131af BB	153	delta_tick = period - (tb & (period - 1));
ddd1055b	154
ab8131af BB	155	/* the timer triggers only when the selected bit toggles from 0 to 1 */
	156	if (tb & period) {
	157	ticks = period;
	158	}
ddd1055b	159
ab8131af BB	160	if (ticks + delta_tick < ticks) {
	161	/* Overflow, so assume the biggest number we can express. */
	162	ticks = UINT64_MAX;
	163	} else {
	164	ticks += delta_tick;
	165	}
	166
73bcb24d	167	*next = now + muldiv64(ticks, NANOSECONDS_PER_SECOND, tb_env->tb_freq);
ab8131af BB	168	if ((next < now) \|\| (next > INT64_MAX)) {
	169	/* Overflow, so assume the biggest number the qemu timer supports. */
	170	*next = INT64_MAX;
	171	}
ddd1055b FC	172
	173	/* XXX: If expire time is now. We can't run the callback because we don't
	174	* have access to it. So we just set the timer one nanosecond later.
	175	*/
	176
	177	if (*next == now) {
	178	(*next)++;
84dc96e1 AG	179	} else {
	180	/*
	181	* There's no point to fake any granularity that's more fine grained
	182	* than milliseconds. Anything beyond that just overloads the system.
	183	*/
	184	next = MAX(next, now + SCALE_MS);
ddd1055b FC	185	}
ddd1055b FC	186
455df3f3	187	/* Fire the next timer */
bc72ad67	188	timer_mod(timer, *next);
ddd1055b FC	189	}
	190
	191	static void booke_decr_cb(void *opaque)
	192	{
ee0c98e6 AF	193	PowerPCCPU *cpu = opaque;
ee0c98e6 AF	194	CPUPPCState *env = &cpu->env;
ddd1055b	195
ddd1055b	196	env->spr[SPR_BOOKE_TSR] \|= TSR_DIS;
7058581a	197	booke_update_irq(cpu);
ddd1055b FC	198
ddd1055b FC	199	if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
0dfe952d RK	200	/* Do not reload 0, it is already there. It would just trigger
	201	* the timer again and lead to infinite loop */
	202	if (env->spr[SPR_BOOKE_DECAR] != 0) {
	203	/* Auto Reload */
	204	cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
	205	}
ddd1055b FC	206	}
	207	}
	208
	209	static void booke_fit_cb(void *opaque)
	210	{
ee0c98e6 AF	211	PowerPCCPU *cpu = opaque;
ee0c98e6 AF	212	CPUPPCState *env = &cpu->env;
ddd1055b FC	213	ppc_tb_t *tb_env;
	214	booke_timer_t *booke_timer;
	215
ddd1055b FC	216	tb_env = env->tb_env;
	217	booke_timer = tb_env->opaque;
	218	env->spr[SPR_BOOKE_TSR] \|= TSR_FIS;
	219
7058581a	220	booke_update_irq(cpu);
ddd1055b FC	221
	222	booke_update_fixed_timer(env,
	223	booke_get_fit_target(env, tb_env),
	224	&booke_timer->fit_next,
455df3f3 AG	225	booke_timer->fit_timer,
455df3f3 AG	226	TSR_FIS);
ddd1055b FC	227	}
	228
	229	static void booke_wdt_cb(void *opaque)
	230	{
ee0c98e6 AF	231	PowerPCCPU *cpu = opaque;
ee0c98e6 AF	232	CPUPPCState *env = &cpu->env;
ddd1055b FC	233	ppc_tb_t *tb_env;
	234	booke_timer_t *booke_timer;
	235
ddd1055b FC	236	tb_env = env->tb_env;
	237	booke_timer = tb_env->opaque;
	238
	239	/* TODO: There's lots of complicated stuff to do here */
	240
7058581a	241	booke_update_irq(cpu);
ddd1055b FC	242
	243	booke_update_fixed_timer(env,
	244	booke_get_wdt_target(env, tb_env),
	245	&booke_timer->wdt_next,
455df3f3 AG	246	booke_timer->wdt_timer,
455df3f3 AG	247	TSR_WIS);
ddd1055b FC	248	}
ddd1055b FC	249
e2684c0b	250	void store_booke_tsr(CPUPPCState *env, target_ulong val)
ddd1055b	251	{
db70b311	252	PowerPCCPU *cpu = env_archcpu(env);
455df3f3 AG	253	ppc_tb_t *tb_env = env->tb_env;
455df3f3 AG	254	booke_timer_t *booke_timer = tb_env->opaque;
7058581a	255
ddd1055b	256	env->spr[SPR_BOOKE_TSR] &= ~val;
31f2cb8f	257	kvmppc_clear_tsr_bits(cpu, val);
455df3f3 AG	258
	259	if (val & TSR_FIS) {
	260	booke_update_fixed_timer(env,
	261	booke_get_fit_target(env, tb_env),
	262	&booke_timer->fit_next,
	263	booke_timer->fit_timer,
	264	TSR_FIS);
	265	}
	266
	267	if (val & TSR_WIS) {
	268	booke_update_fixed_timer(env,
	269	booke_get_wdt_target(env, tb_env),
	270	&booke_timer->wdt_next,
	271	booke_timer->wdt_timer,
	272	TSR_WIS);
	273	}
	274
7058581a	275	booke_update_irq(cpu);
ddd1055b FC	276	}
ddd1055b FC	277
e2684c0b	278	void store_booke_tcr(CPUPPCState *env, target_ulong val)
ddd1055b	279	{
db70b311	280	PowerPCCPU *cpu = env_archcpu(env);
ddd1055b FC	281	ppc_tb_t *tb_env = env->tb_env;
	282	booke_timer_t *booke_timer = tb_env->opaque;
	283
ddd1055b	284	env->spr[SPR_BOOKE_TCR] = val;
31f2cb8f	285	kvmppc_set_tcr(cpu);
ddd1055b	286
7058581a	287	booke_update_irq(cpu);
ddd1055b FC	288
	289	booke_update_fixed_timer(env,
	290	booke_get_fit_target(env, tb_env),
	291	&booke_timer->fit_next,
455df3f3 AG	292	booke_timer->fit_timer,
455df3f3 AG	293	TSR_FIS);
ddd1055b FC	294
	295	booke_update_fixed_timer(env,
	296	booke_get_wdt_target(env, tb_env),
	297	&booke_timer->wdt_next,
455df3f3 AG	298	booke_timer->wdt_timer,
455df3f3 AG	299	TSR_WIS);
ddd1055b FC	300	}
ddd1055b FC	301
88a78d90 BB	302	static void ppc_booke_timer_reset_handle(void *opaque)
	303	{
	304	PowerPCCPU *cpu = opaque;
	305	CPUPPCState *env = &cpu->env;
	306
31f2cb8f BB	307	store_booke_tcr(env, 0);
	308	store_booke_tsr(env, -1);
	309	}
88a78d90	310
31f2cb8f BB	311	/*
	312	* This function will be called whenever the CPU state changes.
	313	* CPU states are defined "typedef enum RunState".
	314	* Regarding timer, When CPU state changes to running after debug halt
	315	* or similar cases which takes time then in between final watchdog
	316	* expiry happenes. This will cause exit to QEMU and configured watchdog
	317	* action will be taken. To avoid this we always clear the watchdog state when
	318	* state changes to running.
	319	*/
538f0497	320	static void cpu_state_change_handler(void *opaque, bool running, RunState state)
31f2cb8f BB	321	{
	322	PowerPCCPU *cpu = opaque;
	323	CPUPPCState *env = &cpu->env;
	324
	325	if (!running) {
	326	return;
	327	}
	328
	329	/*
	330	* Clear watchdog interrupt condition by clearing TSR.
	331	*/
	332	store_booke_tsr(env, TSR_ENW \| TSR_WIS \| TSR_WRS_MASK);
88a78d90 BB	333	}
88a78d90 BB	334
a34a92b9	335	void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
ddd1055b FC	336	{
	337	ppc_tb_t *tb_env;
	338	booke_timer_t *booke_timer;
31f2cb8f	339	int ret = 0;
ddd1055b FC	340
	341	tb_env = g_malloc0(sizeof(ppc_tb_t));
	342	booke_timer = g_malloc0(sizeof(booke_timer_t));
	343
a34a92b9	344	cpu->env.tb_env = tb_env;
ddd1055b FC	345	tb_env->flags = flags \| PPC_TIMER_BOOKE \| PPC_DECR_ZERO_TRIGGERED;
	346
	347	tb_env->tb_freq = freq;
	348	tb_env->decr_freq = freq;
	349	tb_env->opaque = booke_timer;
bc72ad67	350	tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu);
ddd1055b FC	351
ddd1055b FC	352	booke_timer->fit_timer =
bc72ad67	353	timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu);
ddd1055b	354	booke_timer->wdt_timer =
bc72ad67	355	timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu);
88a78d90	356
31f2cb8f BB	357	ret = kvmppc_booke_watchdog_enable(cpu);
	358
	359	if (ret) {
	360	/* TODO: Start the QEMU emulated watchdog if not running on KVM.
	361	* Also start the QEMU emulated watchdog if KVM does not support
	362	* emulated watchdog or somehow it is not enabled (supported but
	363	* not enabled is though some bug and requires debugging :)).
	364	*/
	365	}
	366
	367	qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu);
	368
88a78d90	369	qemu_register_reset(ppc_booke_timer_reset_handle, cpu);
ddd1055b	370	}