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Commit | Line | Data |
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1fc3d392 AJ |
1 | /* |
2 | * QEMU G364 framebuffer Emulator. | |
3 | * | |
97a3f6ff | 4 | * Copyright (c) 2007-2011 Herve Poussineau |
1fc3d392 AJ |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
fad6cb1a | 16 | * You should have received a copy of the GNU General Public License along |
8167ee88 | 17 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
1fc3d392 AJ |
18 | */ |
19 | ||
83c9f4ca | 20 | #include "hw/hw.h" |
28ecbaee PB |
21 | #include "ui/console.h" |
22 | #include "ui/pixel_ops.h" | |
b213b370 | 23 | #include "trace.h" |
83c9f4ca | 24 | #include "hw/sysbus.h" |
0add30cf | 25 | |
1fc3d392 | 26 | typedef struct G364State { |
0add30cf AJ |
27 | /* hardware */ |
28 | uint8_t *vram; | |
97a3f6ff | 29 | uint32_t vram_size; |
0add30cf | 30 | qemu_irq irq; |
97a3f6ff HP |
31 | MemoryRegion mem_vram; |
32 | MemoryRegion mem_ctrl; | |
0add30cf AJ |
33 | /* registers */ |
34 | uint8_t color_palette[256][3]; | |
35 | uint8_t cursor_palette[3][3]; | |
36 | uint16_t cursor[512]; | |
37 | uint32_t cursor_position; | |
1fc3d392 | 38 | uint32_t ctla; |
0add30cf AJ |
39 | uint32_t top_of_screen; |
40 | uint32_t width, height; /* in pixels */ | |
1fc3d392 | 41 | /* display refresh support */ |
c78f7137 | 42 | QemuConsole *con; |
0add30cf AJ |
43 | int depth; |
44 | int blanked; | |
1fc3d392 AJ |
45 | } G364State; |
46 | ||
97a3f6ff HP |
47 | #define REG_BOOT 0x000000 |
48 | #define REG_DISPLAY 0x000118 | |
49 | #define REG_VDISPLAY 0x000150 | |
50 | #define REG_CTLA 0x000300 | |
51 | #define REG_TOP 0x000400 | |
52 | #define REG_CURS_PAL 0x000508 | |
53 | #define REG_CURS_POS 0x000638 | |
54 | #define REG_CLR_PAL 0x000800 | |
55 | #define REG_CURS_PAT 0x001000 | |
56 | #define REG_RESET 0x100000 | |
0add30cf AJ |
57 | |
58 | #define CTLA_FORCE_BLANK 0x00000400 | |
59 | #define CTLA_NO_CURSOR 0x00800000 | |
60 | ||
1213406b BS |
61 | #define G364_PAGE_SIZE 4096 |
62 | ||
97a3f6ff | 63 | static inline int check_dirty(G364State *s, ram_addr_t page) |
0add30cf | 64 | { |
cd7a45c9 BS |
65 | return memory_region_get_dirty(&s->mem_vram, page, G364_PAGE_SIZE, |
66 | DIRTY_MEMORY_VGA); | |
0add30cf AJ |
67 | } |
68 | ||
69 | static inline void reset_dirty(G364State *s, | |
c227f099 | 70 | ram_addr_t page_min, ram_addr_t page_max) |
0add30cf | 71 | { |
97a3f6ff HP |
72 | memory_region_reset_dirty(&s->mem_vram, |
73 | page_min, | |
1213406b | 74 | page_max + G364_PAGE_SIZE - page_min - 1, |
97a3f6ff | 75 | DIRTY_MEMORY_VGA); |
0add30cf AJ |
76 | } |
77 | ||
78 | static void g364fb_draw_graphic8(G364State *s) | |
1fc3d392 | 79 | { |
c78f7137 | 80 | DisplaySurface *surface = qemu_console_surface(s->con); |
0add30cf AJ |
81 | int i, w; |
82 | uint8_t *vram; | |
83 | uint8_t *data_display, *dd; | |
c227f099 | 84 | ram_addr_t page, page_min, page_max; |
0add30cf AJ |
85 | int x, y; |
86 | int xmin, xmax; | |
87 | int ymin, ymax; | |
88 | int xcursor, ycursor; | |
89 | unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b); | |
90 | ||
c78f7137 | 91 | switch (surface_bits_per_pixel(surface)) { |
1fc3d392 | 92 | case 8: |
0add30cf AJ |
93 | rgb_to_pixel = rgb_to_pixel8; |
94 | w = 1; | |
1fc3d392 AJ |
95 | break; |
96 | case 15: | |
0add30cf AJ |
97 | rgb_to_pixel = rgb_to_pixel15; |
98 | w = 2; | |
1fc3d392 AJ |
99 | break; |
100 | case 16: | |
0add30cf AJ |
101 | rgb_to_pixel = rgb_to_pixel16; |
102 | w = 2; | |
1fc3d392 AJ |
103 | break; |
104 | case 32: | |
0add30cf AJ |
105 | rgb_to_pixel = rgb_to_pixel32; |
106 | w = 4; | |
1fc3d392 AJ |
107 | break; |
108 | default: | |
b213b370 | 109 | hw_error("g364: unknown host depth %d", |
c78f7137 | 110 | surface_bits_per_pixel(surface)); |
1fc3d392 AJ |
111 | return; |
112 | } | |
113 | ||
97a3f6ff | 114 | page = 0; |
c227f099 | 115 | page_min = (ram_addr_t)-1; |
0add30cf AJ |
116 | page_max = 0; |
117 | ||
118 | x = y = 0; | |
119 | xmin = s->width; | |
120 | xmax = 0; | |
121 | ymin = s->height; | |
122 | ymax = 0; | |
123 | ||
124 | if (!(s->ctla & CTLA_NO_CURSOR)) { | |
125 | xcursor = s->cursor_position >> 12; | |
126 | ycursor = s->cursor_position & 0xfff; | |
127 | } else { | |
128 | xcursor = ycursor = -65; | |
129 | } | |
130 | ||
131 | vram = s->vram + s->top_of_screen; | |
132 | /* XXX: out of range in vram? */ | |
c78f7137 | 133 | data_display = dd = surface_data(surface); |
0add30cf | 134 | while (y < s->height) { |
97a3f6ff | 135 | if (check_dirty(s, page)) { |
0add30cf AJ |
136 | if (y < ymin) |
137 | ymin = ymax = y; | |
c227f099 | 138 | if (page_min == (ram_addr_t)-1) |
0add30cf AJ |
139 | page_min = page; |
140 | page_max = page; | |
141 | if (x < xmin) | |
142 | xmin = x; | |
1213406b | 143 | for (i = 0; i < G364_PAGE_SIZE; i++) { |
0add30cf AJ |
144 | uint8_t index; |
145 | unsigned int color; | |
146 | if (unlikely((y >= ycursor && y < ycursor + 64) && | |
147 | (x >= xcursor && x < xcursor + 64))) { | |
148 | /* pointer area */ | |
149 | int xdiff = x - xcursor; | |
150 | uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8]; | |
151 | int op = (curs >> ((xdiff & 7) * 2)) & 3; | |
152 | if (likely(op == 0)) { | |
153 | /* transparent */ | |
154 | index = *vram; | |
155 | color = (*rgb_to_pixel)( | |
156 | s->color_palette[index][0], | |
157 | s->color_palette[index][1], | |
158 | s->color_palette[index][2]); | |
159 | } else { | |
160 | /* get cursor color */ | |
161 | index = op - 1; | |
162 | color = (*rgb_to_pixel)( | |
163 | s->cursor_palette[index][0], | |
164 | s->cursor_palette[index][1], | |
165 | s->cursor_palette[index][2]); | |
166 | } | |
167 | } else { | |
168 | /* normal area */ | |
169 | index = *vram; | |
170 | color = (*rgb_to_pixel)( | |
171 | s->color_palette[index][0], | |
172 | s->color_palette[index][1], | |
173 | s->color_palette[index][2]); | |
174 | } | |
175 | memcpy(dd, &color, w); | |
176 | dd += w; | |
177 | x++; | |
178 | vram++; | |
179 | if (x == s->width) { | |
180 | xmax = s->width - 1; | |
181 | y++; | |
182 | if (y == s->height) { | |
183 | ymax = s->height - 1; | |
184 | goto done; | |
185 | } | |
c78f7137 | 186 | data_display = dd = data_display + surface_stride(surface); |
0add30cf AJ |
187 | xmin = 0; |
188 | x = 0; | |
189 | } | |
190 | } | |
191 | if (x > xmax) | |
192 | xmax = x; | |
193 | if (y > ymax) | |
194 | ymax = y; | |
195 | } else { | |
196 | int dy; | |
c227f099 | 197 | if (page_min != (ram_addr_t)-1) { |
0add30cf | 198 | reset_dirty(s, page_min, page_max); |
c227f099 | 199 | page_min = (ram_addr_t)-1; |
0add30cf | 200 | page_max = 0; |
c78f7137 | 201 | dpy_gfx_update(s->con, xmin, ymin, |
a93a4a22 | 202 | xmax - xmin + 1, ymax - ymin + 1); |
0add30cf AJ |
203 | xmin = s->width; |
204 | xmax = 0; | |
205 | ymin = s->height; | |
206 | ymax = 0; | |
207 | } | |
1213406b | 208 | x += G364_PAGE_SIZE; |
0add30cf AJ |
209 | dy = x / s->width; |
210 | x = x % s->width; | |
211 | y += dy; | |
1213406b | 212 | vram += G364_PAGE_SIZE; |
c78f7137 | 213 | data_display += dy * surface_stride(surface); |
0add30cf AJ |
214 | dd = data_display + x * w; |
215 | } | |
1213406b | 216 | page += G364_PAGE_SIZE; |
0add30cf AJ |
217 | } |
218 | ||
219 | done: | |
c227f099 | 220 | if (page_min != (ram_addr_t)-1) { |
c78f7137 | 221 | dpy_gfx_update(s->con, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); |
0add30cf AJ |
222 | reset_dirty(s, page_min, page_max); |
223 | } | |
1fc3d392 AJ |
224 | } |
225 | ||
0add30cf | 226 | static void g364fb_draw_blank(G364State *s) |
1fc3d392 | 227 | { |
c78f7137 | 228 | DisplaySurface *surface = qemu_console_surface(s->con); |
1fc3d392 AJ |
229 | int i, w; |
230 | uint8_t *d; | |
231 | ||
0add30cf AJ |
232 | if (s->blanked) { |
233 | /* Screen is already blank. No need to redraw it */ | |
1fc3d392 | 234 | return; |
0add30cf | 235 | } |
1fc3d392 | 236 | |
c78f7137 GH |
237 | w = s->width * surface_bytes_per_pixel(surface); |
238 | d = surface_data(surface); | |
0add30cf | 239 | for (i = 0; i < s->height; i++) { |
1fc3d392 | 240 | memset(d, 0, w); |
c78f7137 | 241 | d += surface_stride(surface); |
1fc3d392 | 242 | } |
221bb2d5 | 243 | |
c78f7137 | 244 | dpy_gfx_update(s->con, 0, 0, s->width, s->height); |
0add30cf | 245 | s->blanked = 1; |
1fc3d392 AJ |
246 | } |
247 | ||
1fc3d392 AJ |
248 | static void g364fb_update_display(void *opaque) |
249 | { | |
250 | G364State *s = opaque; | |
c78f7137 | 251 | DisplaySurface *surface = qemu_console_surface(s->con); |
1fc3d392 | 252 | |
e9a07334 JK |
253 | qemu_flush_coalesced_mmio_buffer(); |
254 | ||
0add30cf | 255 | if (s->width == 0 || s->height == 0) |
221bb2d5 AJ |
256 | return; |
257 | ||
c78f7137 GH |
258 | if (s->width != surface_width(surface) || |
259 | s->height != surface_height(surface)) { | |
260 | qemu_console_resize(s->con, s->width, s->height); | |
221bb2d5 | 261 | } |
0add30cf AJ |
262 | |
263 | if (s->ctla & CTLA_FORCE_BLANK) { | |
264 | g364fb_draw_blank(s); | |
265 | } else if (s->depth == 8) { | |
266 | g364fb_draw_graphic8(s); | |
267 | } else { | |
b213b370 | 268 | error_report("g364: unknown guest depth %d", s->depth); |
1fc3d392 | 269 | } |
0add30cf AJ |
270 | |
271 | qemu_irq_raise(s->irq); | |
1fc3d392 AJ |
272 | } |
273 | ||
86178a57 | 274 | static inline void g364fb_invalidate_display(void *opaque) |
1fc3d392 AJ |
275 | { |
276 | G364State *s = opaque; | |
0add30cf AJ |
277 | |
278 | s->blanked = 0; | |
fd4aa979 | 279 | memory_region_set_dirty(&s->mem_vram, 0, s->vram_size); |
1fc3d392 AJ |
280 | } |
281 | ||
97a3f6ff | 282 | static void g364fb_reset(G364State *s) |
1fc3d392 | 283 | { |
0add30cf AJ |
284 | qemu_irq_lower(s->irq); |
285 | ||
286 | memset(s->color_palette, 0, sizeof(s->color_palette)); | |
287 | memset(s->cursor_palette, 0, sizeof(s->cursor_palette)); | |
288 | memset(s->cursor, 0, sizeof(s->cursor)); | |
289 | s->cursor_position = 0; | |
290 | s->ctla = 0; | |
291 | s->top_of_screen = 0; | |
292 | s->width = s->height = 0; | |
293 | memset(s->vram, 0, s->vram_size); | |
97a3f6ff | 294 | g364fb_invalidate_display(s); |
1fc3d392 AJ |
295 | } |
296 | ||
1fc3d392 | 297 | /* called for accesses to io ports */ |
97a3f6ff | 298 | static uint64_t g364fb_ctrl_read(void *opaque, |
a8170e5e | 299 | hwaddr addr, |
97a3f6ff | 300 | unsigned int size) |
1fc3d392 | 301 | { |
0add30cf | 302 | G364State *s = opaque; |
1fc3d392 AJ |
303 | uint32_t val; |
304 | ||
0add30cf AJ |
305 | if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { |
306 | /* cursor pattern */ | |
307 | int idx = (addr - REG_CURS_PAT) >> 3; | |
308 | val = s->cursor[idx]; | |
309 | } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { | |
310 | /* cursor palette */ | |
311 | int idx = (addr - REG_CURS_PAL) >> 3; | |
312 | val = ((uint32_t)s->cursor_palette[idx][0] << 16); | |
313 | val |= ((uint32_t)s->cursor_palette[idx][1] << 8); | |
314 | val |= ((uint32_t)s->cursor_palette[idx][2] << 0); | |
315 | } else { | |
316 | switch (addr) { | |
0add30cf AJ |
317 | case REG_DISPLAY: |
318 | val = s->width / 4; | |
319 | break; | |
320 | case REG_VDISPLAY: | |
321 | val = s->height * 2; | |
322 | break; | |
323 | case REG_CTLA: | |
324 | val = s->ctla; | |
325 | break; | |
326 | default: | |
327 | { | |
b213b370 HP |
328 | error_report("g364: invalid read at [" TARGET_FMT_plx "]", |
329 | addr); | |
0add30cf AJ |
330 | val = 0; |
331 | break; | |
332 | } | |
333 | } | |
1fc3d392 AJ |
334 | } |
335 | ||
b213b370 | 336 | trace_g364fb_read(addr, val); |
1fc3d392 AJ |
337 | |
338 | return val; | |
339 | } | |
340 | ||
0add30cf | 341 | static void g364fb_update_depth(G364State *s) |
1fc3d392 | 342 | { |
38972938 | 343 | static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 }; |
0add30cf AJ |
344 | s->depth = depths[(s->ctla & 0x00700000) >> 20]; |
345 | } | |
1fc3d392 | 346 | |
0add30cf AJ |
347 | static void g364_invalidate_cursor_position(G364State *s) |
348 | { | |
c78f7137 | 349 | DisplaySurface *surface = qemu_console_surface(s->con); |
fd4aa979 | 350 | int ymin, ymax, start, end; |
1fc3d392 | 351 | |
0add30cf AJ |
352 | /* invalidate only near the cursor */ |
353 | ymin = s->cursor_position & 0xfff; | |
354 | ymax = MIN(s->height, ymin + 64); | |
c78f7137 GH |
355 | start = ymin * surface_stride(surface); |
356 | end = (ymax + 1) * surface_stride(surface); | |
1fc3d392 | 357 | |
fd4aa979 | 358 | memory_region_set_dirty(&s->mem_vram, start, end - start); |
0add30cf AJ |
359 | } |
360 | ||
97a3f6ff | 361 | static void g364fb_ctrl_write(void *opaque, |
a8170e5e | 362 | hwaddr addr, |
97a3f6ff HP |
363 | uint64_t val, |
364 | unsigned int size) | |
0add30cf AJ |
365 | { |
366 | G364State *s = opaque; | |
367 | ||
b213b370 | 368 | trace_g364fb_write(addr, val); |
0add30cf AJ |
369 | |
370 | if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) { | |
1fc3d392 | 371 | /* color palette */ |
0add30cf AJ |
372 | int idx = (addr - REG_CLR_PAL) >> 3; |
373 | s->color_palette[idx][0] = (val >> 16) & 0xff; | |
374 | s->color_palette[idx][1] = (val >> 8) & 0xff; | |
375 | s->color_palette[idx][2] = val & 0xff; | |
376 | g364fb_invalidate_display(s); | |
377 | } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) { | |
378 | /* cursor pattern */ | |
379 | int idx = (addr - REG_CURS_PAT) >> 3; | |
380 | s->cursor[idx] = val; | |
381 | g364fb_invalidate_display(s); | |
382 | } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) { | |
383 | /* cursor palette */ | |
384 | int idx = (addr - REG_CURS_PAL) >> 3; | |
385 | s->cursor_palette[idx][0] = (val >> 16) & 0xff; | |
386 | s->cursor_palette[idx][1] = (val >> 8) & 0xff; | |
387 | s->cursor_palette[idx][2] = val & 0xff; | |
388 | g364fb_invalidate_display(s); | |
1fc3d392 AJ |
389 | } else { |
390 | switch (addr) { | |
97a3f6ff HP |
391 | case REG_BOOT: /* Boot timing */ |
392 | case 0x00108: /* Line timing: half sync */ | |
393 | case 0x00110: /* Line timing: back porch */ | |
394 | case 0x00120: /* Line timing: short display */ | |
395 | case 0x00128: /* Frame timing: broad pulse */ | |
396 | case 0x00130: /* Frame timing: v sync */ | |
397 | case 0x00138: /* Frame timing: v preequalise */ | |
398 | case 0x00140: /* Frame timing: v postequalise */ | |
399 | case 0x00148: /* Frame timing: v blank */ | |
400 | case 0x00158: /* Line timing: line time */ | |
401 | case 0x00160: /* Frame store: line start */ | |
402 | case 0x00168: /* vram cycle: mem init */ | |
403 | case 0x00170: /* vram cycle: transfer delay */ | |
404 | case 0x00200: /* vram cycle: mask register */ | |
405 | /* ignore */ | |
406 | break; | |
407 | case REG_TOP: | |
408 | s->top_of_screen = val; | |
409 | g364fb_invalidate_display(s); | |
410 | break; | |
411 | case REG_DISPLAY: | |
412 | s->width = val * 4; | |
413 | break; | |
414 | case REG_VDISPLAY: | |
415 | s->height = val / 2; | |
416 | break; | |
417 | case REG_CTLA: | |
418 | s->ctla = val; | |
419 | g364fb_update_depth(s); | |
420 | g364fb_invalidate_display(s); | |
421 | break; | |
422 | case REG_CURS_POS: | |
423 | g364_invalidate_cursor_position(s); | |
424 | s->cursor_position = val; | |
425 | g364_invalidate_cursor_position(s); | |
426 | break; | |
427 | case REG_RESET: | |
428 | g364fb_reset(s); | |
429 | break; | |
430 | default: | |
431 | error_report("g364: invalid write of 0x%" PRIx64 | |
432 | " at [" TARGET_FMT_plx "]", val, addr); | |
433 | break; | |
1fc3d392 AJ |
434 | } |
435 | } | |
0add30cf | 436 | qemu_irq_lower(s->irq); |
1fc3d392 AJ |
437 | } |
438 | ||
97a3f6ff HP |
439 | static const MemoryRegionOps g364fb_ctrl_ops = { |
440 | .read = g364fb_ctrl_read, | |
441 | .write = g364fb_ctrl_write, | |
442 | .endianness = DEVICE_LITTLE_ENDIAN, | |
443 | .impl.min_access_size = 4, | |
444 | .impl.max_access_size = 4, | |
1fc3d392 AJ |
445 | }; |
446 | ||
97a3f6ff | 447 | static int g364fb_post_load(void *opaque, int version_id) |
1fc3d392 AJ |
448 | { |
449 | G364State *s = opaque; | |
0add30cf AJ |
450 | |
451 | /* force refresh */ | |
452 | g364fb_update_depth(s); | |
453 | g364fb_invalidate_display(s); | |
1fc3d392 | 454 | |
0add30cf | 455 | return 0; |
1fc3d392 AJ |
456 | } |
457 | ||
97a3f6ff HP |
458 | static const VMStateDescription vmstate_g364fb = { |
459 | .name = "g364fb", | |
460 | .version_id = 1, | |
461 | .minimum_version_id = 1, | |
462 | .minimum_version_id_old = 1, | |
463 | .post_load = g364fb_post_load, | |
464 | .fields = (VMStateField[]) { | |
465 | VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size), | |
466 | VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3), | |
467 | VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9), | |
468 | VMSTATE_UINT16_ARRAY(cursor, G364State, 512), | |
469 | VMSTATE_UINT32(cursor_position, G364State), | |
470 | VMSTATE_UINT32(ctla, G364State), | |
471 | VMSTATE_UINT32(top_of_screen, G364State), | |
472 | VMSTATE_UINT32(width, G364State), | |
473 | VMSTATE_UINT32(height, G364State), | |
474 | VMSTATE_END_OF_LIST() | |
475 | } | |
476 | }; | |
1fc3d392 | 477 | |
380cd056 GH |
478 | static const GraphicHwOps g364fb_ops = { |
479 | .invalidate = g364fb_invalidate_display, | |
480 | .gfx_update = g364fb_update_display, | |
481 | }; | |
482 | ||
97a3f6ff | 483 | static void g364fb_init(DeviceState *dev, G364State *s) |
1fc3d392 | 484 | { |
97a3f6ff | 485 | s->vram = g_malloc0(s->vram_size); |
1fc3d392 | 486 | |
5643706a | 487 | s->con = graphic_console_init(dev, 0, &g364fb_ops, s); |
1fc3d392 | 488 | |
2c9b15ca PB |
489 | memory_region_init_io(&s->mem_ctrl, NULL, &g364fb_ctrl_ops, s, "ctrl", 0x180000); |
490 | memory_region_init_ram_ptr(&s->mem_vram, NULL, "vram", | |
97a3f6ff | 491 | s->vram_size, s->vram); |
c5705a77 | 492 | vmstate_register_ram(&s->mem_vram, dev); |
97a3f6ff HP |
493 | memory_region_set_coalescing(&s->mem_vram); |
494 | } | |
495 | ||
0f31aa86 AF |
496 | #define TYPE_G364 "sysbus-g364" |
497 | #define G364(obj) OBJECT_CHECK(G364SysBusState, (obj), TYPE_G364) | |
498 | ||
97a3f6ff | 499 | typedef struct { |
0f31aa86 AF |
500 | SysBusDevice parent_obj; |
501 | ||
97a3f6ff HP |
502 | G364State g364; |
503 | } G364SysBusState; | |
1fc3d392 | 504 | |
0f31aa86 | 505 | static int g364fb_sysbus_init(SysBusDevice *sbd) |
97a3f6ff | 506 | { |
0f31aa86 AF |
507 | DeviceState *dev = DEVICE(sbd); |
508 | G364SysBusState *sbs = G364(dev); | |
509 | G364State *s = &sbs->g364; | |
97a3f6ff | 510 | |
0f31aa86 AF |
511 | g364fb_init(dev, s); |
512 | sysbus_init_irq(sbd, &s->irq); | |
513 | sysbus_init_mmio(sbd, &s->mem_ctrl); | |
514 | sysbus_init_mmio(sbd, &s->mem_vram); | |
1fc3d392 AJ |
515 | |
516 | return 0; | |
517 | } | |
97a3f6ff HP |
518 | |
519 | static void g364fb_sysbus_reset(DeviceState *d) | |
520 | { | |
0f31aa86 AF |
521 | G364SysBusState *s = G364(d); |
522 | ||
97a3f6ff HP |
523 | g364fb_reset(&s->g364); |
524 | } | |
525 | ||
999e12bb | 526 | static Property g364fb_sysbus_properties[] = { |
c7bcc85d | 527 | DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size, |
999e12bb AL |
528 | 8 * 1024 * 1024), |
529 | DEFINE_PROP_END_OF_LIST(), | |
530 | }; | |
531 | ||
532 | static void g364fb_sysbus_class_init(ObjectClass *klass, void *data) | |
533 | { | |
39bffca2 | 534 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
535 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
536 | ||
537 | k->init = g364fb_sysbus_init; | |
125ee0ed | 538 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); |
39bffca2 AL |
539 | dc->desc = "G364 framebuffer"; |
540 | dc->reset = g364fb_sysbus_reset; | |
541 | dc->vmsd = &vmstate_g364fb; | |
542 | dc->props = g364fb_sysbus_properties; | |
999e12bb AL |
543 | } |
544 | ||
8c43a6f0 | 545 | static const TypeInfo g364fb_sysbus_info = { |
0f31aa86 | 546 | .name = TYPE_G364, |
39bffca2 AL |
547 | .parent = TYPE_SYS_BUS_DEVICE, |
548 | .instance_size = sizeof(G364SysBusState), | |
549 | .class_init = g364fb_sysbus_class_init, | |
97a3f6ff HP |
550 | }; |
551 | ||
83f7d43a | 552 | static void g364fb_register_types(void) |
97a3f6ff | 553 | { |
39bffca2 | 554 | type_register_static(&g364fb_sysbus_info); |
97a3f6ff HP |
555 | } |
556 | ||
83f7d43a | 557 | type_init(g364fb_register_types) |