[qemu.git] / target-mips / helper.c

/*
 *  MIPS emulation helpers for qemu.
 * 
 *  Copyright (c) 2004-2005 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <stdarg.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <signal.h>
#include <assert.h>

#include "cpu.h"
#include "exec-all.h"

enum {
    TLBRET_DIRTY = -4,
    TLBRET_INVALID = -3,
    TLBRET_NOMATCH = -2,
    TLBRET_BADADDR = -1,
    TLBRET_MATCH = 0
};

/* MIPS32 4K MMU emulation */
#ifdef MIPS_USES_R4K_TLB
static int map_address (CPUState *env, target_ulong *physical, int *prot,
                        target_ulong address, int rw, int access_type)
{
    target_ulong tag = address & (TARGET_PAGE_MASK << 1);
    uint8_t ASID = env->CP0_EntryHi & 0xFF;
    tlb_t *tlb;
    int i, n;

    for (i = 0; i < env->tlb_in_use; i++) {
        tlb = &env->tlb[i];
        /* Check ASID, virtual page number & size */
        if ((tlb->G == 1 || tlb->ASID == ASID) &&
            tlb->VPN == tag && address < tlb->end2) {
            /* TLB match */
            n = (address >> TARGET_PAGE_BITS) & 1;
            /* Check access rights */
           if (!(n ? tlb->V1 : tlb->V0))
                return TLBRET_INVALID;
           if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
                *physical = tlb->PFN[n] | (address & ~TARGET_PAGE_MASK);
                *prot = PAGE_READ;
                if (n ? tlb->D1 : tlb->D0)
                    *prot |= PAGE_WRITE;
                return TLBRET_MATCH;
            }
            return TLBRET_DIRTY;
        }
    }
    return TLBRET_NOMATCH;
}
#endif

static int get_physical_address (CPUState *env, target_ulong *physical,
                                int *prot, target_ulong address,
                                int rw, int access_type)
{
    /* User mode can only access useg */
    int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
    int ret = TLBRET_MATCH;

#if 0
    if (logfile) {
        fprintf(logfile, "user mode %d h %08x\n",
                user_mode, env->hflags);
    }
#endif
    if (user_mode && address > 0x7FFFFFFFUL)
        return TLBRET_BADADDR;
    if (address < (int32_t)0x80000000UL) {
        if (!(env->hflags & MIPS_HFLAG_ERL)) {
#ifdef MIPS_USES_R4K_TLB
            ret = map_address(env, physical, prot, address, rw, access_type);
#else
            *physical = address + 0x40000000UL;
            *prot = PAGE_READ | PAGE_WRITE;
#endif
        } else {
            *physical = address;
            *prot = PAGE_READ | PAGE_WRITE;
        }
    } else if (address < (int32_t)0xA0000000UL) {
        /* kseg0 */
        /* XXX: check supervisor mode */
        *physical = address - (int32_t)0x80000000UL;
        *prot = PAGE_READ | PAGE_WRITE;
    } else if (address < (int32_t)0xC0000000UL) {
        /* kseg1 */
        /* XXX: check supervisor mode */
        *physical = address - (int32_t)0xA0000000UL;
        *prot = PAGE_READ | PAGE_WRITE;
    } else if (address < (int32_t)0xE0000000UL) {
        /* kseg2 */
#ifdef MIPS_USES_R4K_TLB
        ret = map_address(env, physical, prot, address, rw, access_type);
#else
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
#endif
    } else {
        /* kseg3 */
        /* XXX: check supervisor mode */
        /* XXX: debug segment is not emulated */
#ifdef MIPS_USES_R4K_TLB
        ret = map_address(env, physical, prot, address, rw, access_type);
#else
        *physical = address;
        *prot = PAGE_READ | PAGE_WRITE;
#endif
    }
#if 0
    if (logfile) {
        fprintf(logfile, TLSZ " %d %d => " TLSZ " %d (%d)\n",
		address, rw, access_type, *physical, *prot, ret);
    }
#endif

    return ret;
}

#if defined(CONFIG_USER_ONLY) 
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    return addr;
}
#else
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
    target_ulong phys_addr;
    int prot;

    if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
        return -1;
    return phys_addr;
}

void cpu_mips_init_mmu (CPUState *env)
{
}
#endif /* !defined(CONFIG_USER_ONLY) */

int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                               int is_user, int is_softmmu)
{
    target_ulong physical;
    int prot;
    int exception = 0, error_code = 0;
    int access_type;
    int ret = 0;

    if (logfile) {
#if 0
        cpu_dump_state(env, logfile, fprintf, 0);
#endif
        fprintf(logfile, "%s pc " TLSZ " ad " TLSZ " rw %d is_user %d smmu %d\n",
                __func__, env->PC, address, rw, is_user, is_softmmu);
    }

    rw &= 1;

    /* data access */
    /* XXX: put correct access by using cpu_restore_state()
       correctly */
    access_type = ACCESS_INT;
    if (env->user_mode_only) {
        /* user mode only emulation */
        ret = TLBRET_NOMATCH;
        goto do_fault;
    }
    ret = get_physical_address(env, &physical, &prot,
                               address, rw, access_type);
    if (logfile) {
        fprintf(logfile, "%s address=" TLSZ " ret %d physical " TLSZ " prot %d\n",
                __func__, address, ret, physical, prot);
    }
    if (ret == TLBRET_MATCH) {
       ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
                          physical & TARGET_PAGE_MASK, prot,
                          is_user, is_softmmu);
    } else if (ret < 0) {
    do_fault:
        switch (ret) {
        default:
        case TLBRET_BADADDR:
            /* Reference to kernel address from user mode or supervisor mode */
            /* Reference to supervisor address from user mode */
            if (rw)
                exception = EXCP_AdES;
            else
                exception = EXCP_AdEL;
            break;
        case TLBRET_NOMATCH:
            /* No TLB match for a mapped address */
            if (rw)
                exception = EXCP_TLBS;
            else
                exception = EXCP_TLBL;
            error_code = 1;
            break;
        case TLBRET_INVALID:
            /* TLB match with no valid bit */
            if (rw)
                exception = EXCP_TLBS;
            else
                exception = EXCP_TLBL;
            break;
        case TLBRET_DIRTY:
            /* TLB match but 'D' bit is cleared */
            exception = EXCP_LTLBL;
            break;
                
        }
        /* Raise exception */
        env->CP0_BadVAddr = address;
        env->CP0_Context = (env->CP0_Context & 0xff800000) |
	                   ((address >> 9) &   0x007ffff0);
        env->CP0_EntryHi =
            (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
        env->exception_index = exception;
        env->error_code = error_code;
        ret = 1;
    }

    return ret;
}

#if defined(CONFIG_USER_ONLY)
void do_interrupt (CPUState *env)
{
    env->exception_index = EXCP_NONE;
}
#else
void do_interrupt (CPUState *env)
{
    target_ulong offset;
    int cause = -1;

    if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
        fprintf(logfile, "%s enter: PC " TLSZ " EPC " TLSZ " cause %d excp %d\n",
                __func__, env->PC, env->CP0_EPC, cause, env->exception_index);
    }
    if (env->exception_index == EXCP_EXT_INTERRUPT &&
        (env->hflags & MIPS_HFLAG_DM))
        env->exception_index = EXCP_DINT;
    offset = 0x180;
    switch (env->exception_index) {
    case EXCP_DSS:
        env->CP0_Debug |= 1 << CP0DB_DSS;
        /* Debug single step cannot be raised inside a delay slot and
         * resume will always occur on the next instruction
         * (but we assume the pc has always been updated during
         *  code translation).
         */
        env->CP0_DEPC = env->PC;
        goto enter_debug_mode;
    case EXCP_DINT:
        env->CP0_Debug |= 1 << CP0DB_DINT;
        goto set_DEPC;
    case EXCP_DIB:
        env->CP0_Debug |= 1 << CP0DB_DIB;
        goto set_DEPC;
    case EXCP_DBp:
        env->CP0_Debug |= 1 << CP0DB_DBp;
        goto set_DEPC;
    case EXCP_DDBS:
        env->CP0_Debug |= 1 << CP0DB_DDBS;
        goto set_DEPC;
    case EXCP_DDBL:
        env->CP0_Debug |= 1 << CP0DB_DDBL;
        goto set_DEPC;
    set_DEPC:
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
               come back to the jump.  */
            env->CP0_DEPC = env->PC - 4;
            env->hflags &= ~MIPS_HFLAG_BMASK;
        } else {
            env->CP0_DEPC = env->PC;
        }
    enter_debug_mode:
        env->hflags |= MIPS_HFLAG_DM;
        /* EJTAG probe trap enable is not implemented... */
        env->PC = (int32_t)0xBFC00480;
        break;
    case EXCP_RESET:
        cpu_reset(env);
        break;
    case EXCP_SRESET:
        env->CP0_Status = (1 << CP0St_SR);
        env->CP0_WatchLo = 0;
        goto set_error_EPC;
    case EXCP_NMI:
        env->CP0_Status = (1 << CP0St_NMI);
    set_error_EPC:
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
               come back to the jump.  */
            env->CP0_ErrorEPC = env->PC - 4;
            env->hflags &= ~MIPS_HFLAG_BMASK;
        } else {
            env->CP0_ErrorEPC = env->PC;
        }
        env->hflags |= MIPS_HFLAG_ERL;
	env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
        env->PC = (int32_t)0xBFC00000;
        break;
    case EXCP_MCHECK:
        cause = 24;
        goto set_EPC;
    case EXCP_EXT_INTERRUPT:
        cause = 0;
        if (env->CP0_Cause & (1 << CP0Ca_IV))
            offset = 0x200;
        goto set_EPC;
    case EXCP_DWATCH:
        cause = 23;
        /* XXX: TODO: manage defered watch exceptions */
        goto set_EPC;
    case EXCP_AdEL:
    case EXCP_AdES:
        cause = 4;
        goto set_EPC;
    case EXCP_TLBL:
        cause = 2;
        if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
            offset = 0x000;
        goto set_EPC;
    case EXCP_IBE:
        cause = 6;
        goto set_EPC;
    case EXCP_DBE:
        cause = 7;
        goto set_EPC;
    case EXCP_SYSCALL:
        cause = 8;
        goto set_EPC;
    case EXCP_BREAK:
        cause = 9;
        goto set_EPC;
    case EXCP_RI:
        cause = 10;
        goto set_EPC;
    case EXCP_CpU:
        cause = 11;
        env->CP0_Cause = (env->CP0_Cause & ~0x03000000) | (env->error_code << 28);
        goto set_EPC;
    case EXCP_OVERFLOW:
        cause = 12;
        goto set_EPC;
    case EXCP_TRAP:
        cause = 13;
        goto set_EPC;
    case EXCP_LTLBL:
        cause = 1;
        goto set_EPC;
    case EXCP_TLBS:
        cause = 3;
        if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
            offset = 0x000;
        goto set_EPC;
    set_EPC:
        if (env->hflags & MIPS_HFLAG_BMASK) {
            /* If the exception was raised from a delay slot,
               come back to the jump.  */
            env->CP0_EPC = env->PC - 4;
            env->CP0_Cause |= 0x80000000;
            env->hflags &= ~MIPS_HFLAG_BMASK;
        } else {
            env->CP0_EPC = env->PC;
            env->CP0_Cause &= ~0x80000000;
        }
        if (env->CP0_Status & (1 << CP0St_BEV)) {
            env->PC = (int32_t)0xBFC00200;
        } else {
            env->PC = (int32_t)0x80000000;
        }
        env->hflags |= MIPS_HFLAG_EXL;
        env->CP0_Status |= (1 << CP0St_EXL);
        env->PC += offset;
        env->CP0_Cause = (env->CP0_Cause & ~0x7C) | (cause << 2);
        break;
    default:
        if (logfile) {
            fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
                    env->exception_index);
        }
        printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
        exit(1);
    }
    if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
        fprintf(logfile, "%s: PC " TLSZ " EPC " TLSZ " cause %d excp %d\n"
                "    S %08x C %08x A " TLSZ " D " TLSZ "\n",
                __func__, env->PC, env->CP0_EPC, cause, env->exception_index,
                env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
                env->CP0_DEPC);
    }
    env->exception_index = EXCP_NONE;
}
#endif /* !defined(CONFIG_USER_ONLY) */

void invalidate_tlb (CPUState *env, int idx, int use_extra)
{
    tlb_t *tlb;
    target_ulong addr;
    uint8_t ASID;

    ASID = env->CP0_EntryHi & 0xFF;

    tlb = &env->tlb[idx];
    /* The qemu TLB is flushed then the ASID changes, so no need to
       flush these entries again.  */
    if (tlb->G == 0 && tlb->ASID != ASID) {
        return;
    }

    if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
        /* For tlbwr, we can shadow the discarded entry into
	   a new (fake) TLB entry, as long as the guest can not
	   tell that it's there.  */
        env->tlb[env->tlb_in_use] = *tlb;
        env->tlb_in_use++;
        return;
    }

    if (tlb->V0) {
        addr = tlb->VPN;
        while (addr < tlb->end) {
            tlb_flush_page (env, addr);
            addr += TARGET_PAGE_SIZE;
        }
    }
    if (tlb->V1) {
        addr = tlb->end;
        while (addr < tlb->end2) {
            tlb_flush_page (env, addr);
            addr += TARGET_PAGE_SIZE;
        }
    }
}
Commit	Line	Data
6af0bf9c FB	1	/*
	2	* MIPS emulation helpers for qemu.
	3	*
	4	* Copyright (c) 2004-2005 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
e37e863f FB	20	#include <stdarg.h>
	21	#include <stdlib.h>
	22	#include <stdio.h>
	23	#include <string.h>
	24	#include <inttypes.h>
	25	#include <signal.h>
	26	#include <assert.h>
	27
	28	#include "cpu.h"
	29	#include "exec-all.h"
6af0bf9c	30
43057ab1 FB	31	enum {
	32	TLBRET_DIRTY = -4,
	33	TLBRET_INVALID = -3,
	34	TLBRET_NOMATCH = -2,
	35	TLBRET_BADADDR = -1,
	36	TLBRET_MATCH = 0
	37	};
	38
6af0bf9c	39	/* MIPS32 4K MMU emulation */
9fb63ac2	40	#ifdef MIPS_USES_R4K_TLB
6af0bf9c FB	41	static int map_address (CPUState env, target_ulong physical, int *prot,
	42	target_ulong address, int rw, int access_type)
	43	{
43057ab1 FB	44	target_ulong tag = address & (TARGET_PAGE_MASK << 1);
43057ab1 FB	45	uint8_t ASID = env->CP0_EntryHi & 0xFF;
6af0bf9c	46	tlb_t *tlb;
6af0bf9c	47	int i, n;
6af0bf9c	48
814b9a47	49	for (i = 0; i < env->tlb_in_use; i++) {
6af0bf9c FB	50	tlb = &env->tlb[i];
	51	/* Check ASID, virtual page number & size */
	52	if ((tlb->G == 1 \|\| tlb->ASID == ASID) &&
4ad40f36	53	tlb->VPN == tag && address < tlb->end2) {
6af0bf9c	54	/* TLB match */
43057ab1	55	n = (address >> TARGET_PAGE_BITS) & 1;
6af0bf9c	56	/* Check access rights */
43057ab1 FB	57	if (!(n ? tlb->V1 : tlb->V0))
	58	return TLBRET_INVALID;
	59	if (rw == 0 \|\| (n ? tlb->D1 : tlb->D0)) {
	60	*physical = tlb->PFN[n] \| (address & ~TARGET_PAGE_MASK);
9fb63ac2	61	*prot = PAGE_READ;
98c1b82b	62	if (n ? tlb->D1 : tlb->D0)
9fb63ac2	63	*prot \|= PAGE_WRITE;
43057ab1	64	return TLBRET_MATCH;
6af0bf9c	65	}
43057ab1	66	return TLBRET_DIRTY;
6af0bf9c FB	67	}
6af0bf9c FB	68	}
43057ab1	69	return TLBRET_NOMATCH;
6af0bf9c FB	70	}
	71	#endif
	72
43057ab1 FB	73	static int get_physical_address (CPUState env, target_ulong physical,
	74	int *prot, target_ulong address,
	75	int rw, int access_type)
6af0bf9c	76	{
6af0bf9c	77	/* User mode can only access useg */
43057ab1 FB	78	int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
	79	int ret = TLBRET_MATCH;
	80
6af0bf9c FB	81	#if 0
	82	if (logfile) {
	83	fprintf(logfile, "user mode %d h %08x\n",
	84	user_mode, env->hflags);
	85	}
	86	#endif
	87	if (user_mode && address > 0x7FFFFFFFUL)
43057ab1	88	return TLBRET_BADADDR;
5dc4b744	89	if (address < (int32_t)0x80000000UL) {
9fb63ac2 FB	90	if (!(env->hflags & MIPS_HFLAG_ERL)) {
	91	#ifdef MIPS_USES_R4K_TLB
	92	ret = map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	93	#else
	94	*physical = address + 0x40000000UL;
	95	*prot = PAGE_READ \| PAGE_WRITE;
	96	#endif
	97	} else {
	98	*physical = address;
	99	*prot = PAGE_READ \| PAGE_WRITE;
	100	}
5dc4b744	101	} else if (address < (int32_t)0xA0000000UL) {
6af0bf9c FB	102	/* kseg0 */
6af0bf9c FB	103	/* XXX: check supervisor mode */
5dc4b744	104	*physical = address - (int32_t)0x80000000UL;
6af0bf9c	105	*prot = PAGE_READ \| PAGE_WRITE;
5dc4b744	106	} else if (address < (int32_t)0xC0000000UL) {
6af0bf9c FB	107	/* kseg1 */
6af0bf9c FB	108	/* XXX: check supervisor mode */
5dc4b744	109	*physical = address - (int32_t)0xA0000000UL;
6af0bf9c	110	*prot = PAGE_READ \| PAGE_WRITE;
5dc4b744	111	} else if (address < (int32_t)0xE0000000UL) {
6af0bf9c	112	/* kseg2 */
9fb63ac2 FB	113	#ifdef MIPS_USES_R4K_TLB
9fb63ac2 FB	114	ret = map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	115	#else
	116	*physical = address;
	117	*prot = PAGE_READ \| PAGE_WRITE;
	118	#endif
	119	} else {
	120	/* kseg3 */
	121	/* XXX: check supervisor mode */
	122	/* XXX: debug segment is not emulated */
9fb63ac2 FB	123	#ifdef MIPS_USES_R4K_TLB
9fb63ac2 FB	124	ret = map_address(env, physical, prot, address, rw, access_type);
6af0bf9c FB	125	#else
	126	*physical = address;
	127	*prot = PAGE_READ \| PAGE_WRITE;
	128	#endif
	129	}
	130	#if 0
	131	if (logfile) {
c570fd16 TS	132	fprintf(logfile, TLSZ " %d %d => " TLSZ " %d (%d)\n",
c570fd16 TS	133	address, rw, access_type, physical, prot, ret);
6af0bf9c FB	134	}
	135	#endif
	136
	137	return ret;
	138	}
	139
	140	#if defined(CONFIG_USER_ONLY)
	141	target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
	142	{
	143	return addr;
	144	}
	145	#else
	146	target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
	147	{
	148	target_ulong phys_addr;
	149	int prot;
	150
	151	if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
	152	return -1;
	153	return phys_addr;
	154	}
6af0bf9c FB	155
	156	void cpu_mips_init_mmu (CPUState *env)
	157	{
	158	}
6af0bf9c FB	159	#endif /* !defined(CONFIG_USER_ONLY) */
	160
	161	int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
	162	int is_user, int is_softmmu)
	163	{
	164	target_ulong physical;
	165	int prot;
	166	int exception = 0, error_code = 0;
	167	int access_type;
	168	int ret = 0;
	169
	170	if (logfile) {
4ad40f36	171	#if 0
6af0bf9c	172	cpu_dump_state(env, logfile, fprintf, 0);
4ad40f36	173	#endif
c570fd16	174	fprintf(logfile, "%s pc " TLSZ " ad " TLSZ " rw %d is_user %d smmu %d\n",
6af0bf9c FB	175	__func__, env->PC, address, rw, is_user, is_softmmu);
6af0bf9c FB	176	}
4ad40f36 FB	177
	178	rw &= 1;
	179
6af0bf9c FB	180	/* data access */
	181	/* XXX: put correct access by using cpu_restore_state()
	182	correctly */
	183	access_type = ACCESS_INT;
	184	if (env->user_mode_only) {
	185	/* user mode only emulation */
43057ab1	186	ret = TLBRET_NOMATCH;
6af0bf9c FB	187	goto do_fault;
	188	}
	189	ret = get_physical_address(env, &physical, &prot,
	190	address, rw, access_type);
	191	if (logfile) {
c570fd16	192	fprintf(logfile, "%s address=" TLSZ " ret %d physical " TLSZ " prot %d\n",
6af0bf9c FB	193	__func__, address, ret, physical, prot);
6af0bf9c FB	194	}
43057ab1 FB	195	if (ret == TLBRET_MATCH) {
	196	ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
	197	physical & TARGET_PAGE_MASK, prot,
	198	is_user, is_softmmu);
6af0bf9c FB	199	} else if (ret < 0) {
	200	do_fault:
	201	switch (ret) {
	202	default:
43057ab1	203	case TLBRET_BADADDR:
6af0bf9c FB	204	/* Reference to kernel address from user mode or supervisor mode */
	205	/* Reference to supervisor address from user mode */
	206	if (rw)
	207	exception = EXCP_AdES;
	208	else
	209	exception = EXCP_AdEL;
	210	break;
43057ab1	211	case TLBRET_NOMATCH:
6af0bf9c FB	212	/* No TLB match for a mapped address */
	213	if (rw)
	214	exception = EXCP_TLBS;
	215	else
	216	exception = EXCP_TLBL;
	217	error_code = 1;
	218	break;
43057ab1	219	case TLBRET_INVALID:
6af0bf9c FB	220	/* TLB match with no valid bit */
	221	if (rw)
	222	exception = EXCP_TLBS;
	223	else
	224	exception = EXCP_TLBL;
6af0bf9c	225	break;
43057ab1	226	case TLBRET_DIRTY:
6af0bf9c FB	227	/* TLB match but 'D' bit is cleared */
	228	exception = EXCP_LTLBL;
	229	break;
	230
	231	}
6af0bf9c FB	232	/* Raise exception */
6af0bf9c FB	233	env->CP0_BadVAddr = address;
85498508	234	env->CP0_Context = (env->CP0_Context & 0xff800000) \|
4ad40f36	235	((address >> 9) & 0x007ffff0);
6af0bf9c	236	env->CP0_EntryHi =
43057ab1	237	(env->CP0_EntryHi & 0xFF) \| (address & (TARGET_PAGE_MASK << 1));
6af0bf9c FB	238	env->exception_index = exception;
	239	env->error_code = error_code;
	240	ret = 1;
	241	}
	242
	243	return ret;
	244	}
	245
ca7c2b1b TS	246	#if defined(CONFIG_USER_ONLY)
	247	void do_interrupt (CPUState *env)
	248	{
	249	env->exception_index = EXCP_NONE;
	250	}
	251	#else
6af0bf9c FB	252	void do_interrupt (CPUState *env)
6af0bf9c FB	253	{
aa328add	254	target_ulong offset;
6af0bf9c FB	255	int cause = -1;
	256
	257	if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
c570fd16	258	fprintf(logfile, "%s enter: PC " TLSZ " EPC " TLSZ " cause %d excp %d\n",
6af0bf9c FB	259	__func__, env->PC, env->CP0_EPC, cause, env->exception_index);
	260	}
	261	if (env->exception_index == EXCP_EXT_INTERRUPT &&
	262	(env->hflags & MIPS_HFLAG_DM))
	263	env->exception_index = EXCP_DINT;
	264	offset = 0x180;
	265	switch (env->exception_index) {
	266	case EXCP_DSS:
	267	env->CP0_Debug \|= 1 << CP0DB_DSS;
	268	/* Debug single step cannot be raised inside a delay slot and
	269	* resume will always occur on the next instruction
	270	* (but we assume the pc has always been updated during
	271	* code translation).
	272	*/
	273	env->CP0_DEPC = env->PC;
	274	goto enter_debug_mode;
	275	case EXCP_DINT:
	276	env->CP0_Debug \|= 1 << CP0DB_DINT;
	277	goto set_DEPC;
	278	case EXCP_DIB:
	279	env->CP0_Debug \|= 1 << CP0DB_DIB;
	280	goto set_DEPC;
	281	case EXCP_DBp:
	282	env->CP0_Debug \|= 1 << CP0DB_DBp;
	283	goto set_DEPC;
	284	case EXCP_DDBS:
	285	env->CP0_Debug \|= 1 << CP0DB_DDBS;
	286	goto set_DEPC;
	287	case EXCP_DDBL:
	288	env->CP0_Debug \|= 1 << CP0DB_DDBL;
	289	goto set_DEPC;
	290	set_DEPC:
4ad40f36	291	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c	292	/* If the exception was raised from a delay slot,
aa328add	293	come back to the jump. */
6af0bf9c	294	env->CP0_DEPC = env->PC - 4;
4ad40f36	295	env->hflags &= ~MIPS_HFLAG_BMASK;
6af0bf9c FB	296	} else {
	297	env->CP0_DEPC = env->PC;
	298	}
	299	enter_debug_mode:
	300	env->hflags \|= MIPS_HFLAG_DM;
	301	/* EJTAG probe trap enable is not implemented... */
5dc4b744	302	env->PC = (int32_t)0xBFC00480;
6af0bf9c FB	303	break;
6af0bf9c FB	304	case EXCP_RESET:
aa328add TS	305	cpu_reset(env);
aa328add TS	306	break;
6af0bf9c	307	case EXCP_SRESET:
aa328add	308	env->CP0_Status = (1 << CP0St_SR);
6af0bf9c FB	309	env->CP0_WatchLo = 0;
	310	goto set_error_EPC;
	311	case EXCP_NMI:
aa328add	312	env->CP0_Status = (1 << CP0St_NMI);
6af0bf9c	313	set_error_EPC:
4ad40f36	314	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c	315	/* If the exception was raised from a delay slot,
aa328add	316	come back to the jump. */
6af0bf9c	317	env->CP0_ErrorEPC = env->PC - 4;
ecd78a0a	318	env->hflags &= ~MIPS_HFLAG_BMASK;
6af0bf9c FB	319	} else {
	320	env->CP0_ErrorEPC = env->PC;
	321	}
3e382bc8	322	env->hflags \|= MIPS_HFLAG_ERL;
aa328add	323	env->CP0_Status \|= (1 << CP0St_ERL) \| (1 << CP0St_BEV);
5dc4b744	324	env->PC = (int32_t)0xBFC00000;
6af0bf9c FB	325	break;
	326	case EXCP_MCHECK:
	327	cause = 24;
	328	goto set_EPC;
	329	case EXCP_EXT_INTERRUPT:
	330	cause = 0;
	331	if (env->CP0_Cause & (1 << CP0Ca_IV))
	332	offset = 0x200;
	333	goto set_EPC;
	334	case EXCP_DWATCH:
	335	cause = 23;
	336	/* XXX: TODO: manage defered watch exceptions */
	337	goto set_EPC;
	338	case EXCP_AdEL:
	339	case EXCP_AdES:
	340	cause = 4;
	341	goto set_EPC;
	342	case EXCP_TLBL:
6af0bf9c FB	343	cause = 2;
	344	if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
	345	offset = 0x000;
	346	goto set_EPC;
	347	case EXCP_IBE:
	348	cause = 6;
	349	goto set_EPC;
	350	case EXCP_DBE:
	351	cause = 7;
	352	goto set_EPC;
	353	case EXCP_SYSCALL:
	354	cause = 8;
	355	goto set_EPC;
	356	case EXCP_BREAK:
	357	cause = 9;
	358	goto set_EPC;
	359	case EXCP_RI:
	360	cause = 10;
	361	goto set_EPC;
	362	case EXCP_CpU:
	363	cause = 11;
4ad40f36	364	env->CP0_Cause = (env->CP0_Cause & ~0x03000000) \| (env->error_code << 28);
6af0bf9c FB	365	goto set_EPC;
	366	case EXCP_OVERFLOW:
	367	cause = 12;
	368	goto set_EPC;
	369	case EXCP_TRAP:
	370	cause = 13;
	371	goto set_EPC;
	372	case EXCP_LTLBL:
	373	cause = 1;
	374	goto set_EPC;
	375	case EXCP_TLBS:
	376	cause = 3;
0d8aca8c FB	377	if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
	378	offset = 0x000;
	379	goto set_EPC;
6af0bf9c	380	set_EPC:
4ad40f36	381	if (env->hflags & MIPS_HFLAG_BMASK) {
6af0bf9c	382	/* If the exception was raised from a delay slot,
aa328add	383	come back to the jump. */
6af0bf9c FB	384	env->CP0_EPC = env->PC - 4;
6af0bf9c FB	385	env->CP0_Cause \|= 0x80000000;
4ad40f36	386	env->hflags &= ~MIPS_HFLAG_BMASK;
6af0bf9c FB	387	} else {
	388	env->CP0_EPC = env->PC;
	389	env->CP0_Cause &= ~0x80000000;
	390	}
aa328add	391	if (env->CP0_Status & (1 << CP0St_BEV)) {
5dc4b744	392	env->PC = (int32_t)0xBFC00200;
aa328add	393	} else {
5dc4b744	394	env->PC = (int32_t)0x80000000;
aa328add TS	395	}
	396	env->hflags \|= MIPS_HFLAG_EXL;
	397	env->CP0_Status \|= (1 << CP0St_EXL);
	398	env->PC += offset;
	399	env->CP0_Cause = (env->CP0_Cause & ~0x7C) \| (cause << 2);
6af0bf9c FB	400	break;
	401	default:
	402	if (logfile) {
	403	fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
	404	env->exception_index);
	405	}
	406	printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
	407	exit(1);
	408	}
6af0bf9c	409	if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
c570fd16 TS	410	fprintf(logfile, "%s: PC " TLSZ " EPC " TLSZ " cause %d excp %d\n"
c570fd16 TS	411	" S %08x C %08x A " TLSZ " D " TLSZ "\n",
6af0bf9c FB	412	__func__, env->PC, env->CP0_EPC, cause, env->exception_index,
	413	env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
	414	env->CP0_DEPC);
	415	}
	416	env->exception_index = EXCP_NONE;
	417	}
ca7c2b1b	418	#endif /* !defined(CONFIG_USER_ONLY) */
2ee4aed8 FB	419
	420	void invalidate_tlb (CPUState *env, int idx, int use_extra)
	421	{
	422	tlb_t *tlb;
	423	target_ulong addr;
	424	uint8_t ASID;
	425
	426	ASID = env->CP0_EntryHi & 0xFF;
	427
	428	tlb = &env->tlb[idx];
	429	/* The qemu TLB is flushed then the ASID changes, so no need to
	430	flush these entries again. */
	431	if (tlb->G == 0 && tlb->ASID != ASID) {
	432	return;
	433	}
	434
	435	if (use_extra && env->tlb_in_use < MIPS_TLB_MAX) {
	436	/* For tlbwr, we can shadow the discarded entry into
	437	a new (fake) TLB entry, as long as the guest can not
	438	tell that it's there. */
	439	env->tlb[env->tlb_in_use] = *tlb;
	440	env->tlb_in_use++;
	441	return;
	442	}
	443
	444	if (tlb->V0) {
	445	addr = tlb->VPN;
	446	while (addr < tlb->end) {
	447	tlb_flush_page (env, addr);
	448	addr += TARGET_PAGE_SIZE;
	449	}
	450	}
	451	if (tlb->V1) {
	452	addr = tlb->end;
	453	while (addr < tlb->end2) {
	454	tlb_flush_page (env, addr);
	455	addr += TARGET_PAGE_SIZE;
	456	}
	457	}
	458	}
	459