[qemu.git] / target / i386 / bpt_helper.c

/*
 *  i386 breakpoint helpers
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"


#ifndef CONFIG_USER_ONLY
static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
{
    return (dr7 >> (index * 2)) & 1;
}

static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
{
    return (dr7 >> (index * 2)) & 2;

}
static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
{
    return hw_global_breakpoint_enabled(dr7, index) ||
           hw_local_breakpoint_enabled(dr7, index);
}

static inline int hw_breakpoint_type(unsigned long dr7, int index)
{
    return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
}

static inline int hw_breakpoint_len(unsigned long dr7, int index)
{
    int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
    return (len == 2) ? 8 : len + 1;
}

static int hw_breakpoint_insert(CPUX86State *env, int index)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));
    target_ulong dr7 = env->dr[7];
    target_ulong drN = env->dr[index];
    int err = 0;

    switch (hw_breakpoint_type(dr7, index)) {
    case DR7_TYPE_BP_INST:
        if (hw_breakpoint_enabled(dr7, index)) {
            err = cpu_breakpoint_insert(cs, drN, BP_CPU,
                                        &env->cpu_breakpoint[index]);
        }
        break;

    case DR7_TYPE_IO_RW:
        /* Notice when we should enable calls to bpt_io.  */
        return hw_breakpoint_enabled(env->dr[7], index)
               ? HF_IOBPT_MASK : 0;

    case DR7_TYPE_DATA_WR:
        if (hw_breakpoint_enabled(dr7, index)) {
            err = cpu_watchpoint_insert(cs, drN,
                                        hw_breakpoint_len(dr7, index),
                                        BP_CPU | BP_MEM_WRITE,
                                        &env->cpu_watchpoint[index]);
        }
        break;

    case DR7_TYPE_DATA_RW:
        if (hw_breakpoint_enabled(dr7, index)) {
            err = cpu_watchpoint_insert(cs, drN,
                                        hw_breakpoint_len(dr7, index),
                                        BP_CPU | BP_MEM_ACCESS,
                                        &env->cpu_watchpoint[index]);
        }
        break;
    }
    if (err) {
        env->cpu_breakpoint[index] = NULL;
    }
    return 0;
}

static void hw_breakpoint_remove(CPUX86State *env, int index)
{
    CPUState *cs = CPU(x86_env_get_cpu(env));

    switch (hw_breakpoint_type(env->dr[7], index)) {
    case DR7_TYPE_BP_INST:
        if (env->cpu_breakpoint[index]) {
            cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
            env->cpu_breakpoint[index] = NULL;
        }
        break;

    case DR7_TYPE_DATA_WR:
    case DR7_TYPE_DATA_RW:
        if (env->cpu_breakpoint[index]) {
            cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
            env->cpu_breakpoint[index] = NULL;
        }
        break;

    case DR7_TYPE_IO_RW:
        /* HF_IOBPT_MASK cleared elsewhere.  */
        break;
    }
}

void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
{
    target_ulong old_dr7 = env->dr[7];
    int iobpt = 0;
    int i;

    new_dr7 |= DR7_FIXED_1;

    /* If nothing is changing except the global/local enable bits,
       then we can make the change more efficient.  */
    if (((old_dr7 ^ new_dr7) & ~0xff) == 0) {
        /* Fold the global and local enable bits together into the
           global fields, then xor to show which registers have
           changed collective enable state.  */
        int mod = ((old_dr7 | old_dr7 * 2) ^ (new_dr7 | new_dr7 * 2)) & 0xff;

        for (i = 0; i < DR7_MAX_BP; i++) {
            if ((mod & (2 << i * 2)) && !hw_breakpoint_enabled(new_dr7, i)) {
                hw_breakpoint_remove(env, i);
            }
        }
        env->dr[7] = new_dr7;
        for (i = 0; i < DR7_MAX_BP; i++) {
            if (mod & (2 << i * 2) && hw_breakpoint_enabled(new_dr7, i)) {
                iobpt |= hw_breakpoint_insert(env, i);
            } else if (hw_breakpoint_type(new_dr7, i) == DR7_TYPE_IO_RW
                       && hw_breakpoint_enabled(new_dr7, i)) {
                iobpt |= HF_IOBPT_MASK;
            }
        }
    } else {
        for (i = 0; i < DR7_MAX_BP; i++) {
            hw_breakpoint_remove(env, i);
        }
        env->dr[7] = new_dr7;
        for (i = 0; i < DR7_MAX_BP; i++) {
            iobpt |= hw_breakpoint_insert(env, i);
        }
    }

    env->hflags = (env->hflags & ~HF_IOBPT_MASK) | iobpt;
}

static bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
{
    target_ulong dr6;
    int reg;
    bool hit_enabled = false;

    dr6 = env->dr[6] & ~0xf;
    for (reg = 0; reg < DR7_MAX_BP; reg++) {
        bool bp_match = false;
        bool wp_match = false;

        switch (hw_breakpoint_type(env->dr[7], reg)) {
        case DR7_TYPE_BP_INST:
            if (env->dr[reg] == env->eip) {
                bp_match = true;
            }
            break;
        case DR7_TYPE_DATA_WR:
        case DR7_TYPE_DATA_RW:
            if (env->cpu_watchpoint[reg] &&
                env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT) {
                wp_match = true;
            }
            break;
        case DR7_TYPE_IO_RW:
            break;
        }
        if (bp_match || wp_match) {
            dr6 |= 1 << reg;
            if (hw_breakpoint_enabled(env->dr[7], reg)) {
                hit_enabled = true;
            }
        }
    }

    if (hit_enabled || force_dr6_update) {
        env->dr[6] = dr6;
    }

    return hit_enabled;
}

void breakpoint_handler(CPUState *cs)
{
    X86CPU *cpu = X86_CPU(cs);
    CPUX86State *env = &cpu->env;
    CPUBreakpoint *bp;

    if (cs->watchpoint_hit) {
        if (cs->watchpoint_hit->flags & BP_CPU) {
            cs->watchpoint_hit = NULL;
            if (check_hw_breakpoints(env, false)) {
                raise_exception(env, EXCP01_DB);
            } else {
                cpu_loop_exit_noexc(cs);
            }
        }
    } else {
        QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
            if (bp->pc == env->eip) {
                if (bp->flags & BP_CPU) {
                    check_hw_breakpoints(env, true);
                    raise_exception(env, EXCP01_DB);
                }
                break;
            }
        }
    }
}
#endif

void helper_single_step(CPUX86State *env)
{
#ifndef CONFIG_USER_ONLY
    check_hw_breakpoints(env, true);
    env->dr[6] |= DR6_BS;
#endif
    raise_exception(env, EXCP01_DB);
}

void helper_rechecking_single_step(CPUX86State *env)
{
    if ((env->eflags & TF_MASK) != 0) {
        helper_single_step(env);
    }
}

void helper_set_dr(CPUX86State *env, int reg, target_ulong t0)
{
#ifndef CONFIG_USER_ONLY
    switch (reg) {
    case 0: case 1: case 2: case 3:
        if (hw_breakpoint_enabled(env->dr[7], reg)
            && hw_breakpoint_type(env->dr[7], reg) != DR7_TYPE_IO_RW) {
            hw_breakpoint_remove(env, reg);
            env->dr[reg] = t0;
            hw_breakpoint_insert(env, reg);
        } else {
            env->dr[reg] = t0;
        }
        return;
    case 4:
        if (env->cr[4] & CR4_DE_MASK) {
            break;
        }
        /* fallthru */
    case 6:
        env->dr[6] = t0 | DR6_FIXED_1;
        return;
    case 5:
        if (env->cr[4] & CR4_DE_MASK) {
            break;
        }
        /* fallthru */
    case 7:
        cpu_x86_update_dr7(env, t0);
        return;
    }
    raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
#endif
}

target_ulong helper_get_dr(CPUX86State *env, int reg)
{
    switch (reg) {
    case 0: case 1: case 2: case 3: case 6: case 7:
        return env->dr[reg];
    case 4:
        if (env->cr[4] & CR4_DE_MASK) {
            break;
        } else {
            return env->dr[6];
        }
    case 5:
        if (env->cr[4] & CR4_DE_MASK) {
            break;
        } else {
            return env->dr[7];
        }
    }
    raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
}

/* Check if Port I/O is trapped by a breakpoint.  */
void helper_bpt_io(CPUX86State *env, uint32_t port,
                   uint32_t size, target_ulong next_eip)
{
#ifndef CONFIG_USER_ONLY
    target_ulong dr7 = env->dr[7];
    int i, hit = 0;

    for (i = 0; i < DR7_MAX_BP; ++i) {
        if (hw_breakpoint_type(dr7, i) == DR7_TYPE_IO_RW
            && hw_breakpoint_enabled(dr7, i)) {
            int bpt_len = hw_breakpoint_len(dr7, i);
            if (port + size - 1 >= env->dr[i]
                && port <= env->dr[i] + bpt_len - 1) {
                hit |= 1 << i;
            }
        }
    }

    if (hit) {
        env->dr[6] = (env->dr[6] & ~0xf) | hit;
        env->eip = next_eip;
        raise_exception(env, EXCP01_DB);
    }
#endif
}
Commit	Line	Data
ba4b5c65 RH	1	/*
	2	* i386 breakpoint helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
b6a0aa05	20	#include "qemu/osdep.h"
ba4b5c65	21	#include "cpu.h"
63c91552	22	#include "exec/exec-all.h"
ba4b5c65 RH	23	#include "exec/helper-proto.h"
	24
	25
93d00d0f	26	#ifndef CONFIG_USER_ONLY
696ad9e4 RH	27	static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
	28	{
	29	return (dr7 >> (index * 2)) & 1;
	30	}
	31
	32	static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
	33	{
	34	return (dr7 >> (index * 2)) & 2;
	35
	36	}
	37	static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
	38	{
	39	return hw_global_breakpoint_enabled(dr7, index) \|\|
	40	hw_local_breakpoint_enabled(dr7, index);
	41	}
	42
	43	static inline int hw_breakpoint_type(unsigned long dr7, int index)
	44	{
	45	return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
	46	}
	47
	48	static inline int hw_breakpoint_len(unsigned long dr7, int index)
	49	{
	50	int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
	51	return (len == 2) ? 8 : len + 1;
	52	}
	53
5223a942	54	static int hw_breakpoint_insert(CPUX86State *env, int index)
ba4b5c65 RH	55	{
ba4b5c65 RH	56	CPUState *cs = CPU(x86_env_get_cpu(env));
5223a942 EH	57	target_ulong dr7 = env->dr[7];
	58	target_ulong drN = env->dr[index];
	59	int err = 0;
ba4b5c65	60
5223a942	61	switch (hw_breakpoint_type(dr7, index)) {
ba4b5c65	62	case DR7_TYPE_BP_INST:
5223a942 EH	63	if (hw_breakpoint_enabled(dr7, index)) {
5223a942 EH	64	err = cpu_breakpoint_insert(cs, drN, BP_CPU,
ba4b5c65 RH	65	&env->cpu_breakpoint[index]);
	66	}
	67	break;
5223a942	68
ba4b5c65	69	case DR7_TYPE_IO_RW:
5223a942 EH	70	/* Notice when we should enable calls to bpt_io. */
	71	return hw_breakpoint_enabled(env->dr[7], index)
	72	? HF_IOBPT_MASK : 0;
	73
	74	case DR7_TYPE_DATA_WR:
	75	if (hw_breakpoint_enabled(dr7, index)) {
	76	err = cpu_watchpoint_insert(cs, drN,
	77	hw_breakpoint_len(dr7, index),
	78	BP_CPU \| BP_MEM_WRITE,
	79	&env->cpu_watchpoint[index]);
	80	}
ba4b5c65	81	break;
5223a942	82
ba4b5c65	83	case DR7_TYPE_DATA_RW:
5223a942 EH	84	if (hw_breakpoint_enabled(dr7, index)) {
	85	err = cpu_watchpoint_insert(cs, drN,
	86	hw_breakpoint_len(dr7, index),
	87	BP_CPU \| BP_MEM_ACCESS,
	88	&env->cpu_watchpoint[index]);
	89	}
ba4b5c65 RH	90	break;
ba4b5c65 RH	91	}
ba4b5c65 RH	92	if (err) {
	93	env->cpu_breakpoint[index] = NULL;
	94	}
5223a942	95	return 0;
ba4b5c65 RH	96	}
ba4b5c65 RH	97
93d00d0f	98	static void hw_breakpoint_remove(CPUX86State *env, int index)
ba4b5c65	99	{
5223a942	100	CPUState *cs = CPU(x86_env_get_cpu(env));
ba4b5c65	101
ba4b5c65 RH	102	switch (hw_breakpoint_type(env->dr[7], index)) {
ba4b5c65 RH	103	case DR7_TYPE_BP_INST:
5223a942	104	if (env->cpu_breakpoint[index]) {
ba4b5c65	105	cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
5223a942	106	env->cpu_breakpoint[index] = NULL;
ba4b5c65 RH	107	}
ba4b5c65 RH	108	break;
5223a942	109
ba4b5c65 RH	110	case DR7_TYPE_DATA_WR:
ba4b5c65 RH	111	case DR7_TYPE_DATA_RW:
5223a942 EH	112	if (env->cpu_breakpoint[index]) {
	113	cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
	114	env->cpu_breakpoint[index] = NULL;
	115	}
ba4b5c65	116	break;
5223a942	117
ba4b5c65	118	case DR7_TYPE_IO_RW:
5223a942	119	/* HF_IOBPT_MASK cleared elsewhere. */
ba4b5c65 RH	120	break;
	121	}
	122	}
	123
93d00d0f RH	124	void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
93d00d0f RH	125	{
36eb6e09	126	target_ulong old_dr7 = env->dr[7];
5223a942	127	int iobpt = 0;
93d00d0f RH	128	int i;
93d00d0f RH	129
9055330f EH	130	new_dr7 \|= DR7_FIXED_1;
9055330f EH	131
36eb6e09 RH	132	/* If nothing is changing except the global/local enable bits,
	133	then we can make the change more efficient. */
	134	if (((old_dr7 ^ new_dr7) & ~0xff) == 0) {
	135	/* Fold the global and local enable bits together into the
	136	global fields, then xor to show which registers have
	137	changed collective enable state. */
	138	int mod = ((old_dr7 \| old_dr7 * 2) ^ (new_dr7 \| new_dr7 * 2)) & 0xff;
	139
	140	for (i = 0; i < DR7_MAX_BP; i++) {
	141	if ((mod & (2 << i * 2)) && !hw_breakpoint_enabled(new_dr7, i)) {
	142	hw_breakpoint_remove(env, i);
	143	}
	144	}
	145	env->dr[7] = new_dr7;
	146	for (i = 0; i < DR7_MAX_BP; i++) {
	147	if (mod & (2 << i * 2) && hw_breakpoint_enabled(new_dr7, i)) {
5223a942 EH	148	iobpt \|= hw_breakpoint_insert(env, i);
	149	} else if (hw_breakpoint_type(new_dr7, i) == DR7_TYPE_IO_RW
	150	&& hw_breakpoint_enabled(new_dr7, i)) {
	151	iobpt \|= HF_IOBPT_MASK;
36eb6e09 RH	152	}
	153	}
	154	} else {
	155	for (i = 0; i < DR7_MAX_BP; i++) {
	156	hw_breakpoint_remove(env, i);
	157	}
	158	env->dr[7] = new_dr7;
	159	for (i = 0; i < DR7_MAX_BP; i++) {
5223a942	160	iobpt \|= hw_breakpoint_insert(env, i);
36eb6e09	161	}
93d00d0f	162	}
5223a942 EH	163
5223a942 EH	164	env->hflags = (env->hflags & ~HF_IOBPT_MASK) \| iobpt;
93d00d0f	165	}
93d00d0f	166
dd941cdc	167	static bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
ba4b5c65 RH	168	{
	169	target_ulong dr6;
	170	int reg;
	171	bool hit_enabled = false;
	172
	173	dr6 = env->dr[6] & ~0xf;
	174	for (reg = 0; reg < DR7_MAX_BP; reg++) {
	175	bool bp_match = false;
	176	bool wp_match = false;
	177
	178	switch (hw_breakpoint_type(env->dr[7], reg)) {
	179	case DR7_TYPE_BP_INST:
	180	if (env->dr[reg] == env->eip) {
	181	bp_match = true;
	182	}
	183	break;
	184	case DR7_TYPE_DATA_WR:
	185	case DR7_TYPE_DATA_RW:
	186	if (env->cpu_watchpoint[reg] &&
	187	env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT) {
	188	wp_match = true;
	189	}
	190	break;
	191	case DR7_TYPE_IO_RW:
	192	break;
	193	}
	194	if (bp_match \|\| wp_match) {
	195	dr6 \|= 1 << reg;
	196	if (hw_breakpoint_enabled(env->dr[7], reg)) {
	197	hit_enabled = true;
	198	}
	199	}
	200	}
	201
	202	if (hit_enabled \|\| force_dr6_update) {
	203	env->dr[6] = dr6;
	204	}
	205
	206	return hit_enabled;
	207	}
	208
	209	void breakpoint_handler(CPUState *cs)
	210	{
	211	X86CPU *cpu = X86_CPU(cs);
	212	CPUX86State *env = &cpu->env;
	213	CPUBreakpoint *bp;
	214
	215	if (cs->watchpoint_hit) {
	216	if (cs->watchpoint_hit->flags & BP_CPU) {
	217	cs->watchpoint_hit = NULL;
	218	if (check_hw_breakpoints(env, false)) {
	219	raise_exception(env, EXCP01_DB);
	220	} else {
6886b980	221	cpu_loop_exit_noexc(cs);
ba4b5c65 RH	222	}
	223	}
	224	} else {
	225	QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
	226	if (bp->pc == env->eip) {
	227	if (bp->flags & BP_CPU) {
	228	check_hw_breakpoints(env, true);
	229	raise_exception(env, EXCP01_DB);
	230	}
	231	break;
	232	}
	233	}
	234	}
	235	}
696ad9e4	236	#endif
ba4b5c65 RH	237
	238	void helper_single_step(CPUX86State *env)
	239	{
	240	#ifndef CONFIG_USER_ONLY
	241	check_hw_breakpoints(env, true);
	242	env->dr[6] \|= DR6_BS;
	243	#endif
	244	raise_exception(env, EXCP01_DB);
	245	}
	246
c52ab08a DE	247	void helper_rechecking_single_step(CPUX86State *env)
	248	{
	249	if ((env->eflags & TF_MASK) != 0) {
	250	helper_single_step(env);
	251	}
	252	}
	253
d0052339	254	void helper_set_dr(CPUX86State *env, int reg, target_ulong t0)
ba4b5c65 RH	255	{
ba4b5c65 RH	256	#ifndef CONFIG_USER_ONLY
d0052339 RH	257	switch (reg) {
d0052339 RH	258	case 0: case 1: case 2: case 3:
7525b550 RH	259	if (hw_breakpoint_enabled(env->dr[7], reg)
	260	&& hw_breakpoint_type(env->dr[7], reg) != DR7_TYPE_IO_RW) {
	261	hw_breakpoint_remove(env, reg);
	262	env->dr[reg] = t0;
	263	hw_breakpoint_insert(env, reg);
	264	} else {
	265	env->dr[reg] = t0;
	266	}
d0052339 RH	267	return;
	268	case 4:
	269	if (env->cr[4] & CR4_DE_MASK) {
	270	break;
	271	}
	272	/* fallthru */
	273	case 6:
462f8ed1	274	env->dr[6] = t0 \| DR6_FIXED_1;
d0052339 RH	275	return;
	276	case 5:
	277	if (env->cr[4] & CR4_DE_MASK) {
	278	break;
	279	}
	280	/* fallthru */
	281	case 7:
93d00d0f	282	cpu_x86_update_dr7(env, t0);
d0052339	283	return;
ba4b5c65	284	}
d0052339	285	raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
ba4b5c65 RH	286	#endif
ba4b5c65 RH	287	}
5223a942	288
d0052339 RH	289	target_ulong helper_get_dr(CPUX86State *env, int reg)
	290	{
	291	switch (reg) {
	292	case 0: case 1: case 2: case 3: case 6: case 7:
	293	return env->dr[reg];
	294	case 4:
	295	if (env->cr[4] & CR4_DE_MASK) {
	296	break;
	297	} else {
	298	return env->dr[6];
	299	}
	300	case 5:
	301	if (env->cr[4] & CR4_DE_MASK) {
	302	break;
	303	} else {
	304	return env->dr[7];
	305	}
	306	}
	307	raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
	308	}
	309
5223a942 EH	310	/* Check if Port I/O is trapped by a breakpoint. */
	311	void helper_bpt_io(CPUX86State *env, uint32_t port,
	312	uint32_t size, target_ulong next_eip)
	313	{
	314	#ifndef CONFIG_USER_ONLY
	315	target_ulong dr7 = env->dr[7];
	316	int i, hit = 0;
	317
	318	for (i = 0; i < DR7_MAX_BP; ++i) {
	319	if (hw_breakpoint_type(dr7, i) == DR7_TYPE_IO_RW
	320	&& hw_breakpoint_enabled(dr7, i)) {
	321	int bpt_len = hw_breakpoint_len(dr7, i);
	322	if (port + size - 1 >= env->dr[i]
	323	&& port <= env->dr[i] + bpt_len - 1) {
	324	hit \|= 1 << i;
	325	}
	326	}
	327	}
	328
	329	if (hit) {
	330	env->dr[6] = (env->dr[6] & ~0xf) \| hit;
	331	env->eip = next_eip;
	332	raise_exception(env, EXCP01_DB);
	333	}
	334	#endif
	335	}