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Change MMIO callbacks to use offsets, not absolute addresses.
[qemu.git] / hw / musicpal.c
CommitLineData
24859b68
AZ		 1/*
2 * Marvell MV88W8618 / Freecom MusicPal emulation.
3 *
4 * Copyright (c) 2008 Jan Kiszka
5 *
6 * This code is licenced under the GNU GPL v2.
7 */
8
9#include "hw.h"
10#include "arm-misc.h"
11#include "devices.h"
12#include "net.h"
13#include "sysemu.h"
14#include "boards.h"
15#include "pc.h"
16#include "qemu-timer.h"
17#include "block.h"
18#include "flash.h"
19#include "console.h"
20#include "audio/audio.h"
21#include "i2c.h"
22
23#define MP_ETH_BASE 0x80008000
24#define MP_ETH_SIZE 0x00001000
25
26#define MP_UART1_BASE 0x8000C840
27#define MP_UART2_BASE 0x8000C940
28
29#define MP_FLASHCFG_BASE 0x90006000
30#define MP_FLASHCFG_SIZE 0x00001000
31
32#define MP_AUDIO_BASE 0x90007000
33#define MP_AUDIO_SIZE 0x00001000
34
35#define MP_PIC_BASE 0x90008000
36#define MP_PIC_SIZE 0x00001000
37
38#define MP_PIT_BASE 0x90009000
39#define MP_PIT_SIZE 0x00001000
40
41#define MP_LCD_BASE 0x9000c000
42#define MP_LCD_SIZE 0x00001000
43
44#define MP_SRAM_BASE 0xC0000000
45#define MP_SRAM_SIZE 0x00020000
46
47#define MP_RAM_DEFAULT_SIZE 32*1024*1024
48#define MP_FLASH_SIZE_MAX 32*1024*1024
49
50#define MP_TIMER1_IRQ 4
51/* ... */
52#define MP_TIMER4_IRQ 7
53#define MP_EHCI_IRQ 8
54#define MP_ETH_IRQ 9
55#define MP_UART1_IRQ 11
56#define MP_UART2_IRQ 11
57#define MP_GPIO_IRQ 12
58#define MP_RTC_IRQ 28
59#define MP_AUDIO_IRQ 30
60
61static uint32_t gpio_in_state = 0xffffffff;
7c6ce4ba 62static uint32_t gpio_isr;
24859b68
AZ		 63static uint32_t gpio_out_state;
64static ram_addr_t sram_off;
65
66/* Address conversion helpers */
67static void *target2host_addr(uint32_t addr)
68{
69 if (addr < MP_SRAM_BASE) {
70 if (addr >= MP_RAM_DEFAULT_SIZE)
71 return NULL;
72 return (void *)(phys_ram_base + addr);
73 } else {
74 if (addr >= MP_SRAM_BASE + MP_SRAM_SIZE)
75 return NULL;
76 return (void *)(phys_ram_base + sram_off + addr - MP_SRAM_BASE);
77 }
78}
79
80static uint32_t host2target_addr(void *addr)
81{
82 if (addr < ((void *)phys_ram_base) + sram_off)
83 return (unsigned long)addr - (unsigned long)phys_ram_base;
84 else
85 return (unsigned long)addr - (unsigned long)phys_ram_base -
86 sram_off + MP_SRAM_BASE;
87}
88
89
90typedef enum i2c_state {
91 STOPPED = 0,
92 INITIALIZING,
93 SENDING_BIT7,
94 SENDING_BIT6,
95 SENDING_BIT5,
96 SENDING_BIT4,
97 SENDING_BIT3,
98 SENDING_BIT2,
99 SENDING_BIT1,
100 SENDING_BIT0,
101 WAITING_FOR_ACK,
102 RECEIVING_BIT7,
103 RECEIVING_BIT6,
104 RECEIVING_BIT5,
105 RECEIVING_BIT4,
106 RECEIVING_BIT3,
107 RECEIVING_BIT2,
108 RECEIVING_BIT1,
109 RECEIVING_BIT0,
110 SENDING_ACK
111} i2c_state;
112
113typedef struct i2c_interface {
114 i2c_bus *bus;
115 i2c_state state;
116 int last_data;
117 int last_clock;
118 uint8_t buffer;
119 int current_addr;
120} i2c_interface;
121
122static void i2c_enter_stop(i2c_interface *i2c)
123{
124 if (i2c->current_addr >= 0)
125 i2c_end_transfer(i2c->bus);
126 i2c->current_addr = -1;
127 i2c->state = STOPPED;
128}
129
130static void i2c_state_update(i2c_interface *i2c, int data, int clock)
131{
132 if (!i2c)
133 return;
134
135 switch (i2c->state) {
136 case STOPPED:
137 if (data == 0 && i2c->last_data == 1 && clock == 1)
138 i2c->state = INITIALIZING;
139 break;
140
141 case INITIALIZING:
142 if (clock == 0 && i2c->last_clock == 1 && data == 0)
143 i2c->state = SENDING_BIT7;
144 else
145 i2c_enter_stop(i2c);
146 break;
147
148 case SENDING_BIT7 ... SENDING_BIT0:
149 if (clock == 0 && i2c->last_clock == 1) {
150 i2c->buffer = (i2c->buffer << 1) | data;
151 i2c->state++; /* will end up in WAITING_FOR_ACK */
152 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
153 i2c_enter_stop(i2c);
154 break;
155
156 case WAITING_FOR_ACK:
157 if (clock == 0 && i2c->last_clock == 1) {
158 if (i2c->current_addr < 0) {
159 i2c->current_addr = i2c->buffer;
160 i2c_start_transfer(i2c->bus, i2c->current_addr & 0xfe,
161 i2c->buffer & 1);
162 } else
163 i2c_send(i2c->bus, i2c->buffer);
164 if (i2c->current_addr & 1) {
165 i2c->state = RECEIVING_BIT7;
166 i2c->buffer = i2c_recv(i2c->bus);
167 } else
168 i2c->state = SENDING_BIT7;
169 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
170 i2c_enter_stop(i2c);
171 break;
172
173 case RECEIVING_BIT7 ... RECEIVING_BIT0:
174 if (clock == 0 && i2c->last_clock == 1) {
175 i2c->state++; /* will end up in SENDING_ACK */
176 i2c->buffer <<= 1;
177 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
178 i2c_enter_stop(i2c);
179 break;
180
181 case SENDING_ACK:
182 if (clock == 0 && i2c->last_clock == 1) {
183 i2c->state = RECEIVING_BIT7;
184 if (data == 0)
185 i2c->buffer = i2c_recv(i2c->bus);
186 else
187 i2c_nack(i2c->bus);
188 } else if (data == 1 && i2c->last_data == 0 && clock == 1)
189 i2c_enter_stop(i2c);
190 break;
191 }
192
193 i2c->last_data = data;
194 i2c->last_clock = clock;
195}
196
197static int i2c_get_data(i2c_interface *i2c)
198{
199 if (!i2c)
200 return 0;
201
202 switch (i2c->state) {
203 case RECEIVING_BIT7 ... RECEIVING_BIT0:
204 return (i2c->buffer >> 7);
205
206 case WAITING_FOR_ACK:
207 default:
208 return 0;
209 }
210}
211
212static i2c_interface *mixer_i2c;
213
214#ifdef HAS_AUDIO
215
216/* Audio register offsets */
217#define MP_AUDIO_PLAYBACK_MODE 0x00
218#define MP_AUDIO_CLOCK_DIV 0x18
219#define MP_AUDIO_IRQ_STATUS 0x20
220#define MP_AUDIO_IRQ_ENABLE 0x24
221#define MP_AUDIO_TX_START_LO 0x28
222#define MP_AUDIO_TX_THRESHOLD 0x2C
223#define MP_AUDIO_TX_STATUS 0x38
224#define MP_AUDIO_TX_START_HI 0x40
225
226/* Status register and IRQ enable bits */
227#define MP_AUDIO_TX_HALF (1 << 6)
228#define MP_AUDIO_TX_FULL (1 << 7)
229
230/* Playback mode bits */
231#define MP_AUDIO_16BIT_SAMPLE (1 << 0)
232#define MP_AUDIO_PLAYBACK_EN (1 << 7)
233#define MP_AUDIO_CLOCK_24MHZ (1 << 9)
4001a81e 234#define MP_AUDIO_MONO (1 << 14)
24859b68
AZ		 235
236/* Wolfson 8750 I2C address */
237#define MP_WM_ADDR 0x34
238
b1d8e52e 239static const char audio_name[] = "mv88w8618";
24859b68
AZ		 240
241typedef struct musicpal_audio_state {
24859b68
AZ		 242 qemu_irq irq;
243 uint32_t playback_mode;
244 uint32_t status;
245 uint32_t irq_enable;
246 unsigned long phys_buf;
a350e694 247 int8_t *target_buffer;
24859b68
AZ		 248 unsigned int threshold;
249 unsigned int play_pos;
250 unsigned int last_free;
251 uint32_t clock_div;
252 i2c_slave *wm;
253} musicpal_audio_state;
254
255static void audio_callback(void *opaque, int free_out, int free_in)
256{
257 musicpal_audio_state *s = opaque;
4f3cb3be 258 int16_t *codec_buffer;
a350e694 259 int8_t *mem_buffer;
24859b68
AZ		 260 int pos, block_size;
261
262 if (!(s->playback_mode & MP_AUDIO_PLAYBACK_EN))
263 return;
264
265 if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE)
4001a81e
AZ		 266 free_out <<= 1;
267
268 if (!(s->playback_mode & MP_AUDIO_MONO))
24859b68
AZ		 269 free_out <<= 1;
270
271 block_size = s->threshold/2;
272 if (free_out - s->last_free < block_size)
273 return;
274
4001a81e
AZ		 275 mem_buffer = s->target_buffer + s->play_pos;
276 if (s->playback_mode & MP_AUDIO_16BIT_SAMPLE) {
277 if (s->playback_mode & MP_AUDIO_MONO) {
278 codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
279 for (pos = 0; pos < block_size; pos += 2) {
a350e694
AZ		 280 *codec_buffer++ = *(int16_t *)mem_buffer;
281 *codec_buffer++ = *(int16_t *)mem_buffer;
4f3cb3be 282 mem_buffer += 2;
4001a81e
AZ		 283 }
284 } else
285 memcpy(wm8750_dac_buffer(s->wm, block_size >> 2),
286 (uint32_t *)mem_buffer, block_size);
287 } else {
288 if (s->playback_mode & MP_AUDIO_MONO) {
289 codec_buffer = wm8750_dac_buffer(s->wm, block_size);
290 for (pos = 0; pos < block_size; pos++) {
a350e694
AZ		 291 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer);
292 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
4001a81e
AZ		 293 }
294 } else {
295 codec_buffer = wm8750_dac_buffer(s->wm, block_size >> 1);
296 for (pos = 0; pos < block_size; pos += 2) {
a350e694
AZ		 297 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
298 *codec_buffer++ = cpu_to_le16(256 * *mem_buffer++);
4001a81e 299 }
24859b68 300 }
662caa6f
AZ		 301 }
302 wm8750_dac_commit(s->wm);
24859b68
AZ		 303
304 s->last_free = free_out - block_size;
305
306 if (s->play_pos == 0) {
307 s->status |= MP_AUDIO_TX_HALF;
308 s->play_pos = block_size;
309 } else {
310 s->status |= MP_AUDIO_TX_FULL;
311 s->play_pos = 0;
312 }
313
314 if (s->status & s->irq_enable)
315 qemu_irq_raise(s->irq);
316}
317
af83e09e
AZ		 318static void musicpal_audio_clock_update(musicpal_audio_state *s)
319{
320 int rate;
321
322 if (s->playback_mode & MP_AUDIO_CLOCK_24MHZ)
323 rate = 24576000 / 64; /* 24.576MHz */
324 else
325 rate = 11289600 / 64; /* 11.2896MHz */
326
327 rate /= ((s->clock_div >> 8) & 0xff) + 1;
328
91834991 329 wm8750_set_bclk_in(s->wm, rate);
af83e09e
AZ		 330}
331
24859b68
AZ		 332static uint32_t musicpal_audio_read(void *opaque, target_phys_addr_t offset)
333{
334 musicpal_audio_state *s = opaque;
335
24859b68
AZ		 336 switch (offset) {
337 case MP_AUDIO_PLAYBACK_MODE:
338 return s->playback_mode;
339
340 case MP_AUDIO_CLOCK_DIV:
341 return s->clock_div;
342
343 case MP_AUDIO_IRQ_STATUS:
344 return s->status;
345
346 case MP_AUDIO_IRQ_ENABLE:
347 return s->irq_enable;
348
349 case MP_AUDIO_TX_STATUS:
350 return s->play_pos >> 2;
351
352 default:
353 return 0;
354 }
355}
356
357static void musicpal_audio_write(void *opaque, target_phys_addr_t offset,
358 uint32_t value)
359{
360 musicpal_audio_state *s = opaque;
361
24859b68
AZ		 362 switch (offset) {
363 case MP_AUDIO_PLAYBACK_MODE:
364 if (value & MP_AUDIO_PLAYBACK_EN &&
365 !(s->playback_mode & MP_AUDIO_PLAYBACK_EN)) {
366 s->status = 0;
367 s->last_free = 0;
368 s->play_pos = 0;
369 }
370 s->playback_mode = value;
af83e09e 371 musicpal_audio_clock_update(s);
24859b68
AZ		 372 break;
373
374 case MP_AUDIO_CLOCK_DIV:
375 s->clock_div = value;
376 s->last_free = 0;
377 s->play_pos = 0;
af83e09e 378 musicpal_audio_clock_update(s);
24859b68
AZ		 379 break;
380
381 case MP_AUDIO_IRQ_STATUS:
382 s->status &= ~value;
383 break;
384
385 case MP_AUDIO_IRQ_ENABLE:
386 s->irq_enable = value;
387 if (s->status & s->irq_enable)
388 qemu_irq_raise(s->irq);
389 break;
390
391 case MP_AUDIO_TX_START_LO:
392 s->phys_buf = (s->phys_buf & 0xFFFF0000) | (value & 0xFFFF);
393 s->target_buffer = target2host_addr(s->phys_buf);
394 s->play_pos = 0;
395 s->last_free = 0;
396 break;
397
398 case MP_AUDIO_TX_THRESHOLD:
399 s->threshold = (value + 1) * 4;
400 break;
401
402 case MP_AUDIO_TX_START_HI:
403 s->phys_buf = (s->phys_buf & 0xFFFF) | (value << 16);
404 s->target_buffer = target2host_addr(s->phys_buf);
405 s->play_pos = 0;
406 s->last_free = 0;
407 break;
408 }
409}
410
411static void musicpal_audio_reset(void *opaque)
412{
413 musicpal_audio_state *s = opaque;
414
415 s->playback_mode = 0;
416 s->status = 0;
417 s->irq_enable = 0;
418}
419
420static CPUReadMemoryFunc *musicpal_audio_readfn[] = {
421 musicpal_audio_read,
422 musicpal_audio_read,
423 musicpal_audio_read
424};
425
426static CPUWriteMemoryFunc *musicpal_audio_writefn[] = {
427 musicpal_audio_write,
428 musicpal_audio_write,
429 musicpal_audio_write
430};
431
432static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
433{
434 AudioState *audio;
435 musicpal_audio_state *s;
436 i2c_interface *i2c;
437 int iomemtype;
438
439 audio = AUD_init();
440 if (!audio) {
441 AUD_log(audio_name, "No audio state\n");
442 return NULL;
443 }
444
445 s = qemu_mallocz(sizeof(musicpal_audio_state));
446 if (!s)
447 return NULL;
24859b68
AZ		 448 s->irq = irq;
449
450 i2c = qemu_mallocz(sizeof(i2c_interface));
451 if (!i2c)
452 return NULL;
453 i2c->bus = i2c_init_bus();
454 i2c->current_addr = -1;
455
456 s->wm = wm8750_init(i2c->bus, audio);
457 if (!s->wm)
458 return NULL;
459 i2c_set_slave_address(s->wm, MP_WM_ADDR);
460 wm8750_data_req_set(s->wm, audio_callback, s);
461
462 iomemtype = cpu_register_io_memory(0, musicpal_audio_readfn,
463 musicpal_audio_writefn, s);
464 cpu_register_physical_memory(base, MP_AUDIO_SIZE, iomemtype);
465
466 qemu_register_reset(musicpal_audio_reset, s);
467
468 return i2c;
469}
470#else /* !HAS_AUDIO */
471static i2c_interface *musicpal_audio_init(uint32_t base, qemu_irq irq)
472{
473 return NULL;
474}
475#endif /* !HAS_AUDIO */
476
477/* Ethernet register offsets */
478#define MP_ETH_SMIR 0x010
479#define MP_ETH_PCXR 0x408
480#define MP_ETH_SDCMR 0x448
481#define MP_ETH_ICR 0x450
482#define MP_ETH_IMR 0x458
483#define MP_ETH_FRDP0 0x480
484#define MP_ETH_FRDP1 0x484
485#define MP_ETH_FRDP2 0x488
486#define MP_ETH_FRDP3 0x48C
487#define MP_ETH_CRDP0 0x4A0
488#define MP_ETH_CRDP1 0x4A4
489#define MP_ETH_CRDP2 0x4A8
490#define MP_ETH_CRDP3 0x4AC
491#define MP_ETH_CTDP0 0x4E0
492#define MP_ETH_CTDP1 0x4E4
493#define MP_ETH_CTDP2 0x4E8
494#define MP_ETH_CTDP3 0x4EC
495
496/* MII PHY access */
497#define MP_ETH_SMIR_DATA 0x0000FFFF
498#define MP_ETH_SMIR_ADDR 0x03FF0000
499#define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */
500#define MP_ETH_SMIR_RDVALID (1 << 27)
501
502/* PHY registers */
503#define MP_ETH_PHY1_BMSR 0x00210000
504#define MP_ETH_PHY1_PHYSID1 0x00410000
505#define MP_ETH_PHY1_PHYSID2 0x00610000
506
507#define MP_PHY_BMSR_LINK 0x0004
508#define MP_PHY_BMSR_AUTONEG 0x0008
509
510#define MP_PHY_88E3015 0x01410E20
511
512/* TX descriptor status */
513#define MP_ETH_TX_OWN (1 << 31)
514
515/* RX descriptor status */
516#define MP_ETH_RX_OWN (1 << 31)
517
518/* Interrupt cause/mask bits */
519#define MP_ETH_IRQ_RX_BIT 0
520#define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT)
521#define MP_ETH_IRQ_TXHI_BIT 2
522#define MP_ETH_IRQ_TXLO_BIT 3
523
524/* Port config bits */
525#define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */
526
527/* SDMA command bits */
528#define MP_ETH_CMD_TXHI (1 << 23)
529#define MP_ETH_CMD_TXLO (1 << 22)
530
531typedef struct mv88w8618_tx_desc {
532 uint32_t cmdstat;
533 uint16_t res;
534 uint16_t bytes;
535 uint32_t buffer;
536 uint32_t next;
537} mv88w8618_tx_desc;
538
539typedef struct mv88w8618_rx_desc {
540 uint32_t cmdstat;
541 uint16_t bytes;
542 uint16_t buffer_size;
543 uint32_t buffer;
544 uint32_t next;
545} mv88w8618_rx_desc;
546
547typedef struct mv88w8618_eth_state {
24859b68
AZ		 548 qemu_irq irq;
549 uint32_t smir;
550 uint32_t icr;
551 uint32_t imr;
552 int vlan_header;
553 mv88w8618_tx_desc *tx_queue[2];
554 mv88w8618_rx_desc *rx_queue[4];
555 mv88w8618_rx_desc *frx_queue[4];
556 mv88w8618_rx_desc *cur_rx[4];
557 VLANClientState *vc;
558} mv88w8618_eth_state;
559
560static int eth_can_receive(void *opaque)
561{
562 return 1;
563}
564
565static void eth_receive(void *opaque, const uint8_t *buf, int size)
566{
567 mv88w8618_eth_state *s = opaque;
568 mv88w8618_rx_desc *desc;
569 int i;
570
571 for (i = 0; i < 4; i++) {
572 desc = s->cur_rx[i];
573 if (!desc)
574 continue;
575 do {
576 if (le32_to_cpu(desc->cmdstat) & MP_ETH_RX_OWN &&
577 le16_to_cpu(desc->buffer_size) >= size) {
578 memcpy(target2host_addr(le32_to_cpu(desc->buffer) +
579 s->vlan_header),
580 buf, size);
581 desc->bytes = cpu_to_le16(size + s->vlan_header);
582 desc->cmdstat &= cpu_to_le32(~MP_ETH_RX_OWN);
583 s->cur_rx[i] = target2host_addr(le32_to_cpu(desc->next));
584
585 s->icr |= MP_ETH_IRQ_RX;
586 if (s->icr & s->imr)
587 qemu_irq_raise(s->irq);
588 return;
589 }
590 desc = target2host_addr(le32_to_cpu(desc->next));
591 } while (desc != s->rx_queue[i]);
592 }
593}
594
595static void eth_send(mv88w8618_eth_state *s, int queue_index)
596{
597 mv88w8618_tx_desc *desc = s->tx_queue[queue_index];
598
599 do {
600 if (le32_to_cpu(desc->cmdstat) & MP_ETH_TX_OWN) {
601 qemu_send_packet(s->vc,
602 target2host_addr(le32_to_cpu(desc->buffer)),
603 le16_to_cpu(desc->bytes));
604 desc->cmdstat &= cpu_to_le32(~MP_ETH_TX_OWN);
605 s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
606 }
607 desc = target2host_addr(le32_to_cpu(desc->next));
608 } while (desc != s->tx_queue[queue_index]);
609}
610
611static uint32_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset)
612{
613 mv88w8618_eth_state *s = opaque;
614
24859b68
AZ		 615 switch (offset) {
616 case MP_ETH_SMIR:
617 if (s->smir & MP_ETH_SMIR_OPCODE) {
618 switch (s->smir & MP_ETH_SMIR_ADDR) {
619 case MP_ETH_PHY1_BMSR:
620 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
621 MP_ETH_SMIR_RDVALID;
622 case MP_ETH_PHY1_PHYSID1:
623 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
624 case MP_ETH_PHY1_PHYSID2:
625 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
626 default:
627 return MP_ETH_SMIR_RDVALID;
628 }
629 }
630 return 0;
631
632 case MP_ETH_ICR:
633 return s->icr;
634
635 case MP_ETH_IMR:
636 return s->imr;
637
638 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
639 return host2target_addr(s->frx_queue[(offset - MP_ETH_FRDP0)/4]);
640
641 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
642 return host2target_addr(s->rx_queue[(offset - MP_ETH_CRDP0)/4]);
643
644 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
645 return host2target_addr(s->tx_queue[(offset - MP_ETH_CTDP0)/4]);
646
647 default:
648 return 0;
649 }
650}
651
652static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
653 uint32_t value)
654{
655 mv88w8618_eth_state *s = opaque;
656
24859b68
AZ		 657 switch (offset) {
658 case MP_ETH_SMIR:
659 s->smir = value;
660 break;
661
662 case MP_ETH_PCXR:
663 s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
664 break;
665
666 case MP_ETH_SDCMR:
667 if (value & MP_ETH_CMD_TXHI)
668 eth_send(s, 1);
669 if (value & MP_ETH_CMD_TXLO)
670 eth_send(s, 0);
671 if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr)
672 qemu_irq_raise(s->irq);
673 break;
674
675 case MP_ETH_ICR:
676 s->icr &= value;
677 break;
678
679 case MP_ETH_IMR:
680 s->imr = value;
681 if (s->icr & s->imr)
682 qemu_irq_raise(s->irq);
683 break;
684
685 case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
686 s->frx_queue[(offset - MP_ETH_FRDP0)/4] = target2host_addr(value);
687 break;
688
689 case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
690 s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
691 s->cur_rx[(offset - MP_ETH_CRDP0)/4] = target2host_addr(value);
692 break;
693
694 case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
695 s->tx_queue[(offset - MP_ETH_CTDP0)/4] = target2host_addr(value);
696 break;
697 }
698}
699
700static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
701 mv88w8618_eth_read,
702 mv88w8618_eth_read,
703 mv88w8618_eth_read
704};
705
706static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
707 mv88w8618_eth_write,
708 mv88w8618_eth_write,
709 mv88w8618_eth_write
710};
711
712static void mv88w8618_eth_init(NICInfo *nd, uint32_t base, qemu_irq irq)
713{
714 mv88w8618_eth_state *s;
715 int iomemtype;
716
717 s = qemu_mallocz(sizeof(mv88w8618_eth_state));
718 if (!s)
719 return;
24859b68
AZ		 720 s->irq = irq;
721 s->vc = qemu_new_vlan_client(nd->vlan, eth_receive, eth_can_receive, s);
722 iomemtype = cpu_register_io_memory(0, mv88w8618_eth_readfn,
723 mv88w8618_eth_writefn, s);
724 cpu_register_physical_memory(base, MP_ETH_SIZE, iomemtype);
725}
726
727/* LCD register offsets */
728#define MP_LCD_IRQCTRL 0x180
729#define MP_LCD_IRQSTAT 0x184
730#define MP_LCD_SPICTRL 0x1ac
731#define MP_LCD_INST 0x1bc
732#define MP_LCD_DATA 0x1c0
733
734/* Mode magics */
735#define MP_LCD_SPI_DATA 0x00100011
736#define MP_LCD_SPI_CMD 0x00104011
737#define MP_LCD_SPI_INVALID 0x00000000
738
739/* Commmands */
740#define MP_LCD_INST_SETPAGE0 0xB0
741/* ... */
742#define MP_LCD_INST_SETPAGE7 0xB7
743
744#define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
745
746typedef struct musicpal_lcd_state {
24859b68
AZ		 747 uint32_t mode;
748 uint32_t irqctrl;
749 int page;
750 int page_off;
751 DisplayState *ds;
c60e08d9 752 QEMUConsole *console;
24859b68
AZ		 753 uint8_t video_ram[128*64/8];
754} musicpal_lcd_state;
755
756static uint32_t lcd_brightness;
757
758static uint8_t scale_lcd_color(uint8_t col)
759{
760 int tmp = col;
761
762 switch (lcd_brightness) {
763 case 0x00000007: /* 0 */
764 return 0;
765
766 case 0x00020000: /* 1 */
767 return (tmp * 1) / 7;
768
769 case 0x00020001: /* 2 */
770 return (tmp * 2) / 7;
771
772 case 0x00040000: /* 3 */
773 return (tmp * 3) / 7;
774
775 case 0x00010006: /* 4 */
776 return (tmp * 4) / 7;
777
778 case 0x00020005: /* 5 */
779 return (tmp * 5) / 7;
780
781 case 0x00040003: /* 6 */
782 return (tmp * 6) / 7;
783
784 case 0x00030004: /* 7 */
785 default:
786 return col;
787 }
788}
789
0266f2c7
AZ		 790#define SET_LCD_PIXEL(depth, type) \
791static inline void glue(set_lcd_pixel, depth) \
792 (musicpal_lcd_state *s, int x, int y, type col) \
793{ \
794 int dx, dy; \
0e1f5a0c 795 type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
0266f2c7
AZ		 796\
797 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
798 for (dx = 0; dx < 3; dx++, pixel++) \
799 *pixel = col; \
24859b68 800}
0266f2c7
AZ		 801SET_LCD_PIXEL(8, uint8_t)
802SET_LCD_PIXEL(16, uint16_t)
803SET_LCD_PIXEL(32, uint32_t)
804
805#include "pixel_ops.h"
24859b68
AZ		 806
807static void lcd_refresh(void *opaque)
808{
809 musicpal_lcd_state *s = opaque;
0266f2c7 810 int x, y, col;
24859b68 811
0e1f5a0c 812 switch (ds_get_bits_per_pixel(s->ds)) {
0266f2c7
AZ		 813 case 0:
814 return;
815#define LCD_REFRESH(depth, func) \
816 case depth: \
817 col = func(scale_lcd_color((MP_LCD_TEXTCOLOR >> 16) & 0xff), \
818 scale_lcd_color((MP_LCD_TEXTCOLOR >> 8) & 0xff), \
819 scale_lcd_color(MP_LCD_TEXTCOLOR & 0xff)); \
820 for (x = 0; x < 128; x++) \
821 for (y = 0; y < 64; y++) \
822 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) \
823 glue(set_lcd_pixel, depth)(s, x, y, col); \
824 else \
825 glue(set_lcd_pixel, depth)(s, x, y, 0); \
826 break;
827 LCD_REFRESH(8, rgb_to_pixel8)
828 LCD_REFRESH(16, rgb_to_pixel16)
829 LCD_REFRESH(32, (s->ds->bgr ? rgb_to_pixel32bgr : rgb_to_pixel32))
830 default:
831 cpu_abort(cpu_single_env, "unsupported colour depth %i\n",
0e1f5a0c 832 ds_get_bits_per_pixel(s->ds));
0266f2c7 833 }
24859b68
AZ		 834
835 dpy_update(s->ds, 0, 0, 128*3, 64*3);
836}
837
167bc3d2
AZ		 838static void lcd_invalidate(void *opaque)
839{
167bc3d2
AZ		 840}
841
24859b68
AZ		 842static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
843{
844 musicpal_lcd_state *s = opaque;
845
24859b68
AZ		 846 switch (offset) {
847 case MP_LCD_IRQCTRL:
848 return s->irqctrl;
849
850 default:
851 return 0;
852 }
853}
854
855static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
856 uint32_t value)
857{
858 musicpal_lcd_state *s = opaque;
859
24859b68
AZ		 860 switch (offset) {
861 case MP_LCD_IRQCTRL:
862 s->irqctrl = value;
863 break;
864
865 case MP_LCD_SPICTRL:
866 if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD)
867 s->mode = value;
868 else
869 s->mode = MP_LCD_SPI_INVALID;
870 break;
871
872 case MP_LCD_INST:
873 if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
874 s->page = value - MP_LCD_INST_SETPAGE0;
875 s->page_off = 0;
876 }
877 break;
878
879 case MP_LCD_DATA:
880 if (s->mode == MP_LCD_SPI_CMD) {
881 if (value >= MP_LCD_INST_SETPAGE0 &&
882 value <= MP_LCD_INST_SETPAGE7) {
883 s->page = value - MP_LCD_INST_SETPAGE0;
884 s->page_off = 0;
885 }
886 } else if (s->mode == MP_LCD_SPI_DATA) {
887 s->video_ram[s->page*128 + s->page_off] = value;
888 s->page_off = (s->page_off + 1) & 127;
889 }
890 break;
891 }
892}
893
894static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
895 musicpal_lcd_read,
896 musicpal_lcd_read,
897 musicpal_lcd_read
898};
899
900static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
901 musicpal_lcd_write,
902 musicpal_lcd_write,
903 musicpal_lcd_write
904};
905
906static void musicpal_lcd_init(DisplayState *ds, uint32_t base)
907{
908 musicpal_lcd_state *s;
909 int iomemtype;
910
911 s = qemu_mallocz(sizeof(musicpal_lcd_state));
912 if (!s)
913 return;
24859b68
AZ		 914 s->ds = ds;
915 iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
916 musicpal_lcd_writefn, s);
917 cpu_register_physical_memory(base, MP_LCD_SIZE, iomemtype);
918
c60e08d9
PB		 919 s->console = graphic_console_init(ds, lcd_refresh, lcd_invalidate,
920 NULL, NULL, s);
921 qemu_console_resize(s->console, 128*3, 64*3);
24859b68
AZ		 922}
923
924/* PIC register offsets */
925#define MP_PIC_STATUS 0x00
926#define MP_PIC_ENABLE_SET 0x08
927#define MP_PIC_ENABLE_CLR 0x0C
928
929typedef struct mv88w8618_pic_state
930{
24859b68
AZ		 931 uint32_t level;
932 uint32_t enabled;
933 qemu_irq parent_irq;
934} mv88w8618_pic_state;
935
936static void mv88w8618_pic_update(mv88w8618_pic_state *s)
937{
938 qemu_set_irq(s->parent_irq, (s->level & s->enabled));
939}
940
941static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
942{
943 mv88w8618_pic_state *s = opaque;
944
945 if (level)
946 s->level |= 1 << irq;
947 else
948 s->level &= ~(1 << irq);
949 mv88w8618_pic_update(s);
950}
951
952static uint32_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset)
953{
954 mv88w8618_pic_state *s = opaque;
955
24859b68
AZ		 956 switch (offset) {
957 case MP_PIC_STATUS:
958 return s->level & s->enabled;
959
960 default:
961 return 0;
962 }
963}
964
965static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
966 uint32_t value)
967{
968 mv88w8618_pic_state *s = opaque;
969
24859b68
AZ		 970 switch (offset) {
971 case MP_PIC_ENABLE_SET:
972 s->enabled |= value;
973 break;
974
975 case MP_PIC_ENABLE_CLR:
976 s->enabled &= ~value;
977 s->level &= ~value;
978 break;
979 }
980 mv88w8618_pic_update(s);
981}
982
983static void mv88w8618_pic_reset(void *opaque)
984{
985 mv88w8618_pic_state *s = opaque;
986
987 s->level = 0;
988 s->enabled = 0;
989}
990
991static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
992 mv88w8618_pic_read,
993 mv88w8618_pic_read,
994 mv88w8618_pic_read
995};
996
997static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
998 mv88w8618_pic_write,
999 mv88w8618_pic_write,
1000 mv88w8618_pic_write
1001};
1002
1003static qemu_irq *mv88w8618_pic_init(uint32_t base, qemu_irq parent_irq)
1004{
1005 mv88w8618_pic_state *s;
1006 int iomemtype;
1007 qemu_irq *qi;
1008
1009 s = qemu_mallocz(sizeof(mv88w8618_pic_state));
1010 if (!s)
1011 return NULL;
1012 qi = qemu_allocate_irqs(mv88w8618_pic_set_irq, s, 32);
24859b68
AZ		 1013 s->parent_irq = parent_irq;
1014 iomemtype = cpu_register_io_memory(0, mv88w8618_pic_readfn,
1015 mv88w8618_pic_writefn, s);
1016 cpu_register_physical_memory(base, MP_PIC_SIZE, iomemtype);
1017
1018 qemu_register_reset(mv88w8618_pic_reset, s);
1019
1020 return qi;
1021}
1022
1023/* PIT register offsets */
1024#define MP_PIT_TIMER1_LENGTH 0x00
1025/* ... */
1026#define MP_PIT_TIMER4_LENGTH 0x0C
1027#define MP_PIT_CONTROL 0x10
1028#define MP_PIT_TIMER1_VALUE 0x14
1029/* ... */
1030#define MP_PIT_TIMER4_VALUE 0x20
1031#define MP_BOARD_RESET 0x34
1032
1033/* Magic board reset value (probably some watchdog behind it) */
1034#define MP_BOARD_RESET_MAGIC 0x10000
1035
1036typedef struct mv88w8618_timer_state {
1037 ptimer_state *timer;
1038 uint32_t limit;
1039 int freq;
1040 qemu_irq irq;
1041} mv88w8618_timer_state;
1042
1043typedef struct mv88w8618_pit_state {
1044 void *timer[4];
1045 uint32_t control;
24859b68
AZ		 1046} mv88w8618_pit_state;
1047
1048static void mv88w8618_timer_tick(void *opaque)
1049{
1050 mv88w8618_timer_state *s = opaque;
1051
1052 qemu_irq_raise(s->irq);
1053}
1054
1055static void *mv88w8618_timer_init(uint32_t freq, qemu_irq irq)
1056{
1057 mv88w8618_timer_state *s;
1058 QEMUBH *bh;
1059
1060 s = qemu_mallocz(sizeof(mv88w8618_timer_state));
1061 s->irq = irq;
1062 s->freq = freq;
1063
1064 bh = qemu_bh_new(mv88w8618_timer_tick, s);
1065 s->timer = ptimer_init(bh);
1066
1067 return s;
1068}
1069
1070static uint32_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset)
1071{
1072 mv88w8618_pit_state *s = opaque;
1073 mv88w8618_timer_state *t;
1074
24859b68
AZ		 1075 switch (offset) {
1076 case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
1077 t = s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
1078 return ptimer_get_count(t->timer);
1079
1080 default:
1081 return 0;
1082 }
1083}
1084
1085static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
1086 uint32_t value)
1087{
1088 mv88w8618_pit_state *s = opaque;
1089 mv88w8618_timer_state *t;
1090 int i;
1091
24859b68
AZ		 1092 switch (offset) {
1093 case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
1094 t = s->timer[offset >> 2];
1095 t->limit = value;
1096 ptimer_set_limit(t->timer, t->limit, 1);
1097 break;
1098
1099 case MP_PIT_CONTROL:
1100 for (i = 0; i < 4; i++) {
1101 if (value & 0xf) {
1102 t = s->timer[i];
1103 ptimer_set_limit(t->timer, t->limit, 0);
1104 ptimer_set_freq(t->timer, t->freq);
1105 ptimer_run(t->timer, 0);
1106 }
1107 value >>= 4;
1108 }
1109 break;
1110
1111 case MP_BOARD_RESET:
1112 if (value == MP_BOARD_RESET_MAGIC)
1113 qemu_system_reset_request();
1114 break;
1115 }
1116}
1117
1118static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
1119 mv88w8618_pit_read,
1120 mv88w8618_pit_read,
1121 mv88w8618_pit_read
1122};
1123
1124static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
1125 mv88w8618_pit_write,
1126 mv88w8618_pit_write,
1127 mv88w8618_pit_write
1128};
1129
1130static void mv88w8618_pit_init(uint32_t base, qemu_irq *pic, int irq)
1131{
1132 int iomemtype;
1133 mv88w8618_pit_state *s;
1134
1135 s = qemu_mallocz(sizeof(mv88w8618_pit_state));
1136 if (!s)
1137 return;
1138
24859b68
AZ		 1139 /* Letting them all run at 1 MHz is likely just a pragmatic
1140 * simplification. */
1141 s->timer[0] = mv88w8618_timer_init(1000000, pic[irq]);
1142 s->timer[1] = mv88w8618_timer_init(1000000, pic[irq + 1]);
1143 s->timer[2] = mv88w8618_timer_init(1000000, pic[irq + 2]);
1144 s->timer[3] = mv88w8618_timer_init(1000000, pic[irq + 3]);
1145
1146 iomemtype = cpu_register_io_memory(0, mv88w8618_pit_readfn,
1147 mv88w8618_pit_writefn, s);
1148 cpu_register_physical_memory(base, MP_PIT_SIZE, iomemtype);
1149}
1150
1151/* Flash config register offsets */
1152#define MP_FLASHCFG_CFGR0 0x04
1153
1154typedef struct mv88w8618_flashcfg_state {
24859b68
AZ		 1155 uint32_t cfgr0;
1156} mv88w8618_flashcfg_state;
1157
1158static uint32_t mv88w8618_flashcfg_read(void *opaque,
1159 target_phys_addr_t offset)
1160{
1161 mv88w8618_flashcfg_state *s = opaque;
1162
24859b68
AZ		 1163 switch (offset) {
1164 case MP_FLASHCFG_CFGR0:
1165 return s->cfgr0;
1166
1167 default:
1168 return 0;
1169 }
1170}
1171
1172static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
1173 uint32_t value)
1174{
1175 mv88w8618_flashcfg_state *s = opaque;
1176
24859b68
AZ		 1177 switch (offset) {
1178 case MP_FLASHCFG_CFGR0:
1179 s->cfgr0 = value;
1180 break;
1181 }
1182}
1183
1184static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
1185 mv88w8618_flashcfg_read,
1186 mv88w8618_flashcfg_read,
1187 mv88w8618_flashcfg_read
1188};
1189
1190static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
1191 mv88w8618_flashcfg_write,
1192 mv88w8618_flashcfg_write,
1193 mv88w8618_flashcfg_write
1194};
1195
1196static void mv88w8618_flashcfg_init(uint32_t base)
1197{
1198 int iomemtype;
1199 mv88w8618_flashcfg_state *s;
1200
1201 s = qemu_mallocz(sizeof(mv88w8618_flashcfg_state));
1202 if (!s)
1203 return;
1204
24859b68
AZ		 1205 s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1206 iomemtype = cpu_register_io_memory(0, mv88w8618_flashcfg_readfn,
1207 mv88w8618_flashcfg_writefn, s);
1208 cpu_register_physical_memory(base, MP_FLASHCFG_SIZE, iomemtype);
1209}
1210
1211/* Various registers in the 0x80000000 domain */
1212#define MP_BOARD_REVISION 0x2018
1213
1214#define MP_WLAN_MAGIC1 0xc11c
1215#define MP_WLAN_MAGIC2 0xc124
1216
1217#define MP_GPIO_OE_LO 0xd008
1218#define MP_GPIO_OUT_LO 0xd00c
1219#define MP_GPIO_IN_LO 0xd010
1220#define MP_GPIO_ISR_LO 0xd020
1221#define MP_GPIO_OE_HI 0xd508
1222#define MP_GPIO_OUT_HI 0xd50c
1223#define MP_GPIO_IN_HI 0xd510
1224#define MP_GPIO_ISR_HI 0xd520
1225
1226/* GPIO bits & masks */
1227#define MP_GPIO_WHEEL_VOL (1 << 8)
1228#define MP_GPIO_WHEEL_VOL_INV (1 << 9)
1229#define MP_GPIO_WHEEL_NAV (1 << 10)
1230#define MP_GPIO_WHEEL_NAV_INV (1 << 11)
1231#define MP_GPIO_LCD_BRIGHTNESS 0x00070000
1232#define MP_GPIO_BTN_FAVORITS (1 << 19)
1233#define MP_GPIO_BTN_MENU (1 << 20)
1234#define MP_GPIO_BTN_VOLUME (1 << 21)
1235#define MP_GPIO_BTN_NAVIGATION (1 << 22)
1236#define MP_GPIO_I2C_DATA_BIT 29
1237#define MP_GPIO_I2C_DATA (1 << MP_GPIO_I2C_DATA_BIT)
1238#define MP_GPIO_I2C_CLOCK_BIT 30
1239
1240/* LCD brightness bits in GPIO_OE_HI */
1241#define MP_OE_LCD_BRIGHTNESS 0x0007
1242
1243static uint32_t musicpal_read(void *opaque, target_phys_addr_t offset)
1244{
24859b68
AZ		 1245 switch (offset) {
1246 case MP_BOARD_REVISION:
1247 return 0x0031;
1248
1249 case MP_GPIO_OE_HI: /* used for LCD brightness control */
1250 return lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1251
1252 case MP_GPIO_OUT_LO:
1253 return gpio_out_state & 0xFFFF;
1254 case MP_GPIO_OUT_HI:
1255 return gpio_out_state >> 16;
1256
1257 case MP_GPIO_IN_LO:
1258 return gpio_in_state & 0xFFFF;
1259 case MP_GPIO_IN_HI:
1260 /* Update received I2C data */
1261 gpio_in_state = (gpio_in_state & ~MP_GPIO_I2C_DATA) |
1262 (i2c_get_data(mixer_i2c) << MP_GPIO_I2C_DATA_BIT);
1263 return gpio_in_state >> 16;
1264
24859b68 1265 case MP_GPIO_ISR_LO:
7c6ce4ba 1266 return gpio_isr & 0xFFFF;
24859b68 1267 case MP_GPIO_ISR_HI:
7c6ce4ba 1268 return gpio_isr >> 16;
24859b68
AZ		 1269
1270 /* Workaround to allow loading the binary-only wlandrv.ko crap
1271 * from the original Freecom firmware. */
1272 case MP_WLAN_MAGIC1:
1273 return ~3;
1274 case MP_WLAN_MAGIC2:
1275 return -1;
1276
1277 default:
1278 return 0;
1279 }
1280}
1281
1282static void musicpal_write(void *opaque, target_phys_addr_t offset,
1283 uint32_t value)
1284{
24859b68
AZ		 1285 switch (offset) {
1286 case MP_GPIO_OE_HI: /* used for LCD brightness control */
1287 lcd_brightness = (lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1288 (value & MP_OE_LCD_BRIGHTNESS);
1289 break;
1290
1291 case MP_GPIO_OUT_LO:
1292 gpio_out_state = (gpio_out_state & 0xFFFF0000) | (value & 0xFFFF);
1293 break;
1294 case MP_GPIO_OUT_HI:
1295 gpio_out_state = (gpio_out_state & 0xFFFF) | (value << 16);
1296 lcd_brightness = (lcd_brightness & 0xFFFF) |
1297 (gpio_out_state & MP_GPIO_LCD_BRIGHTNESS);
1298 i2c_state_update(mixer_i2c,
1299 (gpio_out_state >> MP_GPIO_I2C_DATA_BIT) & 1,
1300 (gpio_out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1301 break;
1302
1303 }
1304}
1305
1306/* Keyboard codes & masks */
7c6ce4ba 1307#define KEY_RELEASED 0x80
24859b68
AZ		 1308#define KEY_CODE 0x7f
1309
1310#define KEYCODE_TAB 0x0f
1311#define KEYCODE_ENTER 0x1c
1312#define KEYCODE_F 0x21
1313#define KEYCODE_M 0x32
1314
1315#define KEYCODE_EXTENDED 0xe0
1316#define KEYCODE_UP 0x48
1317#define KEYCODE_DOWN 0x50
1318#define KEYCODE_LEFT 0x4b
1319#define KEYCODE_RIGHT 0x4d
1320
1321static void musicpal_key_event(void *opaque, int keycode)
1322{
1323 qemu_irq irq = opaque;
1324 uint32_t event = 0;
1325 static int kbd_extended;
1326
1327 if (keycode == KEYCODE_EXTENDED) {
1328 kbd_extended = 1;
1329 return;
1330 }
1331
1332 if (kbd_extended)
1333 switch (keycode & KEY_CODE) {
1334 case KEYCODE_UP:
1335 event = MP_GPIO_WHEEL_NAV | MP_GPIO_WHEEL_NAV_INV;
1336 break;
1337
1338 case KEYCODE_DOWN:
1339 event = MP_GPIO_WHEEL_NAV;
1340 break;
1341
1342 case KEYCODE_LEFT:
1343 event = MP_GPIO_WHEEL_VOL | MP_GPIO_WHEEL_VOL_INV;
1344 break;
1345
1346 case KEYCODE_RIGHT:
1347 event = MP_GPIO_WHEEL_VOL;
1348 break;
1349 }
7c6ce4ba 1350 else {
24859b68
AZ		 1351 switch (keycode & KEY_CODE) {
1352 case KEYCODE_F:
1353 event = MP_GPIO_BTN_FAVORITS;
1354 break;
1355
1356 case KEYCODE_TAB:
1357 event = MP_GPIO_BTN_VOLUME;
1358 break;
1359
1360 case KEYCODE_ENTER:
1361 event = MP_GPIO_BTN_NAVIGATION;
1362 break;
1363
1364 case KEYCODE_M:
1365 event = MP_GPIO_BTN_MENU;
1366 break;
1367 }
7c6ce4ba
AZ		 1368 /* Do not repeat already pressed buttons */
1369 if (!(keycode & KEY_RELEASED) && !(gpio_in_state & event))
1370 event = 0;
1371 }
24859b68 1372
7c6ce4ba
AZ		 1373 if (event) {
1374 if (keycode & KEY_RELEASED) {
1375 gpio_in_state |= event;
1376 } else {
1377 gpio_in_state &= ~event;
1378 gpio_isr = event;
1379 qemu_irq_raise(irq);
1380 }
24859b68
AZ		 1381 }
1382
1383 kbd_extended = 0;
1384}
1385
1386static CPUReadMemoryFunc *musicpal_readfn[] = {
1387 musicpal_read,
1388 musicpal_read,
1389 musicpal_read,
1390};
1391
1392static CPUWriteMemoryFunc *musicpal_writefn[] = {
1393 musicpal_write,
1394 musicpal_write,
1395 musicpal_write,
1396};
1397
1398static struct arm_boot_info musicpal_binfo = {
1399 .loader_start = 0x0,
1400 .board_id = 0x20e,
1401};
1402
b0f6edb1 1403static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
24859b68
AZ		 1404 const char *boot_device, DisplayState *ds,
1405 const char *kernel_filename, const char *kernel_cmdline,
1406 const char *initrd_filename, const char *cpu_model)
1407{
1408 CPUState *env;
1409 qemu_irq *pic;
1410 int index;
1411 int iomemtype;
1412 unsigned long flash_size;
1413
1414 if (!cpu_model)
1415 cpu_model = "arm926";
1416
1417 env = cpu_init(cpu_model);
1418 if (!env) {
1419 fprintf(stderr, "Unable to find CPU definition\n");
1420 exit(1);
1421 }
1422 pic = arm_pic_init_cpu(env);
1423
1424 /* For now we use a fixed - the original - RAM size */
1425 cpu_register_physical_memory(0, MP_RAM_DEFAULT_SIZE,
1426 qemu_ram_alloc(MP_RAM_DEFAULT_SIZE));
1427
1428 sram_off = qemu_ram_alloc(MP_SRAM_SIZE);
1429 cpu_register_physical_memory(MP_SRAM_BASE, MP_SRAM_SIZE, sram_off);
1430
1431 /* Catch various stuff not handled by separate subsystems */
1432 iomemtype = cpu_register_io_memory(0, musicpal_readfn,
b0f6edb1 1433 musicpal_writefn, env);
24859b68
AZ		 1434 cpu_register_physical_memory(0x80000000, 0x10000, iomemtype);
1435
1436 pic = mv88w8618_pic_init(MP_PIC_BASE, pic[ARM_PIC_CPU_IRQ]);
1437 mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);
1438
1439 if (serial_hds[0])
b6cd0ea1 1440 serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
24859b68
AZ		 1441 serial_hds[0], 1);
1442 if (serial_hds[1])
b6cd0ea1 1443 serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
24859b68
AZ		 1444 serial_hds[1], 1);
1445
1446 /* Register flash */
1447 index = drive_get_index(IF_PFLASH, 0, 0);
1448 if (index != -1) {
1449 flash_size = bdrv_getlength(drives_table[index].bdrv);
1450 if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1451 flash_size != 32*1024*1024) {
1452 fprintf(stderr, "Invalid flash image size\n");
1453 exit(1);
1454 }
1455
1456 /*
1457 * The original U-Boot accesses the flash at 0xFE000000 instead of
1458 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1459 * image is smaller than 32 MB.
1460 */
1461 pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(flash_size),
1462 drives_table[index].bdrv, 0x10000,
1463 (flash_size + 0xffff) >> 16,
1464 MP_FLASH_SIZE_MAX / flash_size,
1465 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1466 0x5555, 0x2AAA);
1467 }
1468 mv88w8618_flashcfg_init(MP_FLASHCFG_BASE);
1469
1470 musicpal_lcd_init(ds, MP_LCD_BASE);
1471
1472 qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
1473
24859b68
AZ		 1474 mv88w8618_eth_init(&nd_table[0], MP_ETH_BASE, pic[MP_ETH_IRQ]);
1475
1476 mixer_i2c = musicpal_audio_init(MP_AUDIO_BASE, pic[MP_AUDIO_IRQ]);
1477
1478 musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1479 musicpal_binfo.kernel_filename = kernel_filename;
1480 musicpal_binfo.kernel_cmdline = kernel_cmdline;
1481 musicpal_binfo.initrd_filename = initrd_filename;
b0f6edb1 1482 arm_load_kernel(env, &musicpal_binfo);
24859b68
AZ		 1483}
1484
1485QEMUMachine musicpal_machine = {
4b32e168
AL		 1486 .name = "musicpal",
1487 .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1488 .init = musicpal_init,
3d878caa
AZ		 1489 .ram_require = MP_RAM_DEFAULT_SIZE + MP_SRAM_SIZE +
1490 MP_FLASH_SIZE_MAX + RAMSIZE_FIXED,
24859b68 1491};
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