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bf957284 PB |
1 | /* |
2 | * QEMU monitor | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
856dfd8a | 24 | |
0d75590d | 25 | #include "qemu/osdep.h" |
bf957284 PB |
26 | #include "cpu.h" |
27 | #include "monitor/monitor.h" | |
856dfd8a | 28 | #include "qemu/ctype.h" |
bf957284 | 29 | #include "monitor/hmp-target.h" |
275307aa | 30 | #include "monitor/hmp.h" |
bf957284 | 31 | |
a6582090 | 32 | static target_long monitor_get_ccr(const struct MonitorDef *md, int val) |
bf957284 PB |
33 | { |
34 | CPUArchState *env = mon_get_cpu_env(); | |
35 | unsigned int u; | |
36 | int i; | |
37 | ||
38 | u = 0; | |
a6582090 | 39 | for (i = 0; i < 8; i++) { |
bf957284 | 40 | u |= env->crf[i] << (32 - (4 * (i + 1))); |
a6582090 | 41 | } |
bf957284 PB |
42 | |
43 | return u; | |
44 | } | |
45 | ||
a6582090 | 46 | static target_long monitor_get_decr(const struct MonitorDef *md, int val) |
bf957284 PB |
47 | { |
48 | CPUArchState *env = mon_get_cpu_env(); | |
49 | return cpu_ppc_load_decr(env); | |
50 | } | |
51 | ||
a6582090 | 52 | static target_long monitor_get_tbu(const struct MonitorDef *md, int val) |
bf957284 PB |
53 | { |
54 | CPUArchState *env = mon_get_cpu_env(); | |
55 | return cpu_ppc_load_tbu(env); | |
56 | } | |
57 | ||
a6582090 | 58 | static target_long monitor_get_tbl(const struct MonitorDef *md, int val) |
bf957284 PB |
59 | { |
60 | CPUArchState *env = mon_get_cpu_env(); | |
61 | return cpu_ppc_load_tbl(env); | |
62 | } | |
63 | ||
64 | void hmp_info_tlb(Monitor *mon, const QDict *qdict) | |
65 | { | |
66 | CPUArchState *env1 = mon_get_cpu_env(); | |
67 | ||
854e67fe TH |
68 | if (!env1) { |
69 | monitor_printf(mon, "No CPU available\n"); | |
70 | return; | |
71 | } | |
fad866da | 72 | dump_mmu(env1); |
bf957284 PB |
73 | } |
74 | ||
bf957284 | 75 | const MonitorDef monitor_defs[] = { |
bf957284 PB |
76 | { "fpscr", offsetof(CPUPPCState, fpscr) }, |
77 | /* Next instruction pointer */ | |
78 | { "nip|pc", offsetof(CPUPPCState, nip) }, | |
79 | { "lr", offsetof(CPUPPCState, lr) }, | |
80 | { "ctr", offsetof(CPUPPCState, ctr) }, | |
81 | { "decr", 0, &monitor_get_decr, }, | |
0a9516c2 | 82 | { "ccr|cr", 0, &monitor_get_ccr, }, |
bf957284 | 83 | /* Machine state register */ |
0a9516c2 AK |
84 | { "xer", offsetof(CPUPPCState, xer) }, |
85 | { "msr", offsetof(CPUPPCState, msr) }, | |
bf957284 PB |
86 | { "tbu", 0, &monitor_get_tbu, }, |
87 | { "tbl", 0, &monitor_get_tbl, }, | |
bf957284 PB |
88 | { NULL }, |
89 | }; | |
90 | ||
91 | const MonitorDef *target_monitor_defs(void) | |
92 | { | |
93 | return monitor_defs; | |
94 | } | |
0a9516c2 AK |
95 | |
96 | static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum) | |
97 | { | |
98 | int regnum; | |
99 | char *endptr = NULL; | |
100 | ||
101 | if (!*numstr) { | |
102 | return false; | |
103 | } | |
104 | ||
105 | regnum = strtoul(numstr, &endptr, 10); | |
106 | if (*endptr || (regnum >= maxnum)) { | |
107 | return false; | |
108 | } | |
109 | *pregnum = regnum; | |
110 | ||
111 | return true; | |
112 | } | |
113 | ||
114 | int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval) | |
115 | { | |
116 | int i, regnum; | |
117 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
118 | CPUPPCState *env = &cpu->env; | |
119 | ||
120 | /* General purpose registers */ | |
95a5befc | 121 | if ((qemu_tolower(name[0]) == 'r') && |
0a9516c2 AK |
122 | ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), ®num)) { |
123 | *pval = env->gpr[regnum]; | |
124 | return 0; | |
125 | } | |
126 | ||
127 | /* Floating point registers */ | |
95a5befc | 128 | if ((qemu_tolower(name[0]) == 'f') && |
ef96e3ae MCA |
129 | ppc_cpu_get_reg_num(name + 1, 32, ®num)) { |
130 | *pval = *cpu_fpr_ptr(env, regnum); | |
0a9516c2 AK |
131 | return 0; |
132 | } | |
133 | ||
134 | /* Special purpose registers */ | |
135 | for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) { | |
136 | ppc_spr_t *spr = &env->spr_cb[i]; | |
137 | ||
138 | if (spr->name && (strcasecmp(name, spr->name) == 0)) { | |
139 | *pval = env->spr[i]; | |
140 | return 0; | |
141 | } | |
142 | } | |
143 | ||
144 | /* Segment registers */ | |
145 | #if !defined(CONFIG_USER_ONLY) | |
146 | if ((strncasecmp(name, "sr", 2) == 0) && | |
147 | ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), ®num)) { | |
148 | *pval = env->sr[regnum]; | |
149 | return 0; | |
150 | } | |
151 | #endif | |
152 | ||
153 | return -EINVAL; | |
154 | } |