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c4efe1ca AL |
1 | /* |
2 | * libqos PCI bindings | |
3 | * | |
4 | * Copyright IBM, Corp. 2012-2013 | |
5 | * | |
6 | * Authors: | |
7 | * Anthony Liguori <[email protected]> | |
8 | * | |
9 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
10 | * See the COPYING file in the top-level directory. | |
11 | */ | |
12 | ||
13 | #ifndef LIBQOS_PCI_H | |
14 | #define LIBQOS_PCI_H | |
15 | ||
58368113 | 16 | #include "libqtest.h" |
c4efe1ca | 17 | |
a795fc08 DG |
18 | #define QPCI_PIO_LIMIT 0x10000 |
19 | ||
c4efe1ca AL |
20 | #define QPCI_DEVFN(dev, fn) (((dev) << 3) | (fn)) |
21 | ||
22 | typedef struct QPCIDevice QPCIDevice; | |
23 | typedef struct QPCIBus QPCIBus; | |
b4ba67d9 | 24 | typedef struct QPCIBar QPCIBar; |
c4efe1ca | 25 | |
b8cc4d02 | 26 | struct QPCIBus { |
a795fc08 DG |
27 | uint8_t (*pio_readb)(QPCIBus *bus, uint32_t addr); |
28 | uint16_t (*pio_readw)(QPCIBus *bus, uint32_t addr); | |
29 | uint32_t (*pio_readl)(QPCIBus *bus, uint32_t addr); | |
f775f45a | 30 | uint64_t (*pio_readq)(QPCIBus *bus, uint32_t addr); |
a795fc08 | 31 | |
a795fc08 DG |
32 | void (*pio_writeb)(QPCIBus *bus, uint32_t addr, uint8_t value); |
33 | void (*pio_writew)(QPCIBus *bus, uint32_t addr, uint16_t value); | |
34 | void (*pio_writel)(QPCIBus *bus, uint32_t addr, uint32_t value); | |
f775f45a | 35 | void (*pio_writeq)(QPCIBus *bus, uint32_t addr, uint64_t value); |
c4efe1ca | 36 | |
9a84f889 DG |
37 | void (*memread)(QPCIBus *bus, uint32_t addr, void *buf, size_t len); |
38 | void (*memwrite)(QPCIBus *bus, uint32_t addr, const void *buf, size_t len); | |
39 | ||
c4efe1ca AL |
40 | uint8_t (*config_readb)(QPCIBus *bus, int devfn, uint8_t offset); |
41 | uint16_t (*config_readw)(QPCIBus *bus, int devfn, uint8_t offset); | |
42 | uint32_t (*config_readl)(QPCIBus *bus, int devfn, uint8_t offset); | |
43 | ||
44 | void (*config_writeb)(QPCIBus *bus, int devfn, | |
45 | uint8_t offset, uint8_t value); | |
46 | void (*config_writew)(QPCIBus *bus, int devfn, | |
47 | uint8_t offset, uint16_t value); | |
48 | void (*config_writel)(QPCIBus *bus, int devfn, | |
49 | uint8_t offset, uint32_t value); | |
50 | ||
e5d1730d | 51 | QTestState *qts; |
b8cc4d02 DG |
52 | uint16_t pio_alloc_ptr; |
53 | uint64_t mmio_alloc_ptr, mmio_limit; | |
c4efe1ca AL |
54 | }; |
55 | ||
b4ba67d9 DG |
56 | struct QPCIBar { |
57 | uint64_t addr; | |
58 | }; | |
59 | ||
c4efe1ca AL |
60 | struct QPCIDevice |
61 | { | |
62 | QPCIBus *bus; | |
63 | int devfn; | |
58368113 | 64 | bool msix_enabled; |
b4ba67d9 DG |
65 | QPCIBar msix_table_bar, msix_pba_bar; |
66 | uint64_t msix_table_off, msix_pba_off; | |
c4efe1ca AL |
67 | }; |
68 | ||
69 | void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id, | |
70 | void (*func)(QPCIDevice *dev, int devfn, void *data), | |
71 | void *data); | |
72 | QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn); | |
73 | ||
74 | void qpci_device_enable(QPCIDevice *dev); | |
58368113 MM |
75 | uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id); |
76 | void qpci_msix_enable(QPCIDevice *dev); | |
77 | void qpci_msix_disable(QPCIDevice *dev); | |
78 | bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry); | |
79 | bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry); | |
80 | uint16_t qpci_msix_table_size(QPCIDevice *dev); | |
c4efe1ca AL |
81 | |
82 | uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset); | |
83 | uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset); | |
84 | uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset); | |
85 | ||
86 | void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value); | |
87 | void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value); | |
88 | void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value); | |
89 | ||
b4ba67d9 DG |
90 | uint8_t qpci_io_readb(QPCIDevice *dev, QPCIBar token, uint64_t off); |
91 | uint16_t qpci_io_readw(QPCIDevice *dev, QPCIBar token, uint64_t off); | |
92 | uint32_t qpci_io_readl(QPCIDevice *dev, QPCIBar token, uint64_t off); | |
93 | uint64_t qpci_io_readq(QPCIDevice *dev, QPCIBar token, uint64_t off); | |
94 | ||
95 | void qpci_io_writeb(QPCIDevice *dev, QPCIBar token, uint64_t off, | |
96 | uint8_t value); | |
97 | void qpci_io_writew(QPCIDevice *dev, QPCIBar token, uint64_t off, | |
98 | uint16_t value); | |
99 | void qpci_io_writel(QPCIDevice *dev, QPCIBar token, uint64_t off, | |
100 | uint32_t value); | |
101 | void qpci_io_writeq(QPCIDevice *dev, QPCIBar token, uint64_t off, | |
102 | uint64_t value); | |
103 | ||
104 | void qpci_memread(QPCIDevice *bus, QPCIBar token, uint64_t off, | |
105 | void *buf, size_t len); | |
106 | void qpci_memwrite(QPCIDevice *bus, QPCIBar token, uint64_t off, | |
107 | const void *buf, size_t len); | |
108 | QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr); | |
109 | void qpci_iounmap(QPCIDevice *dev, QPCIBar addr); | |
110 | QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr); | |
c4efe1ca | 111 | |
2f8b2767 IM |
112 | void qpci_plug_device_test(const char *driver, const char *id, |
113 | uint8_t slot, const char *opts); | |
114 | void qpci_unplug_acpi_device_test(const char *id, uint8_t slot); | |
c4efe1ca | 115 | #endif |