]> Git Repo - qemu.git/blame - target-s390x/cpu.h
projects / qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
cpu: Turn cpu_has_work() into a CPUClass hook
[qemu.git] / target-s390x / cpu.h
CommitLineData
10ec5117
AG		 1/*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
ccb084d3
CB		 16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
70539e18 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
10ec5117
AG		 21 */
22#ifndef CPU_S390X_H
23#define CPU_S390X_H
45133b74
SW		 24
25#include "config.h"
26#include "qemu-common.h"
10ec5117
AG		 27
28#define TARGET_LONG_BITS 64
29
30#define ELF_MACHINE EM_S390
4ab23a91 31#define ELF_MACHINE_UNAME "S390X"
10ec5117 32
9349b4f9 33#define CPUArchState struct CPUS390XState
10ec5117 34
022c62cb 35#include "exec/cpu-defs.h"
bcec36ea
AG		 36#define TARGET_PAGE_BITS 12
37
5b23fd03 38#define TARGET_PHYS_ADDR_SPACE_BITS 64
bcec36ea
AG		 39#define TARGET_VIRT_ADDR_SPACE_BITS 64
40
022c62cb 41#include "exec/cpu-all.h"
10ec5117 42
6b4c305c 43#include "fpu/softfloat.h"
10ec5117 44
bcec36ea 45#define NB_MMU_MODES 3
10ec5117 46
bcec36ea
AG		 47#define MMU_MODE0_SUFFIX _primary
48#define MMU_MODE1_SUFFIX _secondary
49#define MMU_MODE2_SUFFIX _home
50
51#define MMU_USER_IDX 1
52
53#define MAX_EXT_QUEUE 16
5d69c547
CH		 54#define MAX_IO_QUEUE 16
55#define MAX_MCHK_QUEUE 16
56
57#define PSW_MCHK_MASK 0x0004000000000000
58#define PSW_IO_MASK 0x0200000000000000
bcec36ea
AG		 59
60typedef struct PSW {
61 uint64_t mask;
62 uint64_t addr;
63} PSW;
64
65typedef struct ExtQueue {
66 uint32_t code;
67 uint32_t param;
68 uint32_t param64;
69} ExtQueue;
10ec5117 70
5d69c547
CH		 71typedef struct IOIntQueue {
72 uint16_t id;
73 uint16_t nr;
74 uint32_t parm;
75 uint32_t word;
76} IOIntQueue;
77
78typedef struct MchkQueue {
79 uint16_t type;
80} MchkQueue;
81
10ec5117 82typedef struct CPUS390XState {
1ac5889f
RH		 83 uint64_t regs[16]; /* GP registers */
84 CPU_DoubleU fregs[16]; /* FP registers */
85 uint32_t aregs[16]; /* access registers */
10ec5117 86
1ac5889f
RH		 87 uint32_t fpc; /* floating-point control register */
88 uint32_t cc_op;
10ec5117 89
10ec5117
AG		 90 float_status fpu_status; /* passed to softfloat lib */
91
1ac5889f
RH		 92 /* The low part of a 128-bit return, or remainder of a divide. */
93 uint64_t retxl;
94
bcec36ea 95 PSW psw;
10ec5117 96
bcec36ea
AG		 97 uint64_t cc_src;
98 uint64_t cc_dst;
99 uint64_t cc_vr;
10ec5117
AG		 100
101 uint64_t __excp_addr;
bcec36ea
AG		 102 uint64_t psa;
103
104 uint32_t int_pgm_code;
d5a103cd 105 uint32_t int_pgm_ilen;
bcec36ea
AG		 106
107 uint32_t int_svc_code;
d5a103cd 108 uint32_t int_svc_ilen;
bcec36ea
AG		 109
110 uint64_t cregs[16]; /* control registers */
111
bcec36ea 112 ExtQueue ext_queue[MAX_EXT_QUEUE];
5d69c547
CH		 113 IOIntQueue io_queue[MAX_IO_QUEUE][8];
114 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
bcec36ea 115
5d69c547 116 int pending_int;
4e836781 117 int ext_index;
5d69c547
CH		 118 int io_index[8];
119 int mchk_index;
120
121 uint64_t ckc;
122 uint64_t cputm;
123 uint32_t todpr;
4e836781 124
819bd309
DD		 125 uint64_t pfault_token;
126 uint64_t pfault_compare;
127 uint64_t pfault_select;
128
4e836781
AG		 129 CPU_COMMON
130
bcec36ea
AG		 131 /* reset does memset(0) up to here */
132
bcec36ea
AG		 133 int cpu_num;
134 uint8_t *storage_keys;
135
136 uint64_t tod_offset;
137 uint64_t tod_basetime;
138 QEMUTimer *tod_timer;
139
140 QEMUTimer *cpu_timer;
10ec5117
AG		 141} CPUS390XState;
142
564b863d 143#include "cpu-qom.h"
3d0a615f 144#include <sysemu/kvm.h>
564b863d 145
7b18aad5
CH		 146/* distinguish between 24 bit and 31 bit addressing */
147#define HIGH_ORDER_BIT 0x80000000
148
bcec36ea
AG		 149/* Interrupt Codes */
150/* Program Interrupts */
151#define PGM_OPERATION 0x0001
152#define PGM_PRIVILEGED 0x0002
153#define PGM_EXECUTE 0x0003
154#define PGM_PROTECTION 0x0004
155#define PGM_ADDRESSING 0x0005
156#define PGM_SPECIFICATION 0x0006
157#define PGM_DATA 0x0007
158#define PGM_FIXPT_OVERFLOW 0x0008
159#define PGM_FIXPT_DIVIDE 0x0009
160#define PGM_DEC_OVERFLOW 0x000a
161#define PGM_DEC_DIVIDE 0x000b
162#define PGM_HFP_EXP_OVERFLOW 0x000c
163#define PGM_HFP_EXP_UNDERFLOW 0x000d
164#define PGM_HFP_SIGNIFICANCE 0x000e
165#define PGM_HFP_DIVIDE 0x000f
166#define PGM_SEGMENT_TRANS 0x0010
167#define PGM_PAGE_TRANS 0x0011
168#define PGM_TRANS_SPEC 0x0012
169#define PGM_SPECIAL_OP 0x0013
170#define PGM_OPERAND 0x0015
171#define PGM_TRACE_TABLE 0x0016
172#define PGM_SPACE_SWITCH 0x001c
173#define PGM_HFP_SQRT 0x001d
174#define PGM_PC_TRANS_SPEC 0x001f
175#define PGM_AFX_TRANS 0x0020
176#define PGM_ASX_TRANS 0x0021
177#define PGM_LX_TRANS 0x0022
178#define PGM_EX_TRANS 0x0023
179#define PGM_PRIM_AUTH 0x0024
180#define PGM_SEC_AUTH 0x0025
181#define PGM_ALET_SPEC 0x0028
182#define PGM_ALEN_SPEC 0x0029
183#define PGM_ALE_SEQ 0x002a
184#define PGM_ASTE_VALID 0x002b
185#define PGM_ASTE_SEQ 0x002c
186#define PGM_EXT_AUTH 0x002d
187#define PGM_STACK_FULL 0x0030
188#define PGM_STACK_EMPTY 0x0031
189#define PGM_STACK_SPEC 0x0032
190#define PGM_STACK_TYPE 0x0033
191#define PGM_STACK_OP 0x0034
192#define PGM_ASCE_TYPE 0x0038
193#define PGM_REG_FIRST_TRANS 0x0039
194#define PGM_REG_SEC_TRANS 0x003a
195#define PGM_REG_THIRD_TRANS 0x003b
196#define PGM_MONITOR 0x0040
197#define PGM_PER 0x0080
198#define PGM_CRYPTO 0x0119
199
200/* External Interrupts */
201#define EXT_INTERRUPT_KEY 0x0040
202#define EXT_CLOCK_COMP 0x1004
203#define EXT_CPU_TIMER 0x1005
204#define EXT_MALFUNCTION 0x1200
205#define EXT_EMERGENCY 0x1201
206#define EXT_EXTERNAL_CALL 0x1202
207#define EXT_ETR 0x1406
208#define EXT_SERVICE 0x2401
209#define EXT_VIRTIO 0x2603
210
211/* PSW defines */
212#undef PSW_MASK_PER
213#undef PSW_MASK_DAT
214#undef PSW_MASK_IO
215#undef PSW_MASK_EXT
216#undef PSW_MASK_KEY
217#undef PSW_SHIFT_KEY
218#undef PSW_MASK_MCHECK
219#undef PSW_MASK_WAIT
220#undef PSW_MASK_PSTATE
221#undef PSW_MASK_ASC
222#undef PSW_MASK_CC
223#undef PSW_MASK_PM
224#undef PSW_MASK_64
29c6157c
CB		 225#undef PSW_MASK_32
226#undef PSW_MASK_ESA_ADDR
bcec36ea
AG		 227
228#define PSW_MASK_PER 0x4000000000000000ULL
229#define PSW_MASK_DAT 0x0400000000000000ULL
230#define PSW_MASK_IO 0x0200000000000000ULL
231#define PSW_MASK_EXT 0x0100000000000000ULL
232#define PSW_MASK_KEY 0x00F0000000000000ULL
233#define PSW_SHIFT_KEY 56
234#define PSW_MASK_MCHECK 0x0004000000000000ULL
235#define PSW_MASK_WAIT 0x0002000000000000ULL
236#define PSW_MASK_PSTATE 0x0001000000000000ULL
237#define PSW_MASK_ASC 0x0000C00000000000ULL
238#define PSW_MASK_CC 0x0000300000000000ULL
239#define PSW_MASK_PM 0x00000F0000000000ULL
240#define PSW_MASK_64 0x0000000100000000ULL
241#define PSW_MASK_32 0x0000000080000000ULL
29c6157c 242#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
bcec36ea
AG		 243
244#undef PSW_ASC_PRIMARY
245#undef PSW_ASC_ACCREG
246#undef PSW_ASC_SECONDARY
247#undef PSW_ASC_HOME
248
249#define PSW_ASC_PRIMARY 0x0000000000000000ULL
250#define PSW_ASC_ACCREG 0x0000400000000000ULL
251#define PSW_ASC_SECONDARY 0x0000800000000000ULL
252#define PSW_ASC_HOME 0x0000C00000000000ULL
253
254/* tb flags */
255
256#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
257#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
258#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
259#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
260#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
261#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
262#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
263#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
264#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
265#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
266#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
267#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
268#define FLAG_MASK_32 0x00001000
269
a4e3ad19 270static inline int cpu_mmu_index (CPUS390XState *env)
10c339a0 271{
bcec36ea
AG		 272 if (env->psw.mask & PSW_MASK_PSTATE) {
273 return 1;
274 }
275
10c339a0
AG		 276 return 0;
277}
278
a4e3ad19 279static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
bcec36ea
AG		 280 target_ulong *cs_base, int *flags)
281{
282 *pc = env->psw.addr;
283 *cs_base = 0;
284 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
285 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
286}
287
d5a103cd
RH		 288/* While the PoO talks about ILC (a number between 1-3) what is actually
289 stored in LowCore is shifted left one bit (an even between 2-6). As
290 this is the actual length of the insn and therefore more useful, that
291 is what we want to pass around and manipulate. To make sure that we
292 have applied this distinction universally, rename the "ILC" to "ILEN". */
293static inline int get_ilen(uint8_t opc)
bcec36ea
AG		 294{
295 switch (opc >> 6) {
296 case 0:
d5a103cd 297 return 2;
bcec36ea
AG		 298 case 1:
299 case 2:
d5a103cd
RH		 300 return 4;
301 default:
302 return 6;
bcec36ea 303 }
bcec36ea
AG		 304}
305
d5a103cd
RH		 306#ifndef CONFIG_USER_ONLY
307/* In several cases of runtime exceptions, we havn't recorded the true
308 instruction length. Use these codes when raising exceptions in order
309 to re-compute the length by examining the insn in memory. */
310#define ILEN_LATER 0x20
311#define ILEN_LATER_INC 0x21
312#endif
bcec36ea 313
564b863d 314S390CPU *cpu_s390x_init(const char *cpu_model);
bcec36ea 315void s390x_translate_init(void);
10ec5117 316int cpu_s390x_exec(CPUS390XState *s);
10ec5117
AG		 317
318/* you can call this signal handler from your SIGBUS and SIGSEGV
319 signal handlers to inform the virtual CPU of exceptions. non zero
320 is returned if the signal was handled by the virtual CPU. */
321int cpu_s390x_signal_handler(int host_signum, void *pinfo,
322 void *puc);
323int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
97b348e7 324 int mmu_idx);
10ec5117
AG		 325#define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
326
db1c8f53 327#include "ioinst.h"
52705890 328
10c339a0 329#ifndef CONFIG_USER_ONLY
38322ed6
CH		 330void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
331 int is_write);
332void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
333 int is_write);
7b18aad5
CH		 334static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
335{
336 hwaddr addr = 0;
337 uint8_t reg;
338
339 reg = ipb >> 28;
340 if (reg > 0) {
341 addr = env->regs[reg];
342 }
343 addr += (ipb >> 16) & 0xfff;
344
345 return addr;
346}
347
638129ff
CH		 348/* Base/displacement are at the same locations. */
349#define decode_basedisp_rs decode_basedisp_s
350
8f22e0df
AF		 351void s390x_tod_timer(void *opaque);
352void s390x_cpu_timer(void *opaque);
353
28e942f8 354int s390_virtio_hypercall(CPUS390XState *env);
bcec36ea 355
1f206266 356#ifdef CONFIG_KVM
1bc22652
AF		 357void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
358void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
359void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
bcec36ea 360 uint64_t parm64, int vm);
1f206266 361#else
1bc22652 362static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
1f206266
AG		 363{
364}
365
1bc22652 366static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
1f206266
AG		 367 uint64_t token)
368{
369}
370
1bc22652 371static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
1f206266
AG		 372 uint32_t parm, uint64_t parm64,
373 int vm)
374{
375}
376#endif
45fa769b 377S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
49e15878
AF		 378void s390_add_running_cpu(S390CPU *cpu);
379unsigned s390_del_running_cpu(S390CPU *cpu);
bcec36ea 380
000a1a38
CB		 381/* service interrupts are floating therefore we must not pass an cpustate */
382void s390_sclp_extint(uint32_t parm);
383
d1ff903c 384/* from s390-virtio-bus */
a8170e5e 385extern const hwaddr virtio_size;
d1ff903c 386
ef81522b 387#else
49e15878 388static inline void s390_add_running_cpu(S390CPU *cpu)
ef81522b
AG		 389{
390}
391
49e15878 392static inline unsigned s390_del_running_cpu(S390CPU *cpu)
ef81522b
AG		 393{
394 return 0;
395}
10c339a0 396#endif
bcec36ea
AG		 397void cpu_lock(void);
398void cpu_unlock(void);
10c339a0 399
7b18aad5
CH		 400typedef struct SubchDev SubchDev;
401
df1fe5bb 402#ifndef CONFIG_USER_ONLY
4e872a3f 403extern void io_subsystem_reset(void);
df1fe5bb
CH		 404SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
405 uint16_t schid);
406bool css_subch_visible(SubchDev *sch);
407void css_conditional_io_interrupt(SubchDev *sch);
408int css_do_stsch(SubchDev *sch, SCHIB *schib);
38dd7cc7 409bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
df1fe5bb
CH		 410int css_do_msch(SubchDev *sch, SCHIB *schib);
411int css_do_xsch(SubchDev *sch);
412int css_do_csch(SubchDev *sch);
413int css_do_hsch(SubchDev *sch);
414int css_do_ssch(SubchDev *sch, ORB *orb);
415int css_do_tsch(SubchDev *sch, IRB *irb);
416int css_do_stcrw(CRW *crw);
50c8d9bf 417int css_do_tpi(IOIntCode *int_code, int lowcore);
df1fe5bb
CH		 418int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
419 int rfmt, void *buf);
420void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
421int css_enable_mcsse(void);
422int css_enable_mss(void);
423int css_do_rsch(SubchDev *sch);
424int css_do_rchp(uint8_t cssid, uint8_t chpid);
425bool css_present(uint8_t cssid);
426#else
7b18aad5
CH		 427static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
428 uint16_t schid)
429{
430 return NULL;
431}
432static inline bool css_subch_visible(SubchDev *sch)
433{
434 return false;
435}
436static inline void css_conditional_io_interrupt(SubchDev *sch)
437{
438}
439static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
440{
441 return -ENODEV;
442}
443static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
444{
445 return true;
446}
447static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
448{
449 return -ENODEV;
450}
451static inline int css_do_xsch(SubchDev *sch)
452{
453 return -ENODEV;
454}
455static inline int css_do_csch(SubchDev *sch)
456{
457 return -ENODEV;
458}
459static inline int css_do_hsch(SubchDev *sch)
460{
461 return -ENODEV;
462}
463static inline int css_do_ssch(SubchDev *sch, ORB *orb)
464{
465 return -ENODEV;
466}
467static inline int css_do_tsch(SubchDev *sch, IRB *irb)
468{
469 return -ENODEV;
470}
471static inline int css_do_stcrw(CRW *crw)
472{
473 return 1;
474}
50c8d9bf 475static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
7b18aad5
CH		 476{
477 return 0;
478}
479static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
480 int rfmt, uint8_t l_chpid, void *buf)
481{
482 return 0;
483}
484static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
485{
486}
487static inline int css_enable_mss(void)
488{
489 return -EINVAL;
490}
491static inline int css_enable_mcsse(void)
492{
493 return -EINVAL;
494}
495static inline int css_do_rsch(SubchDev *sch)
496{
497 return -ENODEV;
498}
499static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
500{
501 return -ENODEV;
502}
503static inline bool css_present(uint8_t cssid)
504{
505 return false;
506}
df1fe5bb 507#endif
7b18aad5 508
564b863d 509#define cpu_init(model) (&cpu_s390x_init(model)->env)
10ec5117
AG		 510#define cpu_exec cpu_s390x_exec
511#define cpu_gen_code cpu_s390x_gen_code
bcec36ea 512#define cpu_signal_handler cpu_s390x_signal_handler
10ec5117 513
904e5fd5
VM		 514void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
515#define cpu_list s390_cpu_list
516
022c62cb 517#include "exec/exec-all.h"
bcec36ea 518
bcec36ea
AG		 519#define EXCP_EXT 1 /* external interrupt */
520#define EXCP_SVC 2 /* supervisor call (syscall) */
521#define EXCP_PGM 3 /* program interruption */
5d69c547
CH		 522#define EXCP_IO 7 /* I/O interrupt */
523#define EXCP_MCHK 8 /* machine check */
bcec36ea 524
bcec36ea
AG		 525#define INTERRUPT_EXT (1 << 0)
526#define INTERRUPT_TOD (1 << 1)
527#define INTERRUPT_CPUTIMER (1 << 2)
5d69c547
CH		 528#define INTERRUPT_IO (1 << 3)
529#define INTERRUPT_MCHK (1 << 4)
10c339a0
AG		 530
531/* Program Status Word. */
532#define S390_PSWM_REGNUM 0
533#define S390_PSWA_REGNUM 1
534/* General Purpose Registers. */
535#define S390_R0_REGNUM 2
536#define S390_R1_REGNUM 3
537#define S390_R2_REGNUM 4
538#define S390_R3_REGNUM 5
539#define S390_R4_REGNUM 6
540#define S390_R5_REGNUM 7
541#define S390_R6_REGNUM 8
542#define S390_R7_REGNUM 9
543#define S390_R8_REGNUM 10
544#define S390_R9_REGNUM 11
545#define S390_R10_REGNUM 12
546#define S390_R11_REGNUM 13
547#define S390_R12_REGNUM 14
548#define S390_R13_REGNUM 15
549#define S390_R14_REGNUM 16
550#define S390_R15_REGNUM 17
551/* Access Registers. */
552#define S390_A0_REGNUM 18
553#define S390_A1_REGNUM 19
554#define S390_A2_REGNUM 20
555#define S390_A3_REGNUM 21
556#define S390_A4_REGNUM 22
557#define S390_A5_REGNUM 23
558#define S390_A6_REGNUM 24
559#define S390_A7_REGNUM 25
560#define S390_A8_REGNUM 26
561#define S390_A9_REGNUM 27
562#define S390_A10_REGNUM 28
563#define S390_A11_REGNUM 29
564#define S390_A12_REGNUM 30
565#define S390_A13_REGNUM 31
566#define S390_A14_REGNUM 32
567#define S390_A15_REGNUM 33
568/* Floating Point Control Word. */
569#define S390_FPC_REGNUM 34
570/* Floating Point Registers. */
571#define S390_F0_REGNUM 35
572#define S390_F1_REGNUM 36
573#define S390_F2_REGNUM 37
574#define S390_F3_REGNUM 38
575#define S390_F4_REGNUM 39
576#define S390_F5_REGNUM 40
577#define S390_F6_REGNUM 41
578#define S390_F7_REGNUM 42
579#define S390_F8_REGNUM 43
580#define S390_F9_REGNUM 44
581#define S390_F10_REGNUM 45
582#define S390_F11_REGNUM 46
583#define S390_F12_REGNUM 47
584#define S390_F13_REGNUM 48
585#define S390_F14_REGNUM 49
586#define S390_F15_REGNUM 50
587/* Total. */
588#define S390_NUM_REGS 51
589
bcec36ea
AG		 590/* CC optimization */
591
592enum cc_op {
593 CC_OP_CONST0 = 0, /* CC is 0 */
594 CC_OP_CONST1, /* CC is 1 */
595 CC_OP_CONST2, /* CC is 2 */
596 CC_OP_CONST3, /* CC is 3 */
597
598 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
599 CC_OP_STATIC, /* CC value is env->cc_op */
600
601 CC_OP_NZ, /* env->cc_dst != 0 */
602 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
603 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
604 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
605 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
606 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
607 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
608
609 CC_OP_ADD_64, /* overflow on add (64bit) */
610 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
4e4bb438 611 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
e7d81004
SW		 612 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
613 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
4e4bb438 614 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
bcec36ea
AG		 615 CC_OP_ABS_64, /* sign eval on abs (64bit) */
616 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
617
618 CC_OP_ADD_32, /* overflow on add (32bit) */
619 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
4e4bb438 620 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
e7d81004
SW		 621 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
622 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
4e4bb438 623 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
bcec36ea
AG		 624 CC_OP_ABS_32, /* sign eval on abs (64bit) */
625 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
626
627 CC_OP_COMP_32, /* complement */
628 CC_OP_COMP_64, /* complement */
629
630 CC_OP_TM_32, /* test under mask (32bit) */
631 CC_OP_TM_64, /* test under mask (64bit) */
632
bcec36ea
AG		 633 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
634 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
587626f8 635 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
bcec36ea
AG		 636
637 CC_OP_ICM, /* insert characters under mask */
cbe24bfa
RH		 638 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
639 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
102bf2c6 640 CC_OP_FLOGR, /* find leftmost one */
bcec36ea
AG		 641 CC_OP_MAX
642};
643
644static const char *cc_names[] = {
645 [CC_OP_CONST0] = "CC_OP_CONST0",
646 [CC_OP_CONST1] = "CC_OP_CONST1",
647 [CC_OP_CONST2] = "CC_OP_CONST2",
648 [CC_OP_CONST3] = "CC_OP_CONST3",
649 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
650 [CC_OP_STATIC] = "CC_OP_STATIC",
651 [CC_OP_NZ] = "CC_OP_NZ",
652 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
653 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
654 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
655 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
656 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
657 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
658 [CC_OP_ADD_64] = "CC_OP_ADD_64",
659 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
4e4bb438 660 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
bcec36ea
AG		 661 [CC_OP_SUB_64] = "CC_OP_SUB_64",
662 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
4e4bb438 663 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
bcec36ea
AG		 664 [CC_OP_ABS_64] = "CC_OP_ABS_64",
665 [CC_OP_NABS_64] = "CC_OP_NABS_64",
666 [CC_OP_ADD_32] = "CC_OP_ADD_32",
667 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
4e4bb438 668 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
bcec36ea
AG		 669 [CC_OP_SUB_32] = "CC_OP_SUB_32",
670 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
4e4bb438 671 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
bcec36ea
AG		 672 [CC_OP_ABS_32] = "CC_OP_ABS_32",
673 [CC_OP_NABS_32] = "CC_OP_NABS_32",
674 [CC_OP_COMP_32] = "CC_OP_COMP_32",
675 [CC_OP_COMP_64] = "CC_OP_COMP_64",
676 [CC_OP_TM_32] = "CC_OP_TM_32",
677 [CC_OP_TM_64] = "CC_OP_TM_64",
bcec36ea
AG		 678 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
679 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
587626f8 680 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
bcec36ea 681 [CC_OP_ICM] = "CC_OP_ICM",
cbe24bfa
RH		 682 [CC_OP_SLA_32] = "CC_OP_SLA_32",
683 [CC_OP_SLA_64] = "CC_OP_SLA_64",
102bf2c6 684 [CC_OP_FLOGR] = "CC_OP_FLOGR",
bcec36ea
AG		 685};
686
687static inline const char *cc_name(int cc_op)
688{
689 return cc_names[cc_op];
690}
691
3d0a615f
TH		 692static inline void setcc(S390CPU *cpu, uint64_t cc)
693{
694 CPUS390XState *env = &cpu->env;
695
696 env->psw.mask &= ~(3ull << 44);
697 env->psw.mask |= (cc & 3) << 44;
698}
699
bcec36ea
AG		 700typedef struct LowCore
701{
702 /* prefix area: defined by architecture */
703 uint32_t ccw1[2]; /* 0x000 */
704 uint32_t ccw2[4]; /* 0x008 */
705 uint8_t pad1[0x80-0x18]; /* 0x018 */
706 uint32_t ext_params; /* 0x080 */
707 uint16_t cpu_addr; /* 0x084 */
708 uint16_t ext_int_code; /* 0x086 */
d5a103cd 709 uint16_t svc_ilen; /* 0x088 */
bcec36ea 710 uint16_t svc_code; /* 0x08a */
d5a103cd 711 uint16_t pgm_ilen; /* 0x08c */
bcec36ea
AG		 712 uint16_t pgm_code; /* 0x08e */
713 uint32_t data_exc_code; /* 0x090 */
714 uint16_t mon_class_num; /* 0x094 */
715 uint16_t per_perc_atmid; /* 0x096 */
716 uint64_t per_address; /* 0x098 */
717 uint8_t exc_access_id; /* 0x0a0 */
718 uint8_t per_access_id; /* 0x0a1 */
719 uint8_t op_access_id; /* 0x0a2 */
720 uint8_t ar_access_id; /* 0x0a3 */
721 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
722 uint64_t trans_exc_code; /* 0x0a8 */
723 uint64_t monitor_code; /* 0x0b0 */
724 uint16_t subchannel_id; /* 0x0b8 */
725 uint16_t subchannel_nr; /* 0x0ba */
726 uint32_t io_int_parm; /* 0x0bc */
727 uint32_t io_int_word; /* 0x0c0 */
728 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
729 uint32_t stfl_fac_list; /* 0x0c8 */
730 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
731 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
732 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
733 uint32_t external_damage_code; /* 0x0f4 */
734 uint64_t failing_storage_address; /* 0x0f8 */
735 uint8_t pad6[0x120-0x100]; /* 0x100 */
736 PSW restart_old_psw; /* 0x120 */
737 PSW external_old_psw; /* 0x130 */
738 PSW svc_old_psw; /* 0x140 */
739 PSW program_old_psw; /* 0x150 */
740 PSW mcck_old_psw; /* 0x160 */
741 PSW io_old_psw; /* 0x170 */
742 uint8_t pad7[0x1a0-0x180]; /* 0x180 */
743 PSW restart_psw; /* 0x1a0 */
744 PSW external_new_psw; /* 0x1b0 */
745 PSW svc_new_psw; /* 0x1c0 */
746 PSW program_new_psw; /* 0x1d0 */
747 PSW mcck_new_psw; /* 0x1e0 */
748 PSW io_new_psw; /* 0x1f0 */
749 PSW return_psw; /* 0x200 */
750 uint8_t irb[64]; /* 0x210 */
751 uint64_t sync_enter_timer; /* 0x250 */
752 uint64_t async_enter_timer; /* 0x258 */
753 uint64_t exit_timer; /* 0x260 */
754 uint64_t last_update_timer; /* 0x268 */
755 uint64_t user_timer; /* 0x270 */
756 uint64_t system_timer; /* 0x278 */
757 uint64_t last_update_clock; /* 0x280 */
758 uint64_t steal_clock; /* 0x288 */
759 PSW return_mcck_psw; /* 0x290 */
760 uint8_t pad8[0xc00-0x2a0]; /* 0x2a0 */
761 /* System info area */
762 uint64_t save_area[16]; /* 0xc00 */
763 uint8_t pad9[0xd40-0xc80]; /* 0xc80 */
764 uint64_t kernel_stack; /* 0xd40 */
765 uint64_t thread_info; /* 0xd48 */
766 uint64_t async_stack; /* 0xd50 */
767 uint64_t kernel_asce; /* 0xd58 */
768 uint64_t user_asce; /* 0xd60 */
769 uint64_t panic_stack; /* 0xd68 */
770 uint64_t user_exec_asce; /* 0xd70 */
771 uint8_t pad10[0xdc0-0xd78]; /* 0xd78 */
772
773 /* SMP info area: defined by DJB */
774 uint64_t clock_comparator; /* 0xdc0 */
775 uint64_t ext_call_fast; /* 0xdc8 */
776 uint64_t percpu_offset; /* 0xdd0 */
777 uint64_t current_task; /* 0xdd8 */
778 uint32_t softirq_pending; /* 0xde0 */
779 uint32_t pad_0x0de4; /* 0xde4 */
780 uint64_t int_clock; /* 0xde8 */
781 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
782
783 /* 0xe00 is used as indicator for dump tools */
784 /* whether the kernel died with panic() or not */
785 uint32_t panic_magic; /* 0xe00 */
786
787 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
788
789 /* 64 bit extparam used for pfault, diag 250 etc */
790 uint64_t ext_params2; /* 0x11B8 */
791
792 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
793
794 /* System info area */
795
796 uint64_t floating_pt_save_area[16]; /* 0x1200 */
797 uint64_t gpregs_save_area[16]; /* 0x1280 */
798 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
799 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
800 uint32_t prefixreg_save_area; /* 0x1318 */
801 uint32_t fpt_creg_save_area; /* 0x131c */
802 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
803 uint32_t tod_progreg_save_area; /* 0x1324 */
804 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
805 uint32_t clock_comp_save_area[2]; /* 0x1330 */
806 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
807 uint32_t access_regs_save_area[16]; /* 0x1340 */
808 uint64_t cregs_save_area[16]; /* 0x1380 */
809
810 /* align to the top of the prefix area */
811
812 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
541dc0d4 813} QEMU_PACKED LowCore;
bcec36ea
AG		 814
815/* STSI */
816#define STSI_LEVEL_MASK 0x00000000f0000000ULL
817#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
818#define STSI_LEVEL_1 0x0000000010000000ULL
819#define STSI_LEVEL_2 0x0000000020000000ULL
820#define STSI_LEVEL_3 0x0000000030000000ULL
821#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
822#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
823#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
824#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
825
826/* Basic Machine Configuration */
827struct sysib_111 {
828 uint32_t res1[8];
829 uint8_t manuf[16];
830 uint8_t type[4];
831 uint8_t res2[12];
832 uint8_t model[16];
833 uint8_t sequence[16];
834 uint8_t plant[4];
835 uint8_t res3[156];
836};
837
838/* Basic Machine CPU */
839struct sysib_121 {
840 uint32_t res1[80];
841 uint8_t sequence[16];
842 uint8_t plant[4];
843 uint8_t res2[2];
844 uint16_t cpu_addr;
845 uint8_t res3[152];
846};
847
848/* Basic Machine CPUs */
849struct sysib_122 {
850 uint8_t res1[32];
851 uint32_t capability;
852 uint16_t total_cpus;
853 uint16_t active_cpus;
854 uint16_t standby_cpus;
855 uint16_t reserved_cpus;
856 uint16_t adjustments[2026];
857};
858
859/* LPAR CPU */
860struct sysib_221 {
861 uint32_t res1[80];
862 uint8_t sequence[16];
863 uint8_t plant[4];
864 uint16_t cpu_id;
865 uint16_t cpu_addr;
866 uint8_t res3[152];
867};
868
869/* LPAR CPUs */
870struct sysib_222 {
871 uint32_t res1[32];
872 uint16_t lpar_num;
873 uint8_t res2;
874 uint8_t lcpuc;
875 uint16_t total_cpus;
876 uint16_t conf_cpus;
877 uint16_t standby_cpus;
878 uint16_t reserved_cpus;
879 uint8_t name[8];
880 uint32_t caf;
881 uint8_t res3[16];
882 uint16_t dedicated_cpus;
883 uint16_t shared_cpus;
884 uint8_t res4[180];
885};
886
887/* VM CPUs */
888struct sysib_322 {
889 uint8_t res1[31];
890 uint8_t count;
891 struct {
892 uint8_t res2[4];
893 uint16_t total_cpus;
894 uint16_t conf_cpus;
895 uint16_t standby_cpus;
896 uint16_t reserved_cpus;
897 uint8_t name[8];
898 uint32_t caf;
899 uint8_t cpi[16];
900 uint8_t res3[24];
901 } vm[8];
902 uint8_t res4[3552];
903};
904
905/* MMU defines */
906#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
907#define _ASCE_SUBSPACE 0x200 /* subspace group control */
908#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
909#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
910#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
911#define _ASCE_REAL_SPACE 0x20 /* real space control */
912#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
913#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
914#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
915#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
916#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
917#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
918
919#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
920#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
921#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
922#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
923#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
924#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
925#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
926
927#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
928#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
929#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
930
931#define _PAGE_RO 0x200 /* HW read-only bit */
932#define _PAGE_INVALID 0x400 /* HW invalid bit */
933
b9959138
AG		 934#define SK_C (0x1 << 1)
935#define SK_R (0x1 << 2)
936#define SK_F (0x1 << 3)
937#define SK_ACC_MASK (0xf << 4)
bcec36ea 938
bcec36ea
AG		 939#define SIGP_SENSE 0x01
940#define SIGP_EXTERNAL_CALL 0x02
941#define SIGP_EMERGENCY 0x03
942#define SIGP_START 0x04
943#define SIGP_STOP 0x05
944#define SIGP_RESTART 0x06
945#define SIGP_STOP_STORE_STATUS 0x09
946#define SIGP_INITIAL_CPU_RESET 0x0b
947#define SIGP_CPU_RESET 0x0c
948#define SIGP_SET_PREFIX 0x0d
949#define SIGP_STORE_STATUS_ADDR 0x0e
950#define SIGP_SET_ARCH 0x12
951
952/* cpu status bits */
953#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
954#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
955#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
956#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
957#define SIGP_STAT_STOPPED 0x00000040UL
958#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
959#define SIGP_STAT_CHECK_STOP 0x00000010UL
960#define SIGP_STAT_INOPERATIVE 0x00000004UL
961#define SIGP_STAT_INVALID_ORDER 0x00000002UL
962#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
963
a4e3ad19
AF		 964void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
965int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
bcec36ea 966 target_ulong *raddr, int *flags);
6e252802 967int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
a4e3ad19 968uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
bcec36ea
AG		 969 uint64_t vr);
970
971#define TARGET_HAS_ICE 1
972
973/* The value of the TOD clock for 1.1.1970. */
974#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
975
976/* Converts ns to s390's clock format */
977static inline uint64_t time2tod(uint64_t ns) {
978 return (ns << 9) / 125;
979}
980
f9466733 981static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
bcec36ea
AG		 982 uint64_t param64)
983{
f9466733
AF		 984 CPUS390XState *env = &cpu->env;
985
bcec36ea
AG		 986 if (env->ext_index == MAX_EXT_QUEUE - 1) {
987 /* ugh - can't queue anymore. Let's drop. */
988 return;
989 }
990
991 env->ext_index++;
992 assert(env->ext_index < MAX_EXT_QUEUE);
993
994 env->ext_queue[env->ext_index].code = code;
995 env->ext_queue[env->ext_index].param = param;
996 env->ext_queue[env->ext_index].param64 = param64;
997
998 env->pending_int |= INTERRUPT_EXT;
c3affe56 999 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
bcec36ea 1000}
10c339a0 1001
f9466733 1002static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
5d69c547
CH		 1003 uint16_t subchannel_number,
1004 uint32_t io_int_parm, uint32_t io_int_word)
1005{
f9466733 1006 CPUS390XState *env = &cpu->env;
91b0a8f3 1007 int isc = IO_INT_WORD_ISC(io_int_word);
5d69c547
CH		 1008
1009 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1010 /* ugh - can't queue anymore. Let's drop. */
1011 return;
1012 }
1013
1014 env->io_index[isc]++;
1015 assert(env->io_index[isc] < MAX_IO_QUEUE);
1016
1017 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1018 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1019 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1020 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1021
1022 env->pending_int |= INTERRUPT_IO;
c3affe56 1023 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1024}
1025
f9466733 1026static inline void cpu_inject_crw_mchk(S390CPU *cpu)
5d69c547 1027{
f9466733
AF		 1028 CPUS390XState *env = &cpu->env;
1029
5d69c547
CH		 1030 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1031 /* ugh - can't queue anymore. Let's drop. */
1032 return;
1033 }
1034
1035 env->mchk_index++;
1036 assert(env->mchk_index < MAX_MCHK_QUEUE);
1037
1038 env->mchk_queue[env->mchk_index].type = 1;
1039
1040 env->pending_int |= INTERRUPT_MCHK;
c3affe56 1041 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
5d69c547
CH		 1042}
1043
e72ca652 1044/* fpu_helper.c */
e72ca652
BS		 1045uint32_t set_cc_nz_f32(float32 v);
1046uint32_t set_cc_nz_f64(float64 v);
587626f8 1047uint32_t set_cc_nz_f128(float128 v);
e72ca652 1048
aea1e885 1049/* misc_helper.c */
268846ba
ED		 1050#ifndef CONFIG_USER_ONLY
1051void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1052#endif
d5a103cd 1053void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
b4e2bd35
RH		 1054void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1055 uintptr_t retaddr);
a78b0504 1056
09b99878
CH		 1057#ifdef CONFIG_KVM
1058void kvm_s390_io_interrupt(S390CPU *cpu, uint16_t subchannel_id,
1059 uint16_t subchannel_nr, uint32_t io_int_parm,
1060 uint32_t io_int_word);
1061void kvm_s390_crw_mchk(S390CPU *cpu);
1062void kvm_s390_enable_css_support(S390CPU *cpu);
cc3ac9c4
CH		 1063int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1064 int vq, bool assign);
7f7f9752 1065int kvm_s390_cpu_restart(S390CPU *cpu);
09b99878 1066#else
df1fe5bb
CH		 1067static inline void kvm_s390_io_interrupt(S390CPU *cpu,
1068 uint16_t subchannel_id,
1069 uint16_t subchannel_nr,
1070 uint32_t io_int_parm,
1071 uint32_t io_int_word)
1072{
1073}
1074static inline void kvm_s390_crw_mchk(S390CPU *cpu)
1075{
1076}
09b99878
CH		 1077static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1078{
1079}
cc3ac9c4
CH		 1080static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1081 uint32_t sch, int vq,
b4436a0b
CH		 1082 bool assign)
1083{
1084 return -ENOSYS;
1085}
7f7f9752
ED		 1086static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1087{
1088 return -ENOSYS;
1089}
09b99878 1090#endif
df1fe5bb 1091
7f7f9752
ED		 1092static inline int s390_cpu_restart(S390CPU *cpu)
1093{
1094 if (kvm_enabled()) {
1095 return kvm_s390_cpu_restart(cpu);
1096 }
1097 return -ENOSYS;
1098}
1099
df1fe5bb
CH		 1100static inline void s390_io_interrupt(S390CPU *cpu,
1101 uint16_t subchannel_id,
1102 uint16_t subchannel_nr,
1103 uint32_t io_int_parm,
1104 uint32_t io_int_word)
1105{
1106 if (kvm_enabled()) {
1107 kvm_s390_io_interrupt(cpu, subchannel_id, subchannel_nr, io_int_parm,
1108 io_int_word);
1109 } else {
f9466733 1110 cpu_inject_io(cpu, subchannel_id, subchannel_nr, io_int_parm,
df1fe5bb
CH		 1111 io_int_word);
1112 }
1113}
1114
1115static inline void s390_crw_mchk(S390CPU *cpu)
1116{
1117 if (kvm_enabled()) {
1118 kvm_s390_crw_mchk(cpu);
1119 } else {
f9466733 1120 cpu_inject_crw_mchk(cpu);
df1fe5bb
CH		 1121 }
1122}
1123
cc3ac9c4
CH		 1124static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1125 uint32_t sch_id, int vq,
b4436a0b
CH		 1126 bool assign)
1127{
1128 if (kvm_enabled()) {
cc3ac9c4 1129 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
b4436a0b
CH		 1130 } else {
1131 return -ENOSYS;
1132 }
1133}
1134
10ec5117 1135#endif
Empty description
This page took 0.635484 seconds and 4 git commands to generate.