[qemu.git] / dma-helpers.c

/*
 * DMA helper functions
 *
 * Copyright (c) 2009 Red Hat
 *
 * This work is licensed under the terms of the GNU General Public License
 * (GNU GPL), version 2 or later.
 */

#include "dma.h"
#include "trace.h"
#include "range.h"
#include "qemu-thread.h"

/* #define DEBUG_IOMMU */

static void do_dma_memory_set(dma_addr_t addr, uint8_t c, dma_addr_t len)
{
#define FILLBUF_SIZE 512
    uint8_t fillbuf[FILLBUF_SIZE];
    int l;

    memset(fillbuf, c, FILLBUF_SIZE);
    while (len > 0) {
        l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE;
        cpu_physical_memory_rw(addr, fillbuf, l, true);
        len -= l;
        addr += l;
    }
}

int dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, dma_addr_t len)
{
    dma_barrier(dma, DMA_DIRECTION_FROM_DEVICE);

    if (dma_has_iommu(dma)) {
        return iommu_dma_memory_set(dma, addr, c, len);
    }
    do_dma_memory_set(addr, c, len);

    return 0;
}

void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint, DMAContext *dma)
{
    qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry));
    qsg->nsg = 0;
    qsg->nalloc = alloc_hint;
    qsg->size = 0;
    qsg->dma = dma;
}

void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len)
{
    if (qsg->nsg == qsg->nalloc) {
        qsg->nalloc = 2 * qsg->nalloc + 1;
        qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry));
    }
    qsg->sg[qsg->nsg].base = base;
    qsg->sg[qsg->nsg].len = len;
    qsg->size += len;
    ++qsg->nsg;
}

void qemu_sglist_destroy(QEMUSGList *qsg)
{
    g_free(qsg->sg);
    memset(qsg, 0, sizeof(*qsg));
}

typedef struct {
    BlockDriverAIOCB common;
    BlockDriverState *bs;
    BlockDriverAIOCB *acb;
    QEMUSGList *sg;
    uint64_t sector_num;
    DMADirection dir;
    bool in_cancel;
    int sg_cur_index;
    dma_addr_t sg_cur_byte;
    QEMUIOVector iov;
    QEMUBH *bh;
    DMAIOFunc *io_func;
} DMAAIOCB;

static void dma_bdrv_cb(void *opaque, int ret);

static void reschedule_dma(void *opaque)
{
    DMAAIOCB *dbs = (DMAAIOCB *)opaque;

    qemu_bh_delete(dbs->bh);
    dbs->bh = NULL;
    dma_bdrv_cb(dbs, 0);
}

static void continue_after_map_failure(void *opaque)
{
    DMAAIOCB *dbs = (DMAAIOCB *)opaque;

    dbs->bh = qemu_bh_new(reschedule_dma, dbs);
    qemu_bh_schedule(dbs->bh);
}

static void dma_bdrv_unmap(DMAAIOCB *dbs)
{
    int i;

    for (i = 0; i < dbs->iov.niov; ++i) {
        dma_memory_unmap(dbs->sg->dma, dbs->iov.iov[i].iov_base,
                         dbs->iov.iov[i].iov_len, dbs->dir,
                         dbs->iov.iov[i].iov_len);
    }
    qemu_iovec_reset(&dbs->iov);
}

static void dma_complete(DMAAIOCB *dbs, int ret)
{
    trace_dma_complete(dbs, ret, dbs->common.cb);

    dma_bdrv_unmap(dbs);
    if (dbs->common.cb) {
        dbs->common.cb(dbs->common.opaque, ret);
    }
    qemu_iovec_destroy(&dbs->iov);
    if (dbs->bh) {
        qemu_bh_delete(dbs->bh);
        dbs->bh = NULL;
    }
    if (!dbs->in_cancel) {
        /* Requests may complete while dma_aio_cancel is in progress.  In
         * this case, the AIOCB should not be released because it is still
         * referenced by dma_aio_cancel.  */
        qemu_aio_release(dbs);
    }
}

static void dma_bdrv_cb(void *opaque, int ret)
{
    DMAAIOCB *dbs = (DMAAIOCB *)opaque;
    dma_addr_t cur_addr, cur_len;
    void *mem;

    trace_dma_bdrv_cb(dbs, ret);

    dbs->acb = NULL;
    dbs->sector_num += dbs->iov.size / 512;
    dma_bdrv_unmap(dbs);

    if (dbs->sg_cur_index == dbs->sg->nsg || ret < 0) {
        dma_complete(dbs, ret);
        return;
    }

    while (dbs->sg_cur_index < dbs->sg->nsg) {
        cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte;
        cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte;
        mem = dma_memory_map(dbs->sg->dma, cur_addr, &cur_len, dbs->dir);
        if (!mem)
            break;
        qemu_iovec_add(&dbs->iov, mem, cur_len);
        dbs->sg_cur_byte += cur_len;
        if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) {
            dbs->sg_cur_byte = 0;
            ++dbs->sg_cur_index;
        }
    }

    if (dbs->iov.size == 0) {
        trace_dma_map_wait(dbs);
        cpu_register_map_client(dbs, continue_after_map_failure);
        return;
    }

    dbs->acb = dbs->io_func(dbs->bs, dbs->sector_num, &dbs->iov,
                            dbs->iov.size / 512, dma_bdrv_cb, dbs);
    assert(dbs->acb);
}

static void dma_aio_cancel(BlockDriverAIOCB *acb)
{
    DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);

    trace_dma_aio_cancel(dbs);

    if (dbs->acb) {
        BlockDriverAIOCB *acb = dbs->acb;
        dbs->acb = NULL;
        dbs->in_cancel = true;
        bdrv_aio_cancel(acb);
        dbs->in_cancel = false;
    }
    dbs->common.cb = NULL;
    dma_complete(dbs, 0);
}

static AIOPool dma_aio_pool = {
    .aiocb_size         = sizeof(DMAAIOCB),
    .cancel             = dma_aio_cancel,
};

BlockDriverAIOCB *dma_bdrv_io(
    BlockDriverState *bs, QEMUSGList *sg, uint64_t sector_num,
    DMAIOFunc *io_func, BlockDriverCompletionFunc *cb,
    void *opaque, DMADirection dir)
{
    DMAAIOCB *dbs = qemu_aio_get(&dma_aio_pool, bs, cb, opaque);

    trace_dma_bdrv_io(dbs, bs, sector_num, (dir == DMA_DIRECTION_TO_DEVICE));

    dbs->acb = NULL;
    dbs->bs = bs;
    dbs->sg = sg;
    dbs->sector_num = sector_num;
    dbs->sg_cur_index = 0;
    dbs->sg_cur_byte = 0;
    dbs->dir = dir;
    dbs->io_func = io_func;
    dbs->bh = NULL;
    qemu_iovec_init(&dbs->iov, sg->nsg);
    dma_bdrv_cb(dbs, 0);
    return &dbs->common;
}


BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs,
                                QEMUSGList *sg, uint64_t sector,
                                void (*cb)(void *opaque, int ret), void *opaque)
{
    return dma_bdrv_io(bs, sg, sector, bdrv_aio_readv, cb, opaque,
                       DMA_DIRECTION_FROM_DEVICE);
}

BlockDriverAIOCB *dma_bdrv_write(BlockDriverState *bs,
                                 QEMUSGList *sg, uint64_t sector,
                                 void (*cb)(void *opaque, int ret), void *opaque)
{
    return dma_bdrv_io(bs, sg, sector, bdrv_aio_writev, cb, opaque,
                       DMA_DIRECTION_TO_DEVICE);
}


static uint64_t dma_buf_rw(uint8_t *ptr, int32_t len, QEMUSGList *sg,
                           DMADirection dir)
{
    uint64_t resid;
    int sg_cur_index;

    resid = sg->size;
    sg_cur_index = 0;
    len = MIN(len, resid);
    while (len > 0) {
        ScatterGatherEntry entry = sg->sg[sg_cur_index++];
        int32_t xfer = MIN(len, entry.len);
        dma_memory_rw(sg->dma, entry.base, ptr, xfer, dir);
        ptr += xfer;
        len -= xfer;
        resid -= xfer;
    }

    return resid;
}

uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg)
{
    return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_FROM_DEVICE);
}

uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg)
{
    return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_TO_DEVICE);
}

void dma_acct_start(BlockDriverState *bs, BlockAcctCookie *cookie,
                    QEMUSGList *sg, enum BlockAcctType type)
{
    bdrv_acct_start(bs, cookie, sg->size, type);
}

bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
                            DMADirection dir)
{
    target_phys_addr_t paddr, plen;

#ifdef DEBUG_IOMMU
    fprintf(stderr, "dma_memory_check context=%p addr=0x" DMA_ADDR_FMT
            " len=0x" DMA_ADDR_FMT " dir=%d\n", dma, addr, len, dir);
#endif

    while (len) {
        if (dma->translate(dma, addr, &paddr, &plen, dir) != 0) {
            return false;
        }

        /* The translation might be valid for larger regions. */
        if (plen > len) {
            plen = len;
        }

        len -= plen;
        addr += plen;
    }

    return true;
}

int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
                        void *buf, dma_addr_t len, DMADirection dir)
{
    target_phys_addr_t paddr, plen;
    int err;

#ifdef DEBUG_IOMMU
    fprintf(stderr, "dma_memory_rw context=%p addr=0x" DMA_ADDR_FMT " len=0x"
            DMA_ADDR_FMT " dir=%d\n", dma, addr, len, dir);
#endif

    while (len) {
        err = dma->translate(dma, addr, &paddr, &plen, dir);
        if (err) {
	    /*
             * In case of failure on reads from the guest, we clean the
             * destination buffer so that a device that doesn't test
             * for errors will not expose qemu internal memory.
	     */
	    memset(buf, 0, len);
            return -1;
        }

        /* The translation might be valid for larger regions. */
        if (plen > len) {
            plen = len;
        }

        cpu_physical_memory_rw(paddr, buf, plen,
                               dir == DMA_DIRECTION_FROM_DEVICE);

        len -= plen;
        addr += plen;
        buf += plen;
    }

    return 0;
}

int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c,
                         dma_addr_t len)
{
    target_phys_addr_t paddr, plen;
    int err;

#ifdef DEBUG_IOMMU
    fprintf(stderr, "dma_memory_set context=%p addr=0x" DMA_ADDR_FMT
            " len=0x" DMA_ADDR_FMT "\n", dma, addr, len);
#endif

    while (len) {
        err = dma->translate(dma, addr, &paddr, &plen,
                             DMA_DIRECTION_FROM_DEVICE);
        if (err) {
            return err;
        }

        /* The translation might be valid for larger regions. */
        if (plen > len) {
            plen = len;
        }

        do_dma_memory_set(paddr, c, plen);

        len -= plen;
        addr += plen;
    }

    return 0;
}

void dma_context_init(DMAContext *dma, DMATranslateFunc translate,
                      DMAMapFunc map, DMAUnmapFunc unmap)
{
#ifdef DEBUG_IOMMU
    fprintf(stderr, "dma_context_init(%p, %p, %p, %p)\n",
            dma, translate, map, unmap);
#endif
    dma->translate = translate;
    dma->map = map;
    dma->unmap = unmap;
}

void *iommu_dma_memory_map(DMAContext *dma, dma_addr_t addr, dma_addr_t *len,
                           DMADirection dir)
{
    int err;
    target_phys_addr_t paddr, plen;
    void *buf;

    if (dma->map) {
        return dma->map(dma, addr, len, dir);
    }

    plen = *len;
    err = dma->translate(dma, addr, &paddr, &plen, dir);
    if (err) {
        return NULL;
    }

    /*
     * If this is true, the virtual region is contiguous,
     * but the translated physical region isn't. We just
     * clamp *len, much like cpu_physical_memory_map() does.
     */
    if (plen < *len) {
        *len = plen;
    }

    buf = cpu_physical_memory_map(paddr, &plen,
                                  dir == DMA_DIRECTION_FROM_DEVICE);
    *len = plen;

    return buf;
}

void iommu_dma_memory_unmap(DMAContext *dma, void *buffer, dma_addr_t len,
                            DMADirection dir, dma_addr_t access_len)
{
    if (dma->unmap) {
        dma->unmap(dma, buffer, len, dir, access_len);
        return;
    }

    cpu_physical_memory_unmap(buffer, len,
                              dir == DMA_DIRECTION_FROM_DEVICE,
                              access_len);

}
Commit	Line	Data
244ab90e AL	1	/*
	2	* DMA helper functions
	3	*
	4	* Copyright (c) 2009 Red Hat
	5	*
	6	* This work is licensed under the terms of the GNU General Public License
	7	* (GNU GPL), version 2 or later.
	8	*/
	9
	10	#include "dma.h"
c57c4658	11	#include "trace.h"
e5332e63 DG	12	#include "range.h"
e5332e63 DG	13	#include "qemu-thread.h"
244ab90e	14
e5332e63 DG	15	/* #define DEBUG_IOMMU */
	16
	17	static void do_dma_memory_set(dma_addr_t addr, uint8_t c, dma_addr_t len)
d86a77f8 DG	18	{
	19	#define FILLBUF_SIZE 512
	20	uint8_t fillbuf[FILLBUF_SIZE];
	21	int l;
	22
	23	memset(fillbuf, c, FILLBUF_SIZE);
	24	while (len > 0) {
	25	l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE;
	26	cpu_physical_memory_rw(addr, fillbuf, l, true);
bc9b78de BH	27	len -= l;
bc9b78de BH	28	addr += l;
d86a77f8	29	}
e5332e63 DG	30	}
	31
	32	int dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c, dma_addr_t len)
	33	{
7a0bac4d BH	34	dma_barrier(dma, DMA_DIRECTION_FROM_DEVICE);
7a0bac4d BH	35
e5332e63 DG	36	if (dma_has_iommu(dma)) {
	37	return iommu_dma_memory_set(dma, addr, c, len);
	38	}
	39	do_dma_memory_set(addr, c, len);
	40
d86a77f8 DG	41	return 0;
	42	}
	43
c65bcef3	44	void qemu_sglist_init(QEMUSGList qsg, int alloc_hint, DMAContext dma)
244ab90e	45	{
7267c094	46	qsg->sg = g_malloc(alloc_hint * sizeof(ScatterGatherEntry));
244ab90e AL	47	qsg->nsg = 0;
	48	qsg->nalloc = alloc_hint;
	49	qsg->size = 0;
c65bcef3	50	qsg->dma = dma;
244ab90e AL	51	}
244ab90e AL	52
d3231181	53	void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len)
244ab90e AL	54	{
	55	if (qsg->nsg == qsg->nalloc) {
	56	qsg->nalloc = 2 * qsg->nalloc + 1;
7267c094	57	qsg->sg = g_realloc(qsg->sg, qsg->nalloc * sizeof(ScatterGatherEntry));
244ab90e AL	58	}
	59	qsg->sg[qsg->nsg].base = base;
	60	qsg->sg[qsg->nsg].len = len;
	61	qsg->size += len;
	62	++qsg->nsg;
	63	}
	64
	65	void qemu_sglist_destroy(QEMUSGList *qsg)
	66	{
7267c094	67	g_free(qsg->sg);
ea8d82a1	68	memset(qsg, 0, sizeof(*qsg));
244ab90e AL	69	}
244ab90e AL	70
59a703eb	71	typedef struct {
37b7842c	72	BlockDriverAIOCB common;
59a703eb AL	73	BlockDriverState *bs;
	74	BlockDriverAIOCB *acb;
	75	QEMUSGList *sg;
	76	uint64_t sector_num;
43cf8ae6	77	DMADirection dir;
c3adb5b9	78	bool in_cancel;
59a703eb	79	int sg_cur_index;
d3231181	80	dma_addr_t sg_cur_byte;
59a703eb AL	81	QEMUIOVector iov;
59a703eb AL	82	QEMUBH *bh;
cb144ccb	83	DMAIOFunc *io_func;
37b7842c	84	} DMAAIOCB;
59a703eb AL	85
	86	static void dma_bdrv_cb(void *opaque, int ret);
	87
	88	static void reschedule_dma(void *opaque)
	89	{
37b7842c	90	DMAAIOCB dbs = (DMAAIOCB )opaque;
59a703eb AL	91
	92	qemu_bh_delete(dbs->bh);
	93	dbs->bh = NULL;
c3adb5b9	94	dma_bdrv_cb(dbs, 0);
59a703eb AL	95	}
	96
	97	static void continue_after_map_failure(void *opaque)
	98	{
37b7842c	99	DMAAIOCB dbs = (DMAAIOCB )opaque;
59a703eb AL	100
	101	dbs->bh = qemu_bh_new(reschedule_dma, dbs);
	102	qemu_bh_schedule(dbs->bh);
	103	}
	104
7403b14e	105	static void dma_bdrv_unmap(DMAAIOCB *dbs)
59a703eb	106	{
59a703eb AL	107	int i;
59a703eb AL	108
59a703eb	109	for (i = 0; i < dbs->iov.niov; ++i) {
c65bcef3 DG	110	dma_memory_unmap(dbs->sg->dma, dbs->iov.iov[i].iov_base,
	111	dbs->iov.iov[i].iov_len, dbs->dir,
	112	dbs->iov.iov[i].iov_len);
59a703eb	113	}
c3adb5b9 PB	114	qemu_iovec_reset(&dbs->iov);
	115	}
	116
	117	static void dma_complete(DMAAIOCB *dbs, int ret)
	118	{
c57c4658 KW	119	trace_dma_complete(dbs, ret, dbs->common.cb);
c57c4658 KW	120
c3adb5b9 PB	121	dma_bdrv_unmap(dbs);
	122	if (dbs->common.cb) {
	123	dbs->common.cb(dbs->common.opaque, ret);
	124	}
	125	qemu_iovec_destroy(&dbs->iov);
	126	if (dbs->bh) {
	127	qemu_bh_delete(dbs->bh);
	128	dbs->bh = NULL;
	129	}
	130	if (!dbs->in_cancel) {
	131	/* Requests may complete while dma_aio_cancel is in progress. In
	132	* this case, the AIOCB should not be released because it is still
	133	* referenced by dma_aio_cancel. */
	134	qemu_aio_release(dbs);
	135	}
7403b14e AL	136	}
7403b14e AL	137
856ae5c3	138	static void dma_bdrv_cb(void *opaque, int ret)
7403b14e AL	139	{
7403b14e AL	140	DMAAIOCB dbs = (DMAAIOCB )opaque;
c65bcef3	141	dma_addr_t cur_addr, cur_len;
7403b14e AL	142	void *mem;
7403b14e AL	143
c57c4658 KW	144	trace_dma_bdrv_cb(dbs, ret);
c57c4658 KW	145
7403b14e AL	146	dbs->acb = NULL;
	147	dbs->sector_num += dbs->iov.size / 512;
	148	dma_bdrv_unmap(dbs);
59a703eb AL	149
59a703eb AL	150	if (dbs->sg_cur_index == dbs->sg->nsg \|\| ret < 0) {
c3adb5b9	151	dma_complete(dbs, ret);
59a703eb AL	152	return;
	153	}
	154
	155	while (dbs->sg_cur_index < dbs->sg->nsg) {
	156	cur_addr = dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byte;
	157	cur_len = dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte;
c65bcef3	158	mem = dma_memory_map(dbs->sg->dma, cur_addr, &cur_len, dbs->dir);
59a703eb AL	159	if (!mem)
	160	break;
	161	qemu_iovec_add(&dbs->iov, mem, cur_len);
	162	dbs->sg_cur_byte += cur_len;
	163	if (dbs->sg_cur_byte == dbs->sg->sg[dbs->sg_cur_index].len) {
	164	dbs->sg_cur_byte = 0;
	165	++dbs->sg_cur_index;
	166	}
	167	}
	168
	169	if (dbs->iov.size == 0) {
c57c4658	170	trace_dma_map_wait(dbs);
59a703eb AL	171	cpu_register_map_client(dbs, continue_after_map_failure);
	172	return;
	173	}
	174
cb144ccb CH	175	dbs->acb = dbs->io_func(dbs->bs, dbs->sector_num, &dbs->iov,
cb144ccb CH	176	dbs->iov.size / 512, dma_bdrv_cb, dbs);
6bee44ea	177	assert(dbs->acb);
59a703eb AL	178	}
59a703eb AL	179
c16b5a2c CH	180	static void dma_aio_cancel(BlockDriverAIOCB *acb)
	181	{
	182	DMAAIOCB *dbs = container_of(acb, DMAAIOCB, common);
	183
c57c4658 KW	184	trace_dma_aio_cancel(dbs);
c57c4658 KW	185
c16b5a2c	186	if (dbs->acb) {
c3adb5b9 PB	187	BlockDriverAIOCB *acb = dbs->acb;
	188	dbs->acb = NULL;
	189	dbs->in_cancel = true;
	190	bdrv_aio_cancel(acb);
	191	dbs->in_cancel = false;
c16b5a2c	192	}
c3adb5b9 PB	193	dbs->common.cb = NULL;
c3adb5b9 PB	194	dma_complete(dbs, 0);
c16b5a2c CH	195	}
	196
	197	static AIOPool dma_aio_pool = {
	198	.aiocb_size = sizeof(DMAAIOCB),
	199	.cancel = dma_aio_cancel,
	200	};
	201
cb144ccb	202	BlockDriverAIOCB *dma_bdrv_io(
59a703eb	203	BlockDriverState bs, QEMUSGList sg, uint64_t sector_num,
cb144ccb	204	DMAIOFunc io_func, BlockDriverCompletionFunc cb,
43cf8ae6	205	void *opaque, DMADirection dir)
59a703eb	206	{
cb144ccb	207	DMAAIOCB *dbs = qemu_aio_get(&dma_aio_pool, bs, cb, opaque);
59a703eb	208
43cf8ae6	209	trace_dma_bdrv_io(dbs, bs, sector_num, (dir == DMA_DIRECTION_TO_DEVICE));
c57c4658	210
37b7842c	211	dbs->acb = NULL;
59a703eb	212	dbs->bs = bs;
59a703eb AL	213	dbs->sg = sg;
	214	dbs->sector_num = sector_num;
	215	dbs->sg_cur_index = 0;
	216	dbs->sg_cur_byte = 0;
43cf8ae6	217	dbs->dir = dir;
cb144ccb	218	dbs->io_func = io_func;
59a703eb AL	219	dbs->bh = NULL;
	220	qemu_iovec_init(&dbs->iov, sg->nsg);
	221	dma_bdrv_cb(dbs, 0);
37b7842c	222	return &dbs->common;
59a703eb AL	223	}
	224
	225
	226	BlockDriverAIOCB dma_bdrv_read(BlockDriverState bs,
	227	QEMUSGList *sg, uint64_t sector,
	228	void (cb)(void opaque, int ret), void *opaque)
	229	{
43cf8ae6 DG	230	return dma_bdrv_io(bs, sg, sector, bdrv_aio_readv, cb, opaque,
43cf8ae6 DG	231	DMA_DIRECTION_FROM_DEVICE);
59a703eb AL	232	}
	233
	234	BlockDriverAIOCB dma_bdrv_write(BlockDriverState bs,
	235	QEMUSGList *sg, uint64_t sector,
	236	void (cb)(void opaque, int ret), void *opaque)
	237	{
43cf8ae6 DG	238	return dma_bdrv_io(bs, sg, sector, bdrv_aio_writev, cb, opaque,
43cf8ae6 DG	239	DMA_DIRECTION_TO_DEVICE);
59a703eb	240	}
8171ee35 PB	241
8171ee35 PB	242
c65bcef3 DG	243	static uint64_t dma_buf_rw(uint8_t ptr, int32_t len, QEMUSGList sg,
c65bcef3 DG	244	DMADirection dir)
8171ee35 PB	245	{
	246	uint64_t resid;
	247	int sg_cur_index;
	248
	249	resid = sg->size;
	250	sg_cur_index = 0;
	251	len = MIN(len, resid);
	252	while (len > 0) {
	253	ScatterGatherEntry entry = sg->sg[sg_cur_index++];
	254	int32_t xfer = MIN(len, entry.len);
c65bcef3	255	dma_memory_rw(sg->dma, entry.base, ptr, xfer, dir);
8171ee35 PB	256	ptr += xfer;
	257	len -= xfer;
	258	resid -= xfer;
	259	}
	260
	261	return resid;
	262	}
	263
	264	uint64_t dma_buf_read(uint8_t ptr, int32_t len, QEMUSGList sg)
	265	{
c65bcef3	266	return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_FROM_DEVICE);
8171ee35 PB	267	}
	268
	269	uint64_t dma_buf_write(uint8_t ptr, int32_t len, QEMUSGList sg)
	270	{
c65bcef3	271	return dma_buf_rw(ptr, len, sg, DMA_DIRECTION_TO_DEVICE);
8171ee35	272	}
84a69356 PB	273
	274	void dma_acct_start(BlockDriverState bs, BlockAcctCookie cookie,
	275	QEMUSGList *sg, enum BlockAcctType type)
	276	{
	277	bdrv_acct_start(bs, cookie, sg->size, type);
	278	}
e5332e63 DG	279
	280	bool iommu_dma_memory_valid(DMAContext *dma, dma_addr_t addr, dma_addr_t len,
	281	DMADirection dir)
	282	{
	283	target_phys_addr_t paddr, plen;
	284
	285	#ifdef DEBUG_IOMMU
	286	fprintf(stderr, "dma_memory_check context=%p addr=0x" DMA_ADDR_FMT
	287	" len=0x" DMA_ADDR_FMT " dir=%d\n", dma, addr, len, dir);
	288	#endif
	289
	290	while (len) {
	291	if (dma->translate(dma, addr, &paddr, &plen, dir) != 0) {
	292	return false;
	293	}
	294
	295	/* The translation might be valid for larger regions. */
	296	if (plen > len) {
	297	plen = len;
	298	}
	299
	300	len -= plen;
	301	addr += plen;
	302	}
	303
	304	return true;
	305	}
	306
	307	int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
	308	void *buf, dma_addr_t len, DMADirection dir)
	309	{
	310	target_phys_addr_t paddr, plen;
	311	int err;
	312
	313	#ifdef DEBUG_IOMMU
	314	fprintf(stderr, "dma_memory_rw context=%p addr=0x" DMA_ADDR_FMT " len=0x"
	315	DMA_ADDR_FMT " dir=%d\n", dma, addr, len, dir);
	316	#endif
	317
	318	while (len) {
	319	err = dma->translate(dma, addr, &paddr, &plen, dir);
	320	if (err) {
	321	/*
	322	* In case of failure on reads from the guest, we clean the
	323	* destination buffer so that a device that doesn't test
	324	* for errors will not expose qemu internal memory.
	325	*/
	326	memset(buf, 0, len);
	327	return -1;
	328	}
	329
	330	/* The translation might be valid for larger regions. */
	331	if (plen > len) {
	332	plen = len;
	333	}
	334
	335	cpu_physical_memory_rw(paddr, buf, plen,
	336	dir == DMA_DIRECTION_FROM_DEVICE);
	337
	338	len -= plen;
	339	addr += plen;
	340	buf += plen;
	341	}
	342
343	return 0;
344	}
345
346	int iommu_dma_memory_set(DMAContext *dma, dma_addr_t addr, uint8_t c,
347	dma_addr_t len)
348	{
349	target_phys_addr_t paddr, plen;
350	int err;
351
352	#ifdef DEBUG_IOMMU
353	fprintf(stderr, "dma_memory_set context=%p addr=0x" DMA_ADDR_FMT
354	" len=0x" DMA_ADDR_FMT "\n", dma, addr, len);
355	#endif
356
357	while (len) {
358	err = dma->translate(dma, addr, &paddr, &plen,
359	DMA_DIRECTION_FROM_DEVICE);
360	if (err) {
361	return err;
362	}
363
364	/* The translation might be valid for larger regions. */
365	if (plen > len) {
366	plen = len;
367	}
368
369	do_dma_memory_set(paddr, c, plen);
370
371	len -= plen;
372	addr += plen;
373	}
374
375	return 0;
376	}
377
378	void dma_context_init(DMAContext *dma, DMATranslateFunc translate,
379	DMAMapFunc map, DMAUnmapFunc unmap)
380	{
381	#ifdef DEBUG_IOMMU
382	fprintf(stderr, "dma_context_init(%p, %p, %p, %p)\n",
383	dma, translate, map, unmap);
384	#endif
385	dma->translate = translate;
386	dma->map = map;
387	dma->unmap = unmap;
388	}
389
390	void iommu_dma_memory_map(DMAContext dma, dma_addr_t addr, dma_addr_t *len,
391	DMADirection dir)
392	{
393	int err;
394	target_phys_addr_t paddr, plen;
395	void *buf;
396
397	if (dma->map) {
398	return dma->map(dma, addr, len, dir);
399	}
400
401	plen = *len;
402	err = dma->translate(dma, addr, &paddr, &plen, dir);
403	if (err) {
404	return NULL;
405	}
406
407	/*
408	* If this is true, the virtual region is contiguous,
409	* but the translated physical region isn't. We just
410	* clamp *len, much like cpu_physical_memory_map() does.
411	*/
412	if (plen < *len) {
413	*len = plen;
414	}
415
416	buf = cpu_physical_memory_map(paddr, &plen,
417	dir == DMA_DIRECTION_FROM_DEVICE);
418	*len = plen;
419
420	return buf;
421	}
422
423	void iommu_dma_memory_unmap(DMAContext dma, void buffer, dma_addr_t len,
424	DMADirection dir, dma_addr_t access_len)
425	{
426	if (dma->unmap) {
427	dma->unmap(dma, buffer, len, dir, access_len);
428	return;
429	}
430
431	cpu_physical_memory_unmap(buffer, len,
432	dir == DMA_DIRECTION_FROM_DEVICE,
433	access_len);
434
435	}