[qemu.git] / hw / acpi_piix4.c

/*
 * ACPI implementation
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License version 2 as published by the Free Software Foundation.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>
 */
#include "hw.h"
#include "pc.h"
#include "apm.h"
#include "pm_smbus.h"
#include "pci.h"
#include "acpi.h"
#include "sysemu.h"
#include "range.h"

//#define DEBUG

#ifdef DEBUG
# define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
#else
# define PIIX4_DPRINTF(format, ...)     do { } while (0)
#endif

#define ACPI_DBG_IO_ADDR  0xb044

#define GPE_BASE 0xafe0
#define PCI_BASE 0xae00
#define PCI_EJ_BASE 0xae08
#define PCI_RMV_BASE 0xae0c

#define PIIX4_PCI_HOTPLUG_STATUS 2

struct gpe_regs {
    uint16_t sts; /* status */
    uint16_t en;  /* enabled */
};

struct pci_status {
    uint32_t up;
    uint32_t down;
};

typedef struct PIIX4PMState {
    PCIDevice dev;
    IORange ioport;
    uint16_t pmsts;
    uint16_t pmen;
    uint16_t pmcntrl;

    APMState apm;

    QEMUTimer *tmr_timer;
    int64_t tmr_overflow_time;

    PMSMBus smb;
    uint32_t smb_io_base;

    qemu_irq irq;
    qemu_irq cmos_s3;
    qemu_irq smi_irq;
    int kvm_enabled;

    /* for pci hotplug */
    struct gpe_regs gpe;
    struct pci_status pci0_status;
    uint32_t pci0_hotplug_enable;
} PIIX4PMState;

static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);

#define ACPI_ENABLE 0xf1
#define ACPI_DISABLE 0xf0

static uint32_t get_pmtmr(PIIX4PMState *s)
{
    uint32_t d;
    d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
    return d & 0xffffff;
}

static int get_pmsts(PIIX4PMState *s)
{
    int64_t d;

    d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
                 get_ticks_per_sec());
    if (d >= s->tmr_overflow_time)
        s->pmsts |= ACPI_BITMASK_TIMER_STATUS;
    return s->pmsts;
}

static void pm_update_sci(PIIX4PMState *s)
{
    int sci_level, pmsts;
    int64_t expire_time;

    pmsts = get_pmsts(s);
    sci_level = (((pmsts & s->pmen) &
                  (ACPI_BITMASK_RT_CLOCK_ENABLE |
                   ACPI_BITMASK_POWER_BUTTON_ENABLE |
                   ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
                   ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
        (((s->gpe.sts & s->gpe.en) & PIIX4_PCI_HOTPLUG_STATUS) != 0);

    qemu_set_irq(s->irq, sci_level);
    /* schedule a timer interruption if needed */
    if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
        !(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
        expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
                               PM_TIMER_FREQUENCY);
        qemu_mod_timer(s->tmr_timer, expire_time);
    } else {
        qemu_del_timer(s->tmr_timer);
    }
}

static void pm_tmr_timer(void *opaque)
{
    PIIX4PMState *s = opaque;
    pm_update_sci(s);
}

static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
                            uint64_t val)
{
    PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);

    if (width != 2) {
        PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
                      (unsigned)addr, width, (unsigned)val);
    }

    switch(addr) {
    case 0x00:
        {
            int64_t d;
            int pmsts;
            pmsts = get_pmsts(s);
            if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
                /* if TMRSTS is reset, then compute the new overflow time */
                d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
                             get_ticks_per_sec());
                s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
            }
            s->pmsts &= ~val;
            pm_update_sci(s);
        }
        break;
    case 0x02:
        s->pmen = val;
        pm_update_sci(s);
        break;
    case 0x04:
        {
            int sus_typ;
            s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
            if (val & ACPI_BITMASK_SLEEP_ENABLE) {
                /* change suspend type */
                sus_typ = (val >> 10) & 7;
                switch(sus_typ) {
                case 0: /* soft power off */
                    qemu_system_shutdown_request();
                    break;
                case 1:
                    /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
                       Pretend that resume was caused by power button */
                    s->pmsts |= (ACPI_BITMASK_WAKE_STATUS |
                                 ACPI_BITMASK_POWER_BUTTON_STATUS);
                    qemu_system_reset_request();
                    if (s->cmos_s3) {
                        qemu_irq_raise(s->cmos_s3);
                    }
                default:
                    break;
                }
            }
        }
        break;
    default:
        break;
    }
    PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
}

static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
                            uint64_t *data)
{
    PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
    uint32_t val;

    switch(addr) {
    case 0x00:
        val = get_pmsts(s);
        break;
    case 0x02:
        val = s->pmen;
        break;
    case 0x04:
        val = s->pmcntrl;
        break;
    case 0x08:
        val = get_pmtmr(s);
        break;
    default:
        val = 0;
        break;
    }
    PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
    *data = val;
}

static const IORangeOps pm_iorange_ops = {
    .read = pm_ioport_read,
    .write = pm_ioport_write,
};

static void apm_ctrl_changed(uint32_t val, void *arg)
{
    PIIX4PMState *s = arg;

    /* ACPI specs 3.0, 4.7.2.5 */
    if (val == ACPI_ENABLE) {
        s->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
    } else if (val == ACPI_DISABLE) {
        s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
    }

    if (s->dev.config[0x5b] & (1 << 1)) {
        if (s->smi_irq) {
            qemu_irq_raise(s->smi_irq);
        }
    }
}

static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
}

static void pm_io_space_update(PIIX4PMState *s)
{
    uint32_t pm_io_base;

    if (s->dev.config[0x80] & 1) {
        pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
        pm_io_base &= 0xffc0;

        /* XXX: need to improve memory and ioport allocation */
        PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
        iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
        ioport_register(&s->ioport);
    }
}

static void pm_write_config(PCIDevice *d,
                            uint32_t address, uint32_t val, int len)
{
    pci_default_write_config(d, address, val, len);
    if (range_covers_byte(address, len, 0x80))
        pm_io_space_update((PIIX4PMState *)d);
}

static int vmstate_acpi_post_load(void *opaque, int version_id)
{
    PIIX4PMState *s = opaque;

    pm_io_space_update(s);
    return 0;
}

static const VMStateDescription vmstate_gpe = {
    .name = "gpe",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT16(sts, struct gpe_regs),
        VMSTATE_UINT16(en, struct gpe_regs),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_pci_status = {
    .name = "pci_status",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField []) {
        VMSTATE_UINT32(up, struct pci_status),
        VMSTATE_UINT32(down, struct pci_status),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription vmstate_acpi = {
    .name = "piix4_pm",
    .version_id = 2,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = vmstate_acpi_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
        VMSTATE_UINT16(pmsts, PIIX4PMState),
        VMSTATE_UINT16(pmen, PIIX4PMState),
        VMSTATE_UINT16(pmcntrl, PIIX4PMState),
        VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
        VMSTATE_TIMER(tmr_timer, PIIX4PMState),
        VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
        VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, struct gpe_regs),
        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
                       struct pci_status),
        VMSTATE_END_OF_LIST()
    }
};

static void piix4_update_hotplug(PIIX4PMState *s)
{
    PCIDevice *dev = &s->dev;
    BusState *bus = qdev_get_parent_bus(&dev->qdev);
    DeviceState *qdev, *next;

    s->pci0_hotplug_enable = ~0;

    QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
        PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
        PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
        int slot = PCI_SLOT(pdev->devfn);

        if (info->no_hotplug) {
            s->pci0_hotplug_enable &= ~(1 << slot);
        }
    }
}

static void piix4_reset(void *opaque)
{
    PIIX4PMState *s = opaque;
    uint8_t *pci_conf = s->dev.config;

    pci_conf[0x58] = 0;
    pci_conf[0x59] = 0;
    pci_conf[0x5a] = 0;
    pci_conf[0x5b] = 0;

    if (s->kvm_enabled) {
        /* Mark SMM as already inited (until KVM supports SMM). */
        pci_conf[0x5B] = 0x02;
    }
    piix4_update_hotplug(s);
}

static void piix4_powerdown(void *opaque, int irq, int power_failing)
{
    PIIX4PMState *s = opaque;

    if (!s) {
        qemu_system_shutdown_request();
    } else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
        s->pmsts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
        pm_update_sci(s);
    }
}

static int piix4_pm_initfn(PCIDevice *dev)
{
    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
    uint8_t *pci_conf;

    pci_conf = s->dev.config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
    pci_conf[0x06] = 0x80;
    pci_conf[0x07] = 0x02;
    pci_conf[0x08] = 0x03; // revision number
    pci_conf[0x09] = 0x00;
    pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
    pci_conf[0x3d] = 0x01; // interrupt pin 1

    pci_conf[0x40] = 0x01; /* PM io base read only bit */

    /* APM */
    apm_init(&s->apm, apm_ctrl_changed, s);

    register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);

    if (s->kvm_enabled) {
        /* Mark SMM as already inited to prevent SMM from running.  KVM does not
         * support SMM mode. */
        pci_conf[0x5B] = 0x02;
    }

    /* XXX: which specification is used ? The i82731AB has different
       mappings */
    pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
    pci_conf[0x63] = 0x60;
    pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
	(serial_hds[1] != NULL ? 0x90 : 0);

    pci_conf[0x90] = s->smb_io_base | 1;
    pci_conf[0x91] = s->smb_io_base >> 8;
    pci_conf[0xd2] = 0x09;
    register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
    register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);

    s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);

    qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);

    pm_smbus_init(&s->dev.qdev, &s->smb);
    qemu_register_reset(piix4_reset, s);
    piix4_acpi_system_hot_add_init(dev->bus, s);

    return 0;
}

i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
                       int kvm_enabled)
{
    PCIDevice *dev;
    PIIX4PMState *s;

    dev = pci_create(bus, devfn, "PIIX4_PM");
    qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);

    s = DO_UPCAST(PIIX4PMState, dev, dev);
    s->irq = sci_irq;
    s->cmos_s3 = cmos_s3;
    s->smi_irq = smi_irq;
    s->kvm_enabled = kvm_enabled;

    qdev_init_nofail(&dev->qdev);

    return s->smb.smbus;
}

static PCIDeviceInfo piix4_pm_info = {
    .qdev.name          = "PIIX4_PM",
    .qdev.desc          = "PM",
    .qdev.size          = sizeof(PIIX4PMState),
    .qdev.vmsd          = &vmstate_acpi,
    .qdev.no_user       = 1,
    .no_hotplug         = 1,
    .init               = piix4_pm_initfn,
    .config_write       = pm_write_config,
    .qdev.props         = (Property[]) {
        DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void piix4_pm_register(void)
{
    pci_qdev_register(&piix4_pm_info);
}

device_init(piix4_pm_register);

static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
{
    if (addr & 1)
        return (val >> 8) & 0xff;
    return val & 0xff;
}

static uint32_t gpe_readb(void *opaque, uint32_t addr)
{
    uint32_t val = 0;
    PIIX4PMState *s = opaque;
    struct gpe_regs *g = &s->gpe;

    switch (addr) {
        case GPE_BASE:
        case GPE_BASE + 1:
            val = gpe_read_val(g->sts, addr);
            break;
        case GPE_BASE + 2:
        case GPE_BASE + 3:
            val = gpe_read_val(g->en, addr);
            break;
        default:
            break;
    }

    PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
    return val;
}

static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
{
    if (addr & 1)
        *cur = (*cur & 0xff) | (val << 8);
    else
        *cur = (*cur & 0xff00) | (val & 0xff);
}

static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
{
    uint16_t x1, x0 = val & 0xff;
    int shift = (addr & 1) ? 8 : 0;

    x1 = (*cur >> shift) & 0xff;

    x1 = x1 & ~x0;

    *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
}

static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PIIX4PMState *s = opaque;
    struct gpe_regs *g = &s->gpe;

    switch (addr) {
        case GPE_BASE:
        case GPE_BASE + 1:
            gpe_reset_val(&g->sts, addr, val);
            break;
        case GPE_BASE + 2:
        case GPE_BASE + 3:
            gpe_write_val(&g->en, addr, val);
            break;
        default:
            break;
    }

    pm_update_sci(s);

    PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
}

static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
{
    uint32_t val = 0;
    struct pci_status *g = opaque;
    switch (addr) {
        case PCI_BASE:
            val = g->up;
            break;
        case PCI_BASE + 4:
            val = g->down;
            break;
        default:
            break;
    }

    PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
    return val;
}

static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
{
    struct pci_status *g = opaque;
    switch (addr) {
        case PCI_BASE:
            g->up = val;
            break;
        case PCI_BASE + 4:
            g->down = val;
            break;
   }

    PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
}

static uint32_t pciej_read(void *opaque, uint32_t addr)
{
    PIIX4_DPRINTF("pciej read %x\n", addr);
    return 0;
}

static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
{
    BusState *bus = opaque;
    DeviceState *qdev, *next;
    PCIDevice *dev;
    int slot = ffs(val) - 1;

    QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
        dev = DO_UPCAST(PCIDevice, qdev, qdev);
        if (PCI_SLOT(dev->devfn) == slot) {
            qdev_free(qdev);
        }
    }


    PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
}

static uint32_t pcirmv_read(void *opaque, uint32_t addr)
{
    PIIX4PMState *s = opaque;

    return s->pci0_hotplug_enable;
}

static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val)
{
    return;
}

static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
                                PCIHotplugState state);

static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
{
    struct pci_status *pci0_status = &s->pci0_status;

    register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s);
    register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, s);

    register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
    register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);

    register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
    register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);

    register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
    register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);

    pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
}

static void enable_device(PIIX4PMState *s, int slot)
{
    s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
    s->pci0_status.up |= (1 << slot);
}

static void disable_device(PIIX4PMState *s, int slot)
{
    s->gpe.sts |= PIIX4_PCI_HOTPLUG_STATUS;
    s->pci0_status.down |= (1 << slot);
}

static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
				PCIHotplugState state)
{
    int slot = PCI_SLOT(dev->devfn);
    PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
                                DO_UPCAST(PCIDevice, qdev, qdev));

    /* Don't send event when device is enabled during qemu machine creation:
     * it is present on boot, no hotplug event is necessary. We do send an
     * event when the device is disabled later. */
    if (state == PCI_COLDPLUG_ENABLED) {
        return 0;
    }

    s->pci0_status.up = 0;
    s->pci0_status.down = 0;
    if (state == PCI_HOTPLUG_ENABLED) {
        enable_device(s, slot);
    } else {
        disable_device(s, slot);
    }

    pm_update_sci(s);

    return 0;
}
Commit	Line	Data
93d89f63 IY	1	/*
	2	* ACPI implementation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License version 2 as published by the Free Software Foundation.
	9	*
	10	* This library is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* Lesser General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU Lesser General Public
	16	* License along with this library; if not, see <http://www.gnu.org/licenses/>
	17	*/
	18	#include "hw.h"
	19	#include "pc.h"
	20	#include "apm.h"
	21	#include "pm_smbus.h"
	22	#include "pci.h"
93d89f63	23	#include "acpi.h"
666daa68	24	#include "sysemu.h"
bf1b0071	25	#include "range.h"
93d89f63 IY	26
	27	//#define DEBUG
	28
50d8ff8b IY	29	#ifdef DEBUG
	30	# define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
	31	#else
	32	# define PIIX4_DPRINTF(format, ...) do { } while (0)
	33	#endif
	34
93d89f63 IY	35	#define ACPI_DBG_IO_ADDR 0xb044
93d89f63 IY	36
ac404095 IY	37	#define GPE_BASE 0xafe0
	38	#define PCI_BASE 0xae00
	39	#define PCI_EJ_BASE 0xae08
668643b0	40	#define PCI_RMV_BASE 0xae0c
ac404095	41
4441a287 GN	42	#define PIIX4_PCI_HOTPLUG_STATUS 2
4441a287 GN	43
ac404095 IY	44	struct gpe_regs {
	45	uint16_t sts; /* status */
	46	uint16_t en; /* enabled */
	47	};
	48
	49	struct pci_status {
	50	uint32_t up;
	51	uint32_t down;
	52	};
	53
93d89f63 IY	54	typedef struct PIIX4PMState {
93d89f63 IY	55	PCIDevice dev;
2871a3f6	56	IORange ioport;
93d89f63 IY	57	uint16_t pmsts;
	58	uint16_t pmen;
	59	uint16_t pmcntrl;
	60
	61	APMState apm;
	62
	63	QEMUTimer *tmr_timer;
	64	int64_t tmr_overflow_time;
	65
	66	PMSMBus smb;
e8ec0571	67	uint32_t smb_io_base;
93d89f63 IY	68
	69	qemu_irq irq;
	70	qemu_irq cmos_s3;
	71	qemu_irq smi_irq;
	72	int kvm_enabled;
ac404095 IY	73
	74	/* for pci hotplug */
	75	struct gpe_regs gpe;
	76	struct pci_status pci0_status;
668643b0	77	uint32_t pci0_hotplug_enable;
93d89f63 IY	78	} PIIX4PMState;
93d89f63 IY	79
ac404095 IY	80	static void piix4_acpi_system_hot_add_init(PCIBus bus, PIIX4PMState s);
ac404095 IY	81
93d89f63 IY	82	#define ACPI_ENABLE 0xf1
	83	#define ACPI_DISABLE 0xf0
	84
93d89f63 IY	85	static uint32_t get_pmtmr(PIIX4PMState *s)
	86	{
	87	uint32_t d;
	88	d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, get_ticks_per_sec());
	89	return d & 0xffffff;
	90	}
	91
	92	static int get_pmsts(PIIX4PMState *s)
	93	{
	94	int64_t d;
	95
	96	d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
	97	get_ticks_per_sec());
	98	if (d >= s->tmr_overflow_time)
	99	s->pmsts \|= ACPI_BITMASK_TIMER_STATUS;
	100	return s->pmsts;
	101	}
	102
	103	static void pm_update_sci(PIIX4PMState *s)
	104	{
	105	int sci_level, pmsts;
	106	int64_t expire_time;
	107
	108	pmsts = get_pmsts(s);
	109	sci_level = (((pmsts & s->pmen) &
	110	(ACPI_BITMASK_RT_CLOCK_ENABLE \|
	111	ACPI_BITMASK_POWER_BUTTON_ENABLE \|
	112	ACPI_BITMASK_GLOBAL_LOCK_ENABLE \|
633aa0ac GN	113	ACPI_BITMASK_TIMER_ENABLE)) != 0) \|\|
	114	(((s->gpe.sts & s->gpe.en) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
	115
93d89f63 IY	116	qemu_set_irq(s->irq, sci_level);
	117	/* schedule a timer interruption if needed */
	118	if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
	119	!(pmsts & ACPI_BITMASK_TIMER_STATUS)) {
	120	expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(),
	121	PM_TIMER_FREQUENCY);
	122	qemu_mod_timer(s->tmr_timer, expire_time);
	123	} else {
	124	qemu_del_timer(s->tmr_timer);
	125	}
	126	}
	127
	128	static void pm_tmr_timer(void *opaque)
	129	{
	130	PIIX4PMState *s = opaque;
	131	pm_update_sci(s);
	132	}
	133
2871a3f6 AK	134	static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
2871a3f6 AK	135	uint64_t val)
93d89f63	136	{
2871a3f6 AK	137	PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
	138
	139	if (width != 2) {
	140	PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
	141	(unsigned)addr, width, (unsigned)val);
	142	}
	143
93d89f63 IY	144	switch(addr) {
	145	case 0x00:
	146	{
	147	int64_t d;
	148	int pmsts;
	149	pmsts = get_pmsts(s);
	150	if (pmsts & val & ACPI_BITMASK_TIMER_STATUS) {
	151	/* if TMRSTS is reset, then compute the new overflow time */
	152	d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
	153	get_ticks_per_sec());
	154	s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
	155	}
	156	s->pmsts &= ~val;
	157	pm_update_sci(s);
	158	}
	159	break;
	160	case 0x02:
	161	s->pmen = val;
	162	pm_update_sci(s);
	163	break;
	164	case 0x04:
	165	{
	166	int sus_typ;
	167	s->pmcntrl = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
	168	if (val & ACPI_BITMASK_SLEEP_ENABLE) {
	169	/* change suspend type */
	170	sus_typ = (val >> 10) & 7;
	171	switch(sus_typ) {
	172	case 0: /* soft power off */
	173	qemu_system_shutdown_request();
	174	break;
	175	case 1:
	176	/* ACPI_BITMASK_WAKE_STATUS should be set on resume.
	177	Pretend that resume was caused by power button */
	178	s->pmsts \|= (ACPI_BITMASK_WAKE_STATUS \|
	179	ACPI_BITMASK_POWER_BUTTON_STATUS);
	180	qemu_system_reset_request();
	181	if (s->cmos_s3) {
	182	qemu_irq_raise(s->cmos_s3);
	183	}
	184	default:
	185	break;
	186	}
	187	}
	188	}
	189	break;
	190	default:
	191	break;
	192	}
50d8ff8b	193	PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", addr, val);
93d89f63 IY	194	}
93d89f63 IY	195
2871a3f6 AK	196	static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
2871a3f6 AK	197	uint64_t *data)
93d89f63	198	{
2871a3f6	199	PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
93d89f63 IY	200	uint32_t val;
93d89f63 IY	201
93d89f63 IY	202	switch(addr) {
	203	case 0x00:
	204	val = get_pmsts(s);
	205	break;
	206	case 0x02:
	207	val = s->pmen;
	208	break;
	209	case 0x04:
	210	val = s->pmcntrl;
	211	break;
93d89f63 IY	212	case 0x08:
	213	val = get_pmtmr(s);
	214	break;
	215	default:
	216	val = 0;
	217	break;
	218	}
2871a3f6 AK	219	PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", addr, val);
2871a3f6 AK	220	*data = val;
93d89f63 IY	221	}
93d89f63 IY	222
2871a3f6 AK	223	static const IORangeOps pm_iorange_ops = {
	224	.read = pm_ioport_read,
	225	.write = pm_ioport_write,
	226	};
	227
93d89f63 IY	228	static void apm_ctrl_changed(uint32_t val, void *arg)
	229	{
	230	PIIX4PMState *s = arg;
	231
	232	/* ACPI specs 3.0, 4.7.2.5 */
	233	if (val == ACPI_ENABLE) {
	234	s->pmcntrl \|= ACPI_BITMASK_SCI_ENABLE;
	235	} else if (val == ACPI_DISABLE) {
	236	s->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
	237	}
	238
	239	if (s->dev.config[0x5b] & (1 << 1)) {
	240	if (s->smi_irq) {
	241	qemu_irq_raise(s->smi_irq);
	242	}
	243	}
	244	}
	245
	246	static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
	247	{
50d8ff8b	248	PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
93d89f63 IY	249	}
	250
	251	static void pm_io_space_update(PIIX4PMState *s)
	252	{
	253	uint32_t pm_io_base;
	254
	255	if (s->dev.config[0x80] & 1) {
	256	pm_io_base = le32_to_cpu((uint32_t )(s->dev.config + 0x40));
	257	pm_io_base &= 0xffc0;
	258
	259	/* XXX: need to improve memory and ioport allocation */
50d8ff8b	260	PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
2871a3f6 AK	261	iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
2871a3f6 AK	262	ioport_register(&s->ioport);
93d89f63 IY	263	}
	264	}
	265
	266	static void pm_write_config(PCIDevice *d,
	267	uint32_t address, uint32_t val, int len)
	268	{
	269	pci_default_write_config(d, address, val, len);
	270	if (range_covers_byte(address, len, 0x80))
	271	pm_io_space_update((PIIX4PMState *)d);
	272	}
	273
	274	static int vmstate_acpi_post_load(void *opaque, int version_id)
	275	{
	276	PIIX4PMState *s = opaque;
	277
	278	pm_io_space_update(s);
	279	return 0;
	280	}
	281
4cf3e6f3 AW	282	static const VMStateDescription vmstate_gpe = {
	283	.name = "gpe",
	284	.version_id = 1,
	285	.minimum_version_id = 1,
	286	.minimum_version_id_old = 1,
	287	.fields = (VMStateField []) {
	288	VMSTATE_UINT16(sts, struct gpe_regs),
	289	VMSTATE_UINT16(en, struct gpe_regs),
	290	VMSTATE_END_OF_LIST()
	291	}
	292	};
	293
	294	static const VMStateDescription vmstate_pci_status = {
	295	.name = "pci_status",
	296	.version_id = 1,
	297	.minimum_version_id = 1,
	298	.minimum_version_id_old = 1,
	299	.fields = (VMStateField []) {
	300	VMSTATE_UINT32(up, struct pci_status),
	301	VMSTATE_UINT32(down, struct pci_status),
	302	VMSTATE_END_OF_LIST()
	303	}
	304	};
	305
93d89f63 IY	306	static const VMStateDescription vmstate_acpi = {
93d89f63 IY	307	.name = "piix4_pm",
4cf3e6f3	308	.version_id = 2,
93d89f63 IY	309	.minimum_version_id = 1,
	310	.minimum_version_id_old = 1,
	311	.post_load = vmstate_acpi_post_load,
	312	.fields = (VMStateField []) {
	313	VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
	314	VMSTATE_UINT16(pmsts, PIIX4PMState),
	315	VMSTATE_UINT16(pmen, PIIX4PMState),
	316	VMSTATE_UINT16(pmcntrl, PIIX4PMState),
	317	VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
	318	VMSTATE_TIMER(tmr_timer, PIIX4PMState),
	319	VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
4cf3e6f3 AW	320	VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, struct gpe_regs),
	321	VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
	322	struct pci_status),
93d89f63 IY	323	VMSTATE_END_OF_LIST()
	324	}
	325	};
	326
668643b0 MT	327	static void piix4_update_hotplug(PIIX4PMState *s)
	328	{
	329	PCIDevice *dev = &s->dev;
	330	BusState *bus = qdev_get_parent_bus(&dev->qdev);
	331	DeviceState qdev, next;
	332
	333	s->pci0_hotplug_enable = ~0;
	334
	335	QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
	336	PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
	337	PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
	338	int slot = PCI_SLOT(pdev->devfn);
	339
	340	if (info->no_hotplug) {
	341	s->pci0_hotplug_enable &= ~(1 << slot);
	342	}
	343	}
	344	}
	345
93d89f63 IY	346	static void piix4_reset(void *opaque)
	347	{
	348	PIIX4PMState *s = opaque;
	349	uint8_t *pci_conf = s->dev.config;
	350
	351	pci_conf[0x58] = 0;
	352	pci_conf[0x59] = 0;
	353	pci_conf[0x5a] = 0;
	354	pci_conf[0x5b] = 0;
	355
	356	if (s->kvm_enabled) {
	357	/* Mark SMM as already inited (until KVM supports SMM). */
	358	pci_conf[0x5B] = 0x02;
	359	}
668643b0	360	piix4_update_hotplug(s);
93d89f63 IY	361	}
	362
	363	static void piix4_powerdown(void *opaque, int irq, int power_failing)
	364	{
	365	PIIX4PMState *s = opaque;
	366
	367	if (!s) {
	368	qemu_system_shutdown_request();
	369	} else if (s->pmen & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
	370	s->pmsts \|= ACPI_BITMASK_POWER_BUTTON_STATUS;
	371	pm_update_sci(s);
	372	}
	373	}
	374
e8ec0571	375	static int piix4_pm_initfn(PCIDevice *dev)
93d89f63	376	{
e8ec0571	377	PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
93d89f63 IY	378	uint8_t *pci_conf;
93d89f63 IY	379
93d89f63 IY	380	pci_conf = s->dev.config;
	381	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
	382	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
	383	pci_conf[0x06] = 0x80;
	384	pci_conf[0x07] = 0x02;
	385	pci_conf[0x08] = 0x03; // revision number
	386	pci_conf[0x09] = 0x00;
	387	pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
93d89f63 IY	388	pci_conf[0x3d] = 0x01; // interrupt pin 1
	389
	390	pci_conf[0x40] = 0x01; /* PM io base read only bit */
	391
	392	/* APM */
	393	apm_init(&s->apm, apm_ctrl_changed, s);
	394
	395	register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
	396
93d89f63 IY	397	if (s->kvm_enabled) {
	398	/* Mark SMM as already inited to prevent SMM from running. KVM does not
	399	* support SMM mode. */
	400	pci_conf[0x5B] = 0x02;
	401	}
	402
	403	/* XXX: which specification is used ? The i82731AB has different
	404	mappings */
	405	pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) \| 0x10;
	406	pci_conf[0x63] = 0x60;
	407	pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) \|
	408	(serial_hds[1] != NULL ? 0x90 : 0);
	409
e8ec0571 IY	410	pci_conf[0x90] = s->smb_io_base \| 1;
e8ec0571 IY	411	pci_conf[0x91] = s->smb_io_base >> 8;
93d89f63	412	pci_conf[0xd2] = 0x09;
e8ec0571 IY	413	register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
e8ec0571 IY	414	register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
93d89f63 IY	415
	416	s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
	417
	418	qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
	419
e8ec0571 IY	420	pm_smbus_init(&s->dev.qdev, &s->smb);
e8ec0571 IY	421	qemu_register_reset(piix4_reset, s);
ac404095	422	piix4_acpi_system_hot_add_init(dev->bus, s);
e8ec0571 IY	423
	424	return 0;
	425	}
	426
	427	i2c_bus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base,
	428	qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
	429	int kvm_enabled)
	430	{
	431	PCIDevice *dev;
	432	PIIX4PMState *s;
	433
	434	dev = pci_create(bus, devfn, "PIIX4_PM");
	435	qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
93d89f63	436
e8ec0571	437	s = DO_UPCAST(PIIX4PMState, dev, dev);
93d89f63 IY	438	s->irq = sci_irq;
	439	s->cmos_s3 = cmos_s3;
	440	s->smi_irq = smi_irq;
e8ec0571 IY	441	s->kvm_enabled = kvm_enabled;
	442
	443	qdev_init_nofail(&dev->qdev);
93d89f63 IY	444
	445	return s->smb.smbus;
	446	}
	447
e8ec0571 IY	448	static PCIDeviceInfo piix4_pm_info = {
	449	.qdev.name = "PIIX4_PM",
	450	.qdev.desc = "PM",
	451	.qdev.size = sizeof(PIIX4PMState),
	452	.qdev.vmsd = &vmstate_acpi,
0965f12d GH	453	.qdev.no_user = 1,
0965f12d GH	454	.no_hotplug = 1,
e8ec0571 IY	455	.init = piix4_pm_initfn,
	456	.config_write = pm_write_config,
	457	.qdev.props = (Property[]) {
	458	DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
	459	DEFINE_PROP_END_OF_LIST(),
	460	}
	461	};
	462
	463	static void piix4_pm_register(void)
	464	{
	465	pci_qdev_register(&piix4_pm_info);
	466	}
	467
	468	device_init(piix4_pm_register);
	469
93d89f63 IY	470	static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
	471	{
	472	if (addr & 1)
	473	return (val >> 8) & 0xff;
	474	return val & 0xff;
	475	}
	476
	477	static uint32_t gpe_readb(void *opaque, uint32_t addr)
	478	{
	479	uint32_t val = 0;
633aa0ac GN	480	PIIX4PMState *s = opaque;
	481	struct gpe_regs *g = &s->gpe;
	482
93d89f63 IY	483	switch (addr) {
	484	case GPE_BASE:
	485	case GPE_BASE + 1:
	486	val = gpe_read_val(g->sts, addr);
	487	break;
	488	case GPE_BASE + 2:
	489	case GPE_BASE + 3:
	490	val = gpe_read_val(g->en, addr);
	491	break;
	492	default:
	493	break;
	494	}
	495
50d8ff8b	496	PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
93d89f63 IY	497	return val;
	498	}
	499
	500	static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
	501	{
	502	if (addr & 1)
	503	cur = (cur & 0xff) \| (val << 8);
	504	else
	505	cur = (cur & 0xff00) \| (val & 0xff);
	506	}
	507
	508	static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
	509	{
	510	uint16_t x1, x0 = val & 0xff;
	511	int shift = (addr & 1) ? 8 : 0;
	512
	513	x1 = (*cur >> shift) & 0xff;
	514
	515	x1 = x1 & ~x0;
	516
	517	cur = (cur & (0xff << (8 - shift))) \| (x1 << shift);
	518	}
	519
	520	static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
	521	{
633aa0ac GN	522	PIIX4PMState *s = opaque;
	523	struct gpe_regs *g = &s->gpe;
	524
93d89f63 IY	525	switch (addr) {
	526	case GPE_BASE:
	527	case GPE_BASE + 1:
	528	gpe_reset_val(&g->sts, addr, val);
	529	break;
	530	case GPE_BASE + 2:
	531	case GPE_BASE + 3:
	532	gpe_write_val(&g->en, addr, val);
	533	break;
	534	default:
	535	break;
633aa0ac GN	536	}
	537
	538	pm_update_sci(s);
93d89f63	539
50d8ff8b	540	PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
93d89f63 IY	541	}
	542
	543	static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
	544	{
	545	uint32_t val = 0;
	546	struct pci_status *g = opaque;
	547	switch (addr) {
	548	case PCI_BASE:
	549	val = g->up;
	550	break;
	551	case PCI_BASE + 4:
	552	val = g->down;
	553	break;
	554	default:
	555	break;
	556	}
	557
50d8ff8b	558	PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
93d89f63 IY	559	return val;
	560	}
	561
	562	static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
	563	{
	564	struct pci_status *g = opaque;
	565	switch (addr) {
	566	case PCI_BASE:
	567	g->up = val;
	568	break;
	569	case PCI_BASE + 4:
	570	g->down = val;
	571	break;
	572	}
	573
50d8ff8b	574	PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
93d89f63 IY	575	}
	576
	577	static uint32_t pciej_read(void *opaque, uint32_t addr)
	578	{
50d8ff8b	579	PIIX4_DPRINTF("pciej read %x\n", addr);
93d89f63 IY	580	return 0;
	581	}
	582
	583	static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
	584	{
	585	BusState *bus = opaque;
	586	DeviceState qdev, next;
	587	PCIDevice *dev;
	588	int slot = ffs(val) - 1;
	589
	590	QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
	591	dev = DO_UPCAST(PCIDevice, qdev, qdev);
	592	if (PCI_SLOT(dev->devfn) == slot) {
	593	qdev_free(qdev);
	594	}
	595	}
	596
	597
50d8ff8b	598	PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
93d89f63 IY	599	}
93d89f63 IY	600
668643b0 MT	601	static uint32_t pcirmv_read(void *opaque, uint32_t addr)
	602	{
	603	PIIX4PMState *s = opaque;
	604
	605	return s->pci0_hotplug_enable;
	606	}
	607
	608	static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val)
	609	{
	610	return;
	611	}
	612
4cff0a59 MT	613	static int piix4_device_hotplug(DeviceState qdev, PCIDevice dev,
4cff0a59 MT	614	PCIHotplugState state);
93d89f63	615
ac404095	616	static void piix4_acpi_system_hot_add_init(PCIBus bus, PIIX4PMState s)
93d89f63	617	{
ac404095	618	struct pci_status *pci0_status = &s->pci0_status;
93d89f63	619
633aa0ac GN	620	register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s);
633aa0ac GN	621	register_ioport_read(GPE_BASE, 4, 1, gpe_readb, s);
ac404095 IY	622
	623	register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
	624	register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status);
93d89f63 IY	625
	626	register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
	627	register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus);
	628
668643b0 MT	629	register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
	630	register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s);
	631
ac404095	632	pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
93d89f63 IY	633	}
93d89f63 IY	634
ac404095	635	static void enable_device(PIIX4PMState *s, int slot)
93d89f63	636	{
4441a287	637	s->gpe.sts \|= PIIX4_PCI_HOTPLUG_STATUS;
ac404095	638	s->pci0_status.up \|= (1 << slot);
93d89f63 IY	639	}
93d89f63 IY	640
ac404095	641	static void disable_device(PIIX4PMState *s, int slot)
93d89f63	642	{
4441a287	643	s->gpe.sts \|= PIIX4_PCI_HOTPLUG_STATUS;
ac404095	644	s->pci0_status.down \|= (1 << slot);
93d89f63 IY	645	}
93d89f63 IY	646
4cff0a59 MT	647	static int piix4_device_hotplug(DeviceState qdev, PCIDevice dev,
4cff0a59 MT	648	PCIHotplugState state)
93d89f63 IY	649	{
93d89f63 IY	650	int slot = PCI_SLOT(dev->devfn);
ac404095 IY	651	PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
ac404095 IY	652	DO_UPCAST(PCIDevice, qdev, qdev));
93d89f63	653
4cff0a59 MT	654	/* Don't send event when device is enabled during qemu machine creation:
	655	* it is present on boot, no hotplug event is necessary. We do send an
	656	* event when the device is disabled later. */
	657	if (state == PCI_COLDPLUG_ENABLED) {
5beb8ad5	658	return 0;
4cff0a59	659	}
5beb8ad5	660
ac404095 IY	661	s->pci0_status.up = 0;
ac404095 IY	662	s->pci0_status.down = 0;
4cff0a59	663	if (state == PCI_HOTPLUG_ENABLED) {
ac404095 IY	664	enable_device(s, slot);
	665	} else {
	666	disable_device(s, slot);
	667	}
633aa0ac GN	668
	669	pm_update_sci(s);
	670
93d89f63 IY	671	return 0;
93d89f63 IY	672	}