[qemu.git] / hw / arm / fsl-imx31.c

/*
 * Copyright (c) 2013 Jean-Christophe Dubois <[email protected]>
 *
 * i.MX31 SOC emulation.
 *
 * Based on hw/arm/fsl-imx31.c
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
#include "hw/arm/fsl-imx31.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "chardev/char.h"

static void fsl_imx31_init(Object *obj)
{
    FslIMX31State *s = FSL_IMX31(obj);
    int i;

    object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);

    object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);
    qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());

    object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);
    qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());

    for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
        object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
        qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
    }

    object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);
    qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());

    for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
        object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
        qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
    }

    for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
        object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
        qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
    }

    for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
        object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
        qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
    }
}

static void fsl_imx31_realize(DeviceState *dev, Error **errp)
{
    FslIMX31State *s = FSL_IMX31(dev);
    uint16_t i;
    Error *err = NULL;

    object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
                       qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));

    object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);

    /* Initialize all UARTS */
    for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } serial_table[FSL_IMX31_NUM_UARTS] = {
            { FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
            { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
        };

        if (i < MAX_SERIAL_PORTS) {
            Chardev *chr;

            chr = serial_hds[i];

            if (!chr) {
                char label[20];
                snprintf(label, sizeof(label), "imx31.uart%d", i);
                chr = qemu_chr_new(label, "null");
            }

            qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
        }

        object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            serial_table[i].irq));
    }

    s->gpt.ccm = IMX_CCM(&s->ccm);

    object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
                       qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));

    /* Initialize all EPIT timers */
    for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } epit_table[FSL_IMX31_NUM_EPITS] = {
            { FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
            { FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
        };

        s->epit[i].ccm = IMX_CCM(&s->ccm);

        object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }

        sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            epit_table[i].irq));
    }

    /* Initialize all I2C */
    for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } i2c_table[FSL_IMX31_NUM_I2CS] = {
            { FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
            { FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
            { FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
        };

        /* Initialize the I2C */
        object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        /* Map I2C memory */
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
        /* Connect I2C IRQ to PIC */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            i2c_table[i].irq));
    }

    /* Initialize all GPIOs */
    for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
        static const struct {
            hwaddr addr;
            unsigned int irq;
        } gpio_table[FSL_IMX31_NUM_GPIOS] = {
            { FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
            { FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
            { FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
        };

        object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
                                 &error_abort);
        object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
        if (err) {
            error_propagate(errp, err);
            return;
        }
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
        /* Connect GPIO IRQ to PIC */
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
                           qdev_get_gpio_in(DEVICE(&s->avic),
                                            gpio_table[i].irq));
    }

    /* On a real system, the first 16k is a `secure boot rom' */
    memory_region_init_rom(&s->secure_rom, NULL, "imx31.secure_rom",
                           FSL_IMX31_SECURE_ROM_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
                                &s->secure_rom);

    /* There is also a 16k ROM */
    memory_region_init_rom(&s->rom, NULL, "imx31.rom",
                           FSL_IMX31_ROM_SIZE, &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
                                &s->rom);

    /* initialize internal RAM (16 KB) */
    memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
                           &err);
    if (err) {
        error_propagate(errp, err);
        return;
    }
    memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
                                &s->iram);

    /* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
    memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",
                             &s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
    memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
                                &s->iram_alias);
}

static void fsl_imx31_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = fsl_imx31_realize;
    dc->desc = "i.MX31 SOC";
    /*
     * Reason: uses serial_hds in realize and the kzm board does not
     * support multiple CPUs
     */
    dc->user_creatable = false;
}

static const TypeInfo fsl_imx31_type_info = {
    .name = TYPE_FSL_IMX31,
    .parent = TYPE_DEVICE,
    .instance_size = sizeof(FslIMX31State),
    .instance_init = fsl_imx31_init,
    .class_init = fsl_imx31_class_init,
};

static void fsl_imx31_register_types(void)
{
    type_register_static(&fsl_imx31_type_info);
}

type_init(fsl_imx31_register_types)
Commit	Line	Data
558df83d JCD	1	/*
	2	* Copyright (c) 2013 Jean-Christophe Dubois <[email protected]>
	3	*
	4	* i.MX31 SOC emulation.
	5	*
	6	* Based on hw/arm/fsl-imx31.c
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful, but WITHOUT
	14	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	15	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	16	* for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
12b16722	22	#include "qemu/osdep.h"
da34e65c	23	#include "qapi/error.h"
4771d756 PB	24	#include "qemu-common.h"
4771d756 PB	25	#include "cpu.h"
558df83d JCD	26	#include "hw/arm/fsl-imx31.h"
	27	#include "sysemu/sysemu.h"
	28	#include "exec/address-spaces.h"
	29	#include "hw/boards.h"
8228e353	30	#include "chardev/char.h"
558df83d JCD	31
	32	static void fsl_imx31_init(Object *obj)
	33	{
	34	FslIMX31State *s = FSL_IMX31(obj);
	35	int i;
	36
	37	object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);
	38
	39	object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);
	40	qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());
	41
cb54d868	42	object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX31_CCM);
558df83d JCD	43	qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
	44
	45	for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
	46	object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
	47	qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
	48	}
	49
66542f63	50	object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);
558df83d JCD	51	qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
	52
	53	for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
	54	object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
	55	qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
	56	}
d4e26d10 JCD	57
	58	for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
	59	object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
	60	qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
	61	}
dde0c4ca JCD	62
	63	for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
	64	object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
	65	qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
	66	}
558df83d JCD	67	}
	68
	69	static void fsl_imx31_realize(DeviceState dev, Error *errp)
	70	{
	71	FslIMX31State *s = FSL_IMX31(dev);
	72	uint16_t i;
	73	Error *err = NULL;
	74
	75	object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
	76	if (err) {
	77	error_propagate(errp, err);
	78	return;
	79	}
	80
	81	object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
	82	if (err) {
	83	error_propagate(errp, err);
	84	return;
	85	}
	86	sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX31_AVIC_ADDR);
	87	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
	88	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
	89	sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
	90	qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
	91
	92	object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
	93	if (err) {
	94	error_propagate(errp, err);
	95	return;
	96	}
	97	sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX31_CCM_ADDR);
	98
	99	/* Initialize all UARTS */
	100	for (i = 0; i < FSL_IMX31_NUM_UARTS; i++) {
	101	static const struct {
	102	hwaddr addr;
	103	unsigned int irq;
	104	} serial_table[FSL_IMX31_NUM_UARTS] = {
	105	{ FSL_IMX31_UART1_ADDR, FSL_IMX31_UART1_IRQ },
	106	{ FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ },
	107	};
	108
	109	if (i < MAX_SERIAL_PORTS) {
0ec7b3e7	110	Chardev *chr;
558df83d JCD	111
	112	chr = serial_hds[i];
	113
	114	if (!chr) {
	115	char label[20];
	116	snprintf(label, sizeof(label), "imx31.uart%d", i);
b4948be9	117	chr = qemu_chr_new(label, "null");
558df83d JCD	118	}
	119
	120	qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
	121	}
	122
	123	object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
	124	if (err) {
	125	error_propagate(errp, err);
	126	return;
	127	}
	128
	129	sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
	130	sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
	131	qdev_get_gpio_in(DEVICE(&s->avic),
	132	serial_table[i].irq));
	133	}
	134
cb54d868	135	s->gpt.ccm = IMX_CCM(&s->ccm);
558df83d JCD	136
	137	object_property_set_bool(OBJECT(&s->gpt), true, "realized", &err);
	138	if (err) {
	139	error_propagate(errp, err);
	140	return;
	141	}
	142
	143	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX31_GPT_ADDR);
	144	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
	145	qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX31_GPT_IRQ));
	146
	147	/* Initialize all EPIT timers */
	148	for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {
	149	static const struct {
	150	hwaddr addr;
	151	unsigned int irq;
	152	} epit_table[FSL_IMX31_NUM_EPITS] = {
	153	{ FSL_IMX31_EPIT1_ADDR, FSL_IMX31_EPIT1_IRQ },
	154	{ FSL_IMX31_EPIT2_ADDR, FSL_IMX31_EPIT2_IRQ },
	155	};
	156
cb54d868	157	s->epit[i].ccm = IMX_CCM(&s->ccm);
558df83d JCD	158
	159	object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
	160	if (err) {
	161	error_propagate(errp, err);
	162	return;
	163	}
	164
	165	sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
	166	sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
	167	qdev_get_gpio_in(DEVICE(&s->avic),
	168	epit_table[i].irq));
	169	}
d4e26d10 JCD	170
	171	/* Initialize all I2C */
	172	for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
	173	static const struct {
	174	hwaddr addr;
	175	unsigned int irq;
	176	} i2c_table[FSL_IMX31_NUM_I2CS] = {
	177	{ FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
	178	{ FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
	179	{ FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
	180	};
	181
	182	/* Initialize the I2C */
	183	object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
	184	if (err) {
	185	error_propagate(errp, err);
	186	return;
	187	}
	188	/* Map I2C memory */
	189	sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
	190	/* Connect I2C IRQ to PIC */
	191	sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
	192	qdev_get_gpio_in(DEVICE(&s->avic),
	193	i2c_table[i].irq));
	194	}
dde0c4ca JCD	195
	196	/* Initialize all GPIOs */
	197	for (i = 0; i < FSL_IMX31_NUM_GPIOS; i++) {
	198	static const struct {
	199	hwaddr addr;
	200	unsigned int irq;
	201	} gpio_table[FSL_IMX31_NUM_GPIOS] = {
	202	{ FSL_IMX31_GPIO1_ADDR, FSL_IMX31_GPIO1_IRQ },
	203	{ FSL_IMX31_GPIO2_ADDR, FSL_IMX31_GPIO2_IRQ },
	204	{ FSL_IMX31_GPIO3_ADDR, FSL_IMX31_GPIO3_IRQ }
	205	};
	206
	207	object_property_set_bool(OBJECT(&s->gpio[i]), false, "has-edge-sel",
	208	&error_abort);
	209	object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
	210	if (err) {
	211	error_propagate(errp, err);
	212	return;
	213	}
	214	sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
	215	/* Connect GPIO IRQ to PIC */
	216	sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
	217	qdev_get_gpio_in(DEVICE(&s->avic),
	218	gpio_table[i].irq));
	219	}
558df83d JCD	220
558df83d JCD	221	/* On a real system, the first 16k is a `secure boot rom' */
eda40cc1	222	memory_region_init_rom(&s->secure_rom, NULL, "imx31.secure_rom",
a7aeb5f7	223	FSL_IMX31_SECURE_ROM_SIZE, &err);
558df83d JCD	224	if (err) {
	225	error_propagate(errp, err);
	226	return;
	227	}
	228	memory_region_add_subregion(get_system_memory(), FSL_IMX31_SECURE_ROM_ADDR,
	229	&s->secure_rom);
	230
	231	/* There is also a 16k ROM */
eda40cc1	232	memory_region_init_rom(&s->rom, NULL, "imx31.rom",
a7aeb5f7	233	FSL_IMX31_ROM_SIZE, &err);
558df83d JCD	234	if (err) {
	235	error_propagate(errp, err);
	236	return;
	237	}
	238	memory_region_add_subregion(get_system_memory(), FSL_IMX31_ROM_ADDR,
	239	&s->rom);
	240
	241	/* initialize internal RAM (16 KB) */
98a99ce0	242	memory_region_init_ram(&s->iram, NULL, "imx31.iram", FSL_IMX31_IRAM_SIZE,
558df83d JCD	243	&err);
	244	if (err) {
	245	error_propagate(errp, err);
	246	return;
	247	}
	248	memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ADDR,
	249	&s->iram);
558df83d JCD	250
	251	/* internal RAM (16 KB) is aliased over 256 MB - 16 KB */
	252	memory_region_init_alias(&s->iram_alias, NULL, "imx31.iram_alias",
	253	&s->iram, 0, FSL_IMX31_IRAM_ALIAS_SIZE);
	254	memory_region_add_subregion(get_system_memory(), FSL_IMX31_IRAM_ALIAS_ADDR,
	255	&s->iram_alias);
	256	}
	257
	258	static void fsl_imx31_class_init(ObjectClass oc, void data)
	259	{
	260	DeviceClass *dc = DEVICE_CLASS(oc);
	261
	262	dc->realize = fsl_imx31_realize;
eccfa35e	263	dc->desc = "i.MX31 SOC";
e4e05b7b TH	264	/*
	265	* Reason: uses serial_hds in realize and the kzm board does not
	266	* support multiple CPUs
	267	*/
	268	dc->user_creatable = false;
558df83d JCD	269	}
	270
	271	static const TypeInfo fsl_imx31_type_info = {
	272	.name = TYPE_FSL_IMX31,
	273	.parent = TYPE_DEVICE,
	274	.instance_size = sizeof(FslIMX31State),
	275	.instance_init = fsl_imx31_init,
	276	.class_init = fsl_imx31_class_init,
	277	};
	278
	279	static void fsl_imx31_register_types(void)
	280	{
	281	type_register_static(&fsl_imx31_type_info);
	282	}
	283
	284	type_init(fsl_imx31_register_types)