[qemu.git] / target / ppc / cpu-qom.h

/*
 * QEMU PowerPC CPU
 *
 * Copyright (c) 2012 SUSE LINUX Products GmbH
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see
 * <http://www.gnu.org/licenses/lgpl-2.1.html>
 */
#ifndef QEMU_PPC_CPU_QOM_H
#define QEMU_PPC_CPU_QOM_H

#include "qom/cpu.h"

#ifdef TARGET_PPC64
#define TYPE_POWERPC_CPU "powerpc64-cpu"
#else
#define TYPE_POWERPC_CPU "powerpc-cpu"
#endif

#define POWERPC_CPU_CLASS(klass) \
    OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
#define POWERPC_CPU(obj) \
    OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU)
#define POWERPC_CPU_GET_CLASS(obj) \
    OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)

typedef struct PowerPCCPU PowerPCCPU;
typedef struct CPUPPCState CPUPPCState;
typedef struct ppc_tb_t ppc_tb_t;
typedef struct ppc_dcr_t ppc_dcr_t;

/*****************************************************************************/
/* MMU model                                                                 */
typedef enum powerpc_mmu_t powerpc_mmu_t;
enum powerpc_mmu_t {
    POWERPC_MMU_UNKNOWN    = 0x00000000,
    /* Standard 32 bits PowerPC MMU                            */
    POWERPC_MMU_32B        = 0x00000001,
    /* PowerPC 6xx MMU with software TLB                       */
    POWERPC_MMU_SOFT_6xx   = 0x00000002,
    /* PowerPC 74xx MMU with software TLB                      */
    POWERPC_MMU_SOFT_74xx  = 0x00000003,
    /* PowerPC 4xx MMU with software TLB                       */
    POWERPC_MMU_SOFT_4xx   = 0x00000004,
    /* PowerPC 4xx MMU with software TLB and zones protections */
    POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
    /* PowerPC MMU in real mode only                           */
    POWERPC_MMU_REAL       = 0x00000006,
    /* Freescale MPC8xx MMU model                              */
    POWERPC_MMU_MPC8xx     = 0x00000007,
    /* BookE MMU model                                         */
    POWERPC_MMU_BOOKE      = 0x00000008,
    /* BookE 2.06 MMU model                                    */
    POWERPC_MMU_BOOKE206   = 0x00000009,
    /* PowerPC 601 MMU model (specific BATs format)            */
    POWERPC_MMU_601        = 0x0000000A,
#define POWERPC_MMU_64       0x00010000
    /* 64 bits PowerPC MMU                                     */
    POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
    /* Architecture 2.03 and later (has LPCR) */
    POWERPC_MMU_2_03       = POWERPC_MMU_64 | 0x00000002,
    /* Architecture 2.06 variant                               */
    POWERPC_MMU_2_06       = POWERPC_MMU_64 | 0x00000003,
    /* Architecture 2.07 variant                               */
    POWERPC_MMU_2_07       = POWERPC_MMU_64 | 0x00000004,
    /* Architecture 3.00 variant                               */
    POWERPC_MMU_3_00       = POWERPC_MMU_64 | 0x00000005,
};

/*****************************************************************************/
/* Exception model                                                           */
typedef enum powerpc_excp_t powerpc_excp_t;
enum powerpc_excp_t {
    POWERPC_EXCP_UNKNOWN   = 0,
    /* Standard PowerPC exception model */
    POWERPC_EXCP_STD,
    /* PowerPC 40x exception model      */
    POWERPC_EXCP_40x,
    /* PowerPC 601 exception model      */
    POWERPC_EXCP_601,
    /* PowerPC 602 exception model      */
    POWERPC_EXCP_602,
    /* PowerPC 603 exception model      */
    POWERPC_EXCP_603,
    /* PowerPC 603e exception model     */
    POWERPC_EXCP_603E,
    /* PowerPC G2 exception model       */
    POWERPC_EXCP_G2,
    /* PowerPC 604 exception model      */
    POWERPC_EXCP_604,
    /* PowerPC 7x0 exception model      */
    POWERPC_EXCP_7x0,
    /* PowerPC 7x5 exception model      */
    POWERPC_EXCP_7x5,
    /* PowerPC 74xx exception model     */
    POWERPC_EXCP_74xx,
    /* BookE exception model            */
    POWERPC_EXCP_BOOKE,
    /* PowerPC 970 exception model      */
    POWERPC_EXCP_970,
    /* POWER7 exception model           */
    POWERPC_EXCP_POWER7,
    /* POWER8 exception model           */
    POWERPC_EXCP_POWER8,
    /* POWER9 exception model           */
    POWERPC_EXCP_POWER9,
};

/*****************************************************************************/
/* PM instructions */
typedef enum {
    PPC_PM_DOZE,
    PPC_PM_NAP,
    PPC_PM_SLEEP,
    PPC_PM_RVWINKLE,
    PPC_PM_STOP,
} powerpc_pm_insn_t;

/*****************************************************************************/
/* Input pins model                                                          */
typedef enum powerpc_input_t powerpc_input_t;
enum powerpc_input_t {
    PPC_FLAGS_INPUT_UNKNOWN = 0,
    /* PowerPC 6xx bus                  */
    PPC_FLAGS_INPUT_6xx,
    /* BookE bus                        */
    PPC_FLAGS_INPUT_BookE,
    /* PowerPC 405 bus                  */
    PPC_FLAGS_INPUT_405,
    /* PowerPC 970 bus                  */
    PPC_FLAGS_INPUT_970,
    /* PowerPC POWER7 bus               */
    PPC_FLAGS_INPUT_POWER7,
    /* PowerPC POWER9 bus               */
    PPC_FLAGS_INPUT_POWER9,
    /* PowerPC 401 bus                  */
    PPC_FLAGS_INPUT_401,
    /* Freescale RCPU bus               */
    PPC_FLAGS_INPUT_RCPU,
};

typedef struct PPCHash64Options PPCHash64Options;

/**
 * PowerPCCPUClass:
 * @parent_realize: The parent class' realize handler.
 * @parent_reset: The parent class' reset handler.
 *
 * A PowerPC CPU model.
 */
typedef struct PowerPCCPUClass {
    /*< private >*/
    CPUClass parent_class;
    /*< public >*/

    DeviceRealize parent_realize;
    DeviceUnrealize parent_unrealize;
    void (*parent_reset)(CPUState *cpu);
    void (*parent_parse_features)(const char *type, char *str, Error **errp);

    uint32_t pvr;
    bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
    uint64_t pcr_mask;          /* Available bits in PCR register */
    uint64_t pcr_supported;     /* Bits for supported PowerISA versions */
    uint32_t svr;
    uint64_t insns_flags;
    uint64_t insns_flags2;
    uint64_t msr_mask;
    uint64_t lpcr_pm;           /* Power-saving mode Exit Cause Enable bits */
    powerpc_mmu_t   mmu_model;
    powerpc_excp_t  excp_model;
    powerpc_input_t bus_model;
    uint32_t flags;
    int bfd_mach;
    uint32_t l1_dcache_size, l1_icache_size;
#ifndef CONFIG_USER_ONLY
    unsigned int gdb_num_sprs;
    const char *gdb_spr_xml;
#endif
    const PPCHash64Options *hash64_opts;
    struct ppc_radix_page_info *radix_page_info;
    uint32_t lrg_decr_bits;
    void (*init_proc)(CPUPPCState *env);
    int  (*check_pow)(CPUPPCState *env);
    int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx);
    bool (*interrupts_big_endian)(PowerPCCPU *cpu);
} PowerPCCPUClass;

#ifndef CONFIG_USER_ONLY
typedef struct PPCTimebase {
    uint64_t guest_timebase;
    int64_t time_of_the_day_ns;
} PPCTimebase;

extern const struct VMStateDescription vmstate_ppc_timebase;

#define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) {            \
    .name       = (stringify(_field)),                                \
    .version_id = (_version),                                         \
    .size       = sizeof(PPCTimebase),                                \
    .vmsd       = &vmstate_ppc_timebase,                              \
    .flags      = VMS_STRUCT,                                         \
    .offset     = vmstate_offset_value(_state, _field, PPCTimebase),  \
}

void cpu_ppc_clock_vm_state_change(void *opaque, int running,
                                   RunState state);
#endif

#endif
Commit	Line	Data
1d0cb67d AF	1	/*
	2	* QEMU PowerPC CPU
	3	*
	4	* Copyright (c) 2012 SUSE LINUX Products GmbH
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2.1 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see
	18	* <http://www.gnu.org/licenses/lgpl-2.1.html>
	19	*/
	20	#ifndef QEMU_PPC_CPU_QOM_H
	21	#define QEMU_PPC_CPU_QOM_H
	22
14cccb61	23	#include "qom/cpu.h"
1d0cb67d AF	24
	25	#ifdef TARGET_PPC64
	26	#define TYPE_POWERPC_CPU "powerpc64-cpu"
1d0cb67d AF	27	#else
	28	#define TYPE_POWERPC_CPU "powerpc-cpu"
	29	#endif
	30
	31	#define POWERPC_CPU_CLASS(klass) \
	32	OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
	33	#define POWERPC_CPU(obj) \
	34	OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU)
	35	#define POWERPC_CPU_GET_CLASS(obj) \
	36	OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
	37
d0e39c5d	38	typedef struct PowerPCCPU PowerPCCPU;
2d34fe39 PB	39	typedef struct CPUPPCState CPUPPCState;
	40	typedef struct ppc_tb_t ppc_tb_t;
	41	typedef struct ppc_dcr_t ppc_dcr_t;
	42
	43	/*****************************************************************************/
	44	/* MMU model */
	45	typedef enum powerpc_mmu_t powerpc_mmu_t;
	46	enum powerpc_mmu_t {
	47	POWERPC_MMU_UNKNOWN = 0x00000000,
	48	/* Standard 32 bits PowerPC MMU */
	49	POWERPC_MMU_32B = 0x00000001,
	50	/* PowerPC 6xx MMU with software TLB */
	51	POWERPC_MMU_SOFT_6xx = 0x00000002,
	52	/* PowerPC 74xx MMU with software TLB */
	53	POWERPC_MMU_SOFT_74xx = 0x00000003,
	54	/* PowerPC 4xx MMU with software TLB */
	55	POWERPC_MMU_SOFT_4xx = 0x00000004,
	56	/* PowerPC 4xx MMU with software TLB and zones protections */
	57	POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
	58	/* PowerPC MMU in real mode only */
	59	POWERPC_MMU_REAL = 0x00000006,
	60	/* Freescale MPC8xx MMU model */
	61	POWERPC_MMU_MPC8xx = 0x00000007,
	62	/* BookE MMU model */
	63	POWERPC_MMU_BOOKE = 0x00000008,
	64	/* BookE 2.06 MMU model */
	65	POWERPC_MMU_BOOKE206 = 0x00000009,
	66	/* PowerPC 601 MMU model (specific BATs format) */
	67	POWERPC_MMU_601 = 0x0000000A,
	68	#define POWERPC_MMU_64 0x00010000
2d34fe39 PB	69	/* 64 bits PowerPC MMU */
	70	POWERPC_MMU_64B = POWERPC_MMU_64 \| 0x00000001,
	71	/* Architecture 2.03 and later (has LPCR) */
	72	POWERPC_MMU_2_03 = POWERPC_MMU_64 \| 0x00000002,
	73	/* Architecture 2.06 variant */
58969eee	74	POWERPC_MMU_2_06 = POWERPC_MMU_64 \| 0x00000003,
2d34fe39	75	/* Architecture 2.07 variant */
58969eee	76	POWERPC_MMU_2_07 = POWERPC_MMU_64 \| 0x00000004,
86cf1e9f	77	/* Architecture 3.00 variant */
ca79b3b7	78	POWERPC_MMU_3_00 = POWERPC_MMU_64 \| 0x00000005,
2d34fe39 PB	79	};
	80
	81	/*****************************************************************************/
	82	/* Exception model */
	83	typedef enum powerpc_excp_t powerpc_excp_t;
	84	enum powerpc_excp_t {
	85	POWERPC_EXCP_UNKNOWN = 0,
	86	/* Standard PowerPC exception model */
	87	POWERPC_EXCP_STD,
	88	/* PowerPC 40x exception model */
	89	POWERPC_EXCP_40x,
	90	/* PowerPC 601 exception model */
	91	POWERPC_EXCP_601,
	92	/* PowerPC 602 exception model */
	93	POWERPC_EXCP_602,
	94	/* PowerPC 603 exception model */
	95	POWERPC_EXCP_603,
	96	/* PowerPC 603e exception model */
	97	POWERPC_EXCP_603E,
	98	/* PowerPC G2 exception model */
	99	POWERPC_EXCP_G2,
	100	/* PowerPC 604 exception model */
	101	POWERPC_EXCP_604,
	102	/* PowerPC 7x0 exception model */
	103	POWERPC_EXCP_7x0,
	104	/* PowerPC 7x5 exception model */
	105	POWERPC_EXCP_7x5,
	106	/* PowerPC 74xx exception model */
	107	POWERPC_EXCP_74xx,
	108	/* BookE exception model */
	109	POWERPC_EXCP_BOOKE,
	110	/* PowerPC 970 exception model */
	111	POWERPC_EXCP_970,
	112	/* POWER7 exception model */
	113	POWERPC_EXCP_POWER7,
	114	/* POWER8 exception model */
	115	POWERPC_EXCP_POWER8,
a790e82b BH	116	/* POWER9 exception model */
a790e82b BH	117	POWERPC_EXCP_POWER9,
2d34fe39 PB	118	};
2d34fe39 PB	119
7778a575 BH	120	/*****************************************************************************/
	121	/* PM instructions */
	122	typedef enum {
	123	PPC_PM_DOZE,
	124	PPC_PM_NAP,
	125	PPC_PM_SLEEP,
	126	PPC_PM_RVWINKLE,
21c0d66a	127	PPC_PM_STOP,
7778a575 BH	128	} powerpc_pm_insn_t;
7778a575 BH	129
2d34fe39 PB	130	/*****************************************************************************/
	131	/* Input pins model */
	132	typedef enum powerpc_input_t powerpc_input_t;
	133	enum powerpc_input_t {
	134	PPC_FLAGS_INPUT_UNKNOWN = 0,
	135	/* PowerPC 6xx bus */
	136	PPC_FLAGS_INPUT_6xx,
	137	/* BookE bus */
	138	PPC_FLAGS_INPUT_BookE,
	139	/* PowerPC 405 bus */
	140	PPC_FLAGS_INPUT_405,
	141	/* PowerPC 970 bus */
	142	PPC_FLAGS_INPUT_970,
	143	/* PowerPC POWER7 bus */
	144	PPC_FLAGS_INPUT_POWER7,
67afe775 BH	145	/* PowerPC POWER9 bus */
67afe775 BH	146	PPC_FLAGS_INPUT_POWER9,
2d34fe39 PB	147	/* PowerPC 401 bus */
	148	PPC_FLAGS_INPUT_401,
	149	/* Freescale RCPU bus */
	150	PPC_FLAGS_INPUT_RCPU,
	151	};
	152
b07c59f7	153	typedef struct PPCHash64Options PPCHash64Options;
d0e39c5d	154
1d0cb67d AF	155	/**
1d0cb67d AF	156	* PowerPCCPUClass:
4776ce60	157	* @parent_realize: The parent class' realize handler.
1d0cb67d AF	158	* @parent_reset: The parent class' reset handler.
	159	*
	160	* A PowerPC CPU model.
	161	*/
	162	typedef struct PowerPCCPUClass {
	163	/< private >/
	164	CPUClass parent_class;
	165	/< public >/
	166
4776ce60	167	DeviceRealize parent_realize;
7bbc124e	168	DeviceUnrealize parent_unrealize;
1d0cb67d	169	void (parent_reset)(CPUState cpu);
b8e99967	170	void (parent_parse_features)(const char type, char str, Error *errp);
2985b86b	171
cfe34f44	172	uint32_t pvr;
03ae4133	173	bool (pvr_match)(struct PowerPCCPUClass pcc, uint32_t pvr);
8cd2ce7a TH	174	uint64_t pcr_mask; /* Available bits in PCR register */
8cd2ce7a TH	175	uint64_t pcr_supported; /* Bits for supported PowerISA versions */
cfe34f44 AF	176	uint32_t svr;
	177	uint64_t insns_flags;
	178	uint64_t insns_flags2;
	179	uint64_t msr_mask;
403aacdb	180	uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
cfe34f44 AF	181	powerpc_mmu_t mmu_model;
	182	powerpc_excp_t excp_model;
	183	powerpc_input_t bus_model;
	184	uint32_t flags;
	185	int bfd_mach;
0cbad81f	186	uint32_t l1_dcache_size, l1_icache_size;
707c7c2e FR	187	#ifndef CONFIG_USER_ONLY
	188	unsigned int gdb_num_sprs;
	189	const char *gdb_spr_xml;
	190	#endif
b07c59f7	191	const PPCHash64Options *hash64_opts;
c64abd1f	192	struct ppc_radix_page_info *radix_page_info;
a8dafa52	193	uint32_t lrg_decr_bits;
cfe34f44 AF	194	void (init_proc)(CPUPPCState env);
cfe34f44 AF	195	int (check_pow)(CPUPPCState env);
b2305601	196	int (handle_mmu_fault)(PowerPCCPU cpu, vaddr eaddr, int rwx, int mmu_idx);
382d2db6	197	bool (interrupts_big_endian)(PowerPCCPU cpu);
1d0cb67d AF	198	} PowerPCCPUClass;
1d0cb67d AF	199
a90db158	200	#ifndef CONFIG_USER_ONLY
98a8b524 AK	201	typedef struct PPCTimebase {
	202	uint64_t guest_timebase;
	203	int64_t time_of_the_day_ns;
	204	} PPCTimebase;
	205
	206	extern const struct VMStateDescription vmstate_ppc_timebase;
	207
	208	#define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \
	209	.name = (stringify(_field)), \
	210	.version_id = (_version), \
	211	.size = sizeof(PPCTimebase), \
	212	.vmsd = &vmstate_ppc_timebase, \
	213	.flags = VMS_STRUCT, \
	214	.offset = vmstate_offset_value(_state, _field, PPCTimebase), \
	215	}
42043e4f LV	216
	217	void cpu_ppc_clock_vm_state_change(void *opaque, int running,
	218	RunState state);
a90db158 AK	219	#endif
a90db158 AK	220
1d0cb67d	221	#endif