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Commit | Line | Data |
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cb9c377f PB |
1 | #ifndef HW_FLASH_H |
2 | #define HW_FLASH_H 1 | |
3 | ||
87ecb68b | 4 | /* NOR flash devices */ |
cfe5f011 | 5 | |
022c62cb | 6 | #include "exec/memory.h" |
cfe5f011 | 7 | |
c227f099 | 8 | typedef struct pflash_t pflash_t; |
87ecb68b | 9 | |
88eeee0a | 10 | /* pflash_cfi01.c */ |
a8170e5e | 11 | pflash_t *pflash_cfi01_register(hwaddr base, |
cfe5f011 | 12 | DeviceState *qdev, const char *name, |
a8170e5e | 13 | hwaddr size, |
88eeee0a AZ |
14 | BlockDriverState *bs, |
15 | uint32_t sector_len, int nb_blocs, int width, | |
16 | uint16_t id0, uint16_t id1, | |
01e0451a | 17 | uint16_t id2, uint16_t id3, int be); |
88eeee0a AZ |
18 | |
19 | /* pflash_cfi02.c */ | |
a8170e5e | 20 | pflash_t *pflash_cfi02_register(hwaddr base, |
cfe5f011 | 21 | DeviceState *qdev, const char *name, |
a8170e5e | 22 | hwaddr size, |
cf6d9118 | 23 | BlockDriverState *bs, uint32_t sector_len, |
4fbd24ba | 24 | int nb_blocs, int nb_mappings, int width, |
88eeee0a | 25 | uint16_t id0, uint16_t id1, |
6725070d | 26 | uint16_t id2, uint16_t id3, |
01e0451a AL |
27 | uint16_t unlock_addr0, uint16_t unlock_addr1, |
28 | int be); | |
87ecb68b | 29 | |
cfe5f011 AK |
30 | MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl); |
31 | ||
87ecb68b | 32 | /* nand.c */ |
d4220389 JR |
33 | DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id); |
34 | void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale, | |
51db57f7 | 35 | uint8_t ce, uint8_t wp, uint8_t gnd); |
d4220389 JR |
36 | void nand_getpins(DeviceState *dev, int *rb); |
37 | void nand_setio(DeviceState *dev, uint32_t value); | |
38 | uint32_t nand_getio(DeviceState *dev); | |
39 | uint32_t nand_getbuswidth(DeviceState *dev); | |
87ecb68b PB |
40 | |
41 | #define NAND_MFR_TOSHIBA 0x98 | |
42 | #define NAND_MFR_SAMSUNG 0xec | |
43 | #define NAND_MFR_FUJITSU 0x04 | |
44 | #define NAND_MFR_NATIONAL 0x8f | |
45 | #define NAND_MFR_RENESAS 0x07 | |
46 | #define NAND_MFR_STMICRO 0x20 | |
47 | #define NAND_MFR_HYNIX 0xad | |
48 | #define NAND_MFR_MICRON 0x2c | |
49 | ||
7e7c5e4c | 50 | /* onenand.c */ |
500954e3 | 51 | void *onenand_raw_otp(DeviceState *onenand_device); |
7e7c5e4c | 52 | |
87ecb68b | 53 | /* ecc.c */ |
bc24a225 | 54 | typedef struct { |
87ecb68b PB |
55 | uint8_t cp; /* Column parity */ |
56 | uint16_t lp[2]; /* Line parity */ | |
57 | uint16_t count; | |
bc24a225 | 58 | } ECCState; |
87ecb68b | 59 | |
bc24a225 PB |
60 | uint8_t ecc_digest(ECCState *s, uint8_t sample); |
61 | void ecc_reset(ECCState *s); | |
34f9f0b5 | 62 | extern VMStateDescription vmstate_ecc_state; |
cb9c377f PB |
63 | |
64 | #endif |