target/riscv: Add hfence instructions

[qemu.git] / target / riscv / insn16-64.decode

#
# RISC-V translation routines for the RVXI Base Integer Instruction Set.
#
# Copyright (c) 2018 Peer Adelt, [email protected]
#                    Bastian Koppelmann, [email protected]
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2 or later, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License along with
# this program.  If not, see <http://www.gnu.org/licenses/>.

# *** RV64C Standard Extension (Quadrant 0) ***
ld                011  ... ... .. ... 00 @cl_d
sd                111  ... ... .. ... 00 @cs_d

# *** RV64C Standard Extension (Quadrant 1) ***
{
  illegal         001 -  00000  ----- 01 # c.addiw, RES rd=0
  addiw           001 .  .....  ..... 01 @ci
}
subw              100 1 11 ... 00 ... 01 @cs_2
addw              100 1 11 ... 01 ... 01 @cs_2

# *** RV64C Standard Extension (Quadrant 2) ***
{
  illegal         011 -  00000  ----- 10 # c.ldsp, RES rd=0
  ld              011 .  .....  ..... 10 @c_ldsp
}
sd                111 .  .....  ..... 10 @c_sdsp