[qemu.git] / hw / misc / edu.c

/*
 * QEMU educational PCI device
 *
 * Copyright (c) 2012-2015 Jiri Slaby
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "hw/pci/pci.h"
#include "hw/hw.h"
#include "hw/pci/msi.h"
#include "qemu/timer.h"
#include "qemu/main-loop.h" /* iothread mutex */
#include "qemu/module.h"
#include "qapi/visitor.h"

#define TYPE_PCI_EDU_DEVICE "edu"
#define EDU(obj)        OBJECT_CHECK(EduState, obj, TYPE_PCI_EDU_DEVICE)

#define FACT_IRQ        0x00000001
#define DMA_IRQ         0x00000100

#define DMA_START       0x40000
#define DMA_SIZE        4096

typedef struct {
    PCIDevice pdev;
    MemoryRegion mmio;

    QemuThread thread;
    QemuMutex thr_mutex;
    QemuCond thr_cond;
    bool stopping;

    uint32_t addr4;
    uint32_t fact;
#define EDU_STATUS_COMPUTING    0x01
#define EDU_STATUS_IRQFACT      0x80
    uint32_t status;

    uint32_t irq_status;

#define EDU_DMA_RUN             0x1
#define EDU_DMA_DIR(cmd)        (((cmd) & 0x2) >> 1)
# define EDU_DMA_FROM_PCI       0
# define EDU_DMA_TO_PCI         1
#define EDU_DMA_IRQ             0x4
    struct dma_state {
        dma_addr_t src;
        dma_addr_t dst;
        dma_addr_t cnt;
        dma_addr_t cmd;
    } dma;
    QEMUTimer dma_timer;
    char dma_buf[DMA_SIZE];
    uint64_t dma_mask;
} EduState;

static bool edu_msi_enabled(EduState *edu)
{
    return msi_enabled(&edu->pdev);
}

static void edu_raise_irq(EduState *edu, uint32_t val)
{
    edu->irq_status |= val;
    if (edu->irq_status) {
        if (edu_msi_enabled(edu)) {
            msi_notify(&edu->pdev, 0);
        } else {
            pci_set_irq(&edu->pdev, 1);
        }
    }
}

static void edu_lower_irq(EduState *edu, uint32_t val)
{
    edu->irq_status &= ~val;

    if (!edu->irq_status && !edu_msi_enabled(edu)) {
        pci_set_irq(&edu->pdev, 0);
    }
}

static bool within(uint64_t addr, uint64_t start, uint64_t end)
{
    return start <= addr && addr < end;
}

static void edu_check_range(uint64_t addr, uint64_t size1, uint64_t start,
                uint64_t size2)
{
    uint64_t end1 = addr + size1;
    uint64_t end2 = start + size2;

    if (within(addr, start, end2) &&
            end1 > addr && within(end1, start, end2)) {
        return;
    }

    hw_error("EDU: DMA range 0x%016"PRIx64"-0x%016"PRIx64
             " out of bounds (0x%016"PRIx64"-0x%016"PRIx64")!",
            addr, end1 - 1, start, end2 - 1);
}

static dma_addr_t edu_clamp_addr(const EduState *edu, dma_addr_t addr)
{
    dma_addr_t res = addr & edu->dma_mask;

    if (addr != res) {
        printf("EDU: clamping DMA %#.16"PRIx64" to %#.16"PRIx64"!\n", addr, res);
    }

    return res;
}

static void edu_dma_timer(void *opaque)
{
    EduState *edu = opaque;
    bool raise_irq = false;

    if (!(edu->dma.cmd & EDU_DMA_RUN)) {
        return;
    }

    if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) {
        uint64_t dst = edu->dma.dst;
        edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE);
        dst -= DMA_START;
        pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src),
                edu->dma_buf + dst, edu->dma.cnt);
    } else {
        uint64_t src = edu->dma.src;
        edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE);
        src -= DMA_START;
        pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst),
                edu->dma_buf + src, edu->dma.cnt);
    }

    edu->dma.cmd &= ~EDU_DMA_RUN;
    if (edu->dma.cmd & EDU_DMA_IRQ) {
        raise_irq = true;
    }

    if (raise_irq) {
        edu_raise_irq(edu, DMA_IRQ);
    }
}

static void dma_rw(EduState *edu, bool write, dma_addr_t *val, dma_addr_t *dma,
                bool timer)
{
    if (write && (edu->dma.cmd & EDU_DMA_RUN)) {
        return;
    }

    if (write) {
        *dma = *val;
    } else {
        *val = *dma;
    }

    if (timer) {
        timer_mod(&edu->dma_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100);
    }
}

static uint64_t edu_mmio_read(void *opaque, hwaddr addr, unsigned size)
{
    EduState *edu = opaque;
    uint64_t val = ~0ULL;

    if (addr < 0x80 && size != 4) {
        return val;
    }

    if (addr >= 0x80 && size != 4 && size != 8) {
        return val;
    }

    switch (addr) {
    case 0x00:
        val = 0x010000edu;
        break;
    case 0x04:
        val = edu->addr4;
        break;
    case 0x08:
        qemu_mutex_lock(&edu->thr_mutex);
        val = edu->fact;
        qemu_mutex_unlock(&edu->thr_mutex);
        break;
    case 0x20:
        val = atomic_read(&edu->status);
        break;
    case 0x24:
        val = edu->irq_status;
        break;
    case 0x80:
        dma_rw(edu, false, &val, &edu->dma.src, false);
        break;
    case 0x88:
        dma_rw(edu, false, &val, &edu->dma.dst, false);
        break;
    case 0x90:
        dma_rw(edu, false, &val, &edu->dma.cnt, false);
        break;
    case 0x98:
        dma_rw(edu, false, &val, &edu->dma.cmd, false);
        break;
    }

    return val;
}

static void edu_mmio_write(void *opaque, hwaddr addr, uint64_t val,
                unsigned size)
{
    EduState *edu = opaque;

    if (addr < 0x80 && size != 4) {
        return;
    }

    if (addr >= 0x80 && size != 4 && size != 8) {
        return;
    }

    switch (addr) {
    case 0x04:
        edu->addr4 = ~val;
        break;
    case 0x08:
        if (atomic_read(&edu->status) & EDU_STATUS_COMPUTING) {
            break;
        }
        /* EDU_STATUS_COMPUTING cannot go 0->1 concurrently, because it is only
         * set in this function and it is under the iothread mutex.
         */
        qemu_mutex_lock(&edu->thr_mutex);
        edu->fact = val;
        atomic_or(&edu->status, EDU_STATUS_COMPUTING);
        qemu_cond_signal(&edu->thr_cond);
        qemu_mutex_unlock(&edu->thr_mutex);
        break;
    case 0x20:
        if (val & EDU_STATUS_IRQFACT) {
            atomic_or(&edu->status, EDU_STATUS_IRQFACT);
        } else {
            atomic_and(&edu->status, ~EDU_STATUS_IRQFACT);
        }
        break;
    case 0x60:
        edu_raise_irq(edu, val);
        break;
    case 0x64:
        edu_lower_irq(edu, val);
        break;
    case 0x80:
        dma_rw(edu, true, &val, &edu->dma.src, false);
        break;
    case 0x88:
        dma_rw(edu, true, &val, &edu->dma.dst, false);
        break;
    case 0x90:
        dma_rw(edu, true, &val, &edu->dma.cnt, false);
        break;
    case 0x98:
        if (!(val & EDU_DMA_RUN)) {
            break;
        }
        dma_rw(edu, true, &val, &edu->dma.cmd, true);
        break;
    }
}

static const MemoryRegionOps edu_mmio_ops = {
    .read = edu_mmio_read,
    .write = edu_mmio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 8,
    },
    .impl = {
        .min_access_size = 4,
        .max_access_size = 8,
    },

};

/*
 * We purposely use a thread, so that users are forced to wait for the status
 * register.
 */
static void *edu_fact_thread(void *opaque)
{
    EduState *edu = opaque;

    while (1) {
        uint32_t val, ret = 1;

        qemu_mutex_lock(&edu->thr_mutex);
        while ((atomic_read(&edu->status) & EDU_STATUS_COMPUTING) == 0 &&
                        !edu->stopping) {
            qemu_cond_wait(&edu->thr_cond, &edu->thr_mutex);
        }

        if (edu->stopping) {
            qemu_mutex_unlock(&edu->thr_mutex);
            break;
        }

        val = edu->fact;
        qemu_mutex_unlock(&edu->thr_mutex);

        while (val > 0) {
            ret *= val--;
        }

        /*
         * We should sleep for a random period here, so that students are
         * forced to check the status properly.
         */

        qemu_mutex_lock(&edu->thr_mutex);
        edu->fact = ret;
        qemu_mutex_unlock(&edu->thr_mutex);
        atomic_and(&edu->status, ~EDU_STATUS_COMPUTING);

        if (atomic_read(&edu->status) & EDU_STATUS_IRQFACT) {
            qemu_mutex_lock_iothread();
            edu_raise_irq(edu, FACT_IRQ);
            qemu_mutex_unlock_iothread();
        }
    }

    return NULL;
}

static void pci_edu_realize(PCIDevice *pdev, Error **errp)
{
    EduState *edu = EDU(pdev);
    uint8_t *pci_conf = pdev->config;

    pci_config_set_interrupt_pin(pci_conf, 1);

    if (msi_init(pdev, 0, 1, true, false, errp)) {
        return;
    }

    timer_init_ms(&edu->dma_timer, QEMU_CLOCK_VIRTUAL, edu_dma_timer, edu);

    qemu_mutex_init(&edu->thr_mutex);
    qemu_cond_init(&edu->thr_cond);
    qemu_thread_create(&edu->thread, "edu", edu_fact_thread,
                       edu, QEMU_THREAD_JOINABLE);

    memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
                    "edu-mmio", 1 * MiB);
    pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);
}

static void pci_edu_uninit(PCIDevice *pdev)
{
    EduState *edu = EDU(pdev);

    qemu_mutex_lock(&edu->thr_mutex);
    edu->stopping = true;
    qemu_mutex_unlock(&edu->thr_mutex);
    qemu_cond_signal(&edu->thr_cond);
    qemu_thread_join(&edu->thread);

    qemu_cond_destroy(&edu->thr_cond);
    qemu_mutex_destroy(&edu->thr_mutex);

    timer_del(&edu->dma_timer);
    msi_uninit(pdev);
}

static void edu_obj_uint64(Object *obj, Visitor *v, const char *name,
                           void *opaque, Error **errp)
{
    uint64_t *val = opaque;

    visit_type_uint64(v, name, val, errp);
}

static void edu_instance_init(Object *obj)
{
    EduState *edu = EDU(obj);

    edu->dma_mask = (1UL << 28) - 1;
    object_property_add(obj, "dma_mask", "uint64", edu_obj_uint64,
                    edu_obj_uint64, NULL, &edu->dma_mask, NULL);
}

static void edu_class_init(ObjectClass *class, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(class);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(class);

    k->realize = pci_edu_realize;
    k->exit = pci_edu_uninit;
    k->vendor_id = PCI_VENDOR_ID_QEMU;
    k->device_id = 0x11e8;
    k->revision = 0x10;
    k->class_id = PCI_CLASS_OTHERS;
    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
}

static void pci_edu_register_types(void)
{
    static InterfaceInfo interfaces[] = {
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
        { },
    };
    static const TypeInfo edu_info = {
        .name          = TYPE_PCI_EDU_DEVICE,
        .parent        = TYPE_PCI_DEVICE,
        .instance_size = sizeof(EduState),
        .instance_init = edu_instance_init,
        .class_init    = edu_class_init,
        .interfaces = interfaces,
    };

    type_register_static(&edu_info);
}
type_init(pci_edu_register_types)
Commit	Line	Data
b30934cb JS	1	/*
	2	* QEMU educational PCI device
	3	*
	4	* Copyright (c) 2012-2015 Jiri Slaby
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	19	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*/
	24
0d1c9782	25	#include "qemu/osdep.h"
de9b602e	26	#include "qemu/units.h"
b30934cb	27	#include "hw/pci/pci.h"
650d103d	28	#include "hw/hw.h"
eabb5782	29	#include "hw/pci/msi.h"
b30934cb JS	30	#include "qemu/timer.h"
b30934cb JS	31	#include "qemu/main-loop.h" /* iothread mutex */
0b8fa32f	32	#include "qemu/module.h"
b30934cb JS	33	#include "qapi/visitor.h"
b30934cb JS	34
8371158b LQ	35	#define TYPE_PCI_EDU_DEVICE "edu"
8371158b LQ	36	#define EDU(obj) OBJECT_CHECK(EduState, obj, TYPE_PCI_EDU_DEVICE)
b30934cb JS	37
	38	#define FACT_IRQ 0x00000001
	39	#define DMA_IRQ 0x00000100
	40
	41	#define DMA_START 0x40000
	42	#define DMA_SIZE 4096
	43
	44	typedef struct {
	45	PCIDevice pdev;
	46	MemoryRegion mmio;
	47
	48	QemuThread thread;
	49	QemuMutex thr_mutex;
	50	QemuCond thr_cond;
	51	bool stopping;
	52
	53	uint32_t addr4;
	54	uint32_t fact;
	55	#define EDU_STATUS_COMPUTING 0x01
	56	#define EDU_STATUS_IRQFACT 0x80
	57	uint32_t status;
	58
	59	uint32_t irq_status;
	60
	61	#define EDU_DMA_RUN 0x1
	62	#define EDU_DMA_DIR(cmd) (((cmd) & 0x2) >> 1)
	63	# define EDU_DMA_FROM_PCI 0
	64	# define EDU_DMA_TO_PCI 1
	65	#define EDU_DMA_IRQ 0x4
	66	struct dma_state {
	67	dma_addr_t src;
	68	dma_addr_t dst;
	69	dma_addr_t cnt;
	70	dma_addr_t cmd;
	71	} dma;
	72	QEMUTimer dma_timer;
	73	char dma_buf[DMA_SIZE];
	74	uint64_t dma_mask;
	75	} EduState;
	76
eabb5782 PX	77	static bool edu_msi_enabled(EduState *edu)
	78	{
	79	return msi_enabled(&edu->pdev);
	80	}
	81
b30934cb JS	82	static void edu_raise_irq(EduState *edu, uint32_t val)
	83	{
	84	edu->irq_status \|= val;
	85	if (edu->irq_status) {
eabb5782 PX	86	if (edu_msi_enabled(edu)) {
	87	msi_notify(&edu->pdev, 0);
	88	} else {
	89	pci_set_irq(&edu->pdev, 1);
	90	}
b30934cb JS	91	}
	92	}
	93
	94	static void edu_lower_irq(EduState *edu, uint32_t val)
	95	{
	96	edu->irq_status &= ~val;
	97
eabb5782	98	if (!edu->irq_status && !edu_msi_enabled(edu)) {
b30934cb JS	99	pci_set_irq(&edu->pdev, 0);
	100	}
	101	}
	102
7fca21c8	103	static bool within(uint64_t addr, uint64_t start, uint64_t end)
b30934cb JS	104	{
	105	return start <= addr && addr < end;
	106	}
	107
7fca21c8 LQ	108	static void edu_check_range(uint64_t addr, uint64_t size1, uint64_t start,
7fca21c8 LQ	109	uint64_t size2)
b30934cb	110	{
7fca21c8 LQ	111	uint64_t end1 = addr + size1;
7fca21c8 LQ	112	uint64_t end2 = start + size2;
b30934cb JS	113
	114	if (within(addr, start, end2) &&
	115	end1 > addr && within(end1, start, end2)) {
	116	return;
	117	}
	118
7fca21c8 LQ	119	hw_error("EDU: DMA range 0x%016"PRIx64"-0x%016"PRIx64
7fca21c8 LQ	120	" out of bounds (0x%016"PRIx64"-0x%016"PRIx64")!",
b30934cb JS	121	addr, end1 - 1, start, end2 - 1);
	122	}
	123
	124	static dma_addr_t edu_clamp_addr(const EduState *edu, dma_addr_t addr)
	125	{
	126	dma_addr_t res = addr & edu->dma_mask;
	127
	128	if (addr != res) {
	129	printf("EDU: clamping DMA %#.16"PRIx64" to %#.16"PRIx64"!\n", addr, res);
	130	}
	131
	132	return res;
	133	}
	134
	135	static void edu_dma_timer(void *opaque)
	136	{
	137	EduState *edu = opaque;
	138	bool raise_irq = false;
	139
	140	if (!(edu->dma.cmd & EDU_DMA_RUN)) {
	141	return;
	142	}
	143
	144	if (EDU_DMA_DIR(edu->dma.cmd) == EDU_DMA_FROM_PCI) {
7fca21c8	145	uint64_t dst = edu->dma.dst;
b30934cb JS	146	edu_check_range(dst, edu->dma.cnt, DMA_START, DMA_SIZE);
	147	dst -= DMA_START;
	148	pci_dma_read(&edu->pdev, edu_clamp_addr(edu, edu->dma.src),
	149	edu->dma_buf + dst, edu->dma.cnt);
	150	} else {
7fca21c8	151	uint64_t src = edu->dma.src;
b30934cb JS	152	edu_check_range(src, edu->dma.cnt, DMA_START, DMA_SIZE);
	153	src -= DMA_START;
	154	pci_dma_write(&edu->pdev, edu_clamp_addr(edu, edu->dma.dst),
	155	edu->dma_buf + src, edu->dma.cnt);
	156	}
	157
	158	edu->dma.cmd &= ~EDU_DMA_RUN;
	159	if (edu->dma.cmd & EDU_DMA_IRQ) {
	160	raise_irq = true;
	161	}
	162
	163	if (raise_irq) {
	164	edu_raise_irq(edu, DMA_IRQ);
	165	}
	166	}
	167
	168	static void dma_rw(EduState edu, bool write, dma_addr_t val, dma_addr_t *dma,
	169	bool timer)
	170	{
	171	if (write && (edu->dma.cmd & EDU_DMA_RUN)) {
	172	return;
	173	}
	174
	175	if (write) {
	176	dma = val;
	177	} else {
	178	val = dma;
	179	}
	180
	181	if (timer) {
	182	timer_mod(&edu->dma_timer, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100);
	183	}
	184	}
	185
	186	static uint64_t edu_mmio_read(void *opaque, hwaddr addr, unsigned size)
	187	{
	188	EduState *edu = opaque;
	189	uint64_t val = ~0ULL;
	190
c45eb53a LQ	191	if (addr < 0x80 && size != 4) {
	192	return val;
	193	}
	194
	195	if (addr >= 0x80 && size != 4 && size != 8) {
b30934cb JS	196	return val;
	197	}
	198
	199	switch (addr) {
	200	case 0x00:
	201	val = 0x010000edu;
	202	break;
	203	case 0x04:
	204	val = edu->addr4;
	205	break;
	206	case 0x08:
	207	qemu_mutex_lock(&edu->thr_mutex);
	208	val = edu->fact;
	209	qemu_mutex_unlock(&edu->thr_mutex);
	210	break;
	211	case 0x20:
	212	val = atomic_read(&edu->status);
	213	break;
	214	case 0x24:
	215	val = edu->irq_status;
	216	break;
	217	case 0x80:
	218	dma_rw(edu, false, &val, &edu->dma.src, false);
	219	break;
	220	case 0x88:
	221	dma_rw(edu, false, &val, &edu->dma.dst, false);
	222	break;
	223	case 0x90:
	224	dma_rw(edu, false, &val, &edu->dma.cnt, false);
	225	break;
	226	case 0x98:
	227	dma_rw(edu, false, &val, &edu->dma.cmd, false);
	228	break;
	229	}
	230
	231	return val;
	232	}
	233
	234	static void edu_mmio_write(void *opaque, hwaddr addr, uint64_t val,
	235	unsigned size)
	236	{
	237	EduState *edu = opaque;
	238
	239	if (addr < 0x80 && size != 4) {
	240	return;
	241	}
	242
	243	if (addr >= 0x80 && size != 4 && size != 8) {
	244	return;
	245	}
	246
	247	switch (addr) {
	248	case 0x04:
	249	edu->addr4 = ~val;
	250	break;
	251	case 0x08:
	252	if (atomic_read(&edu->status) & EDU_STATUS_COMPUTING) {
	253	break;
	254	}
	255	/* EDU_STATUS_COMPUTING cannot go 0->1 concurrently, because it is only
	256	* set in this function and it is under the iothread mutex.
	257	*/
	258	qemu_mutex_lock(&edu->thr_mutex);
	259	edu->fact = val;
260	atomic_or(&edu->status, EDU_STATUS_COMPUTING);
261	qemu_cond_signal(&edu->thr_cond);
262	qemu_mutex_unlock(&edu->thr_mutex);
263	break;
264	case 0x20:
265	if (val & EDU_STATUS_IRQFACT) {
266	atomic_or(&edu->status, EDU_STATUS_IRQFACT);
267	} else {
268	atomic_and(&edu->status, ~EDU_STATUS_IRQFACT);
269	}
270	break;
271	case 0x60:
272	edu_raise_irq(edu, val);
273	break;
274	case 0x64:
275	edu_lower_irq(edu, val);
276	break;
277	case 0x80:
278	dma_rw(edu, true, &val, &edu->dma.src, false);
279	break;
280	case 0x88:
281	dma_rw(edu, true, &val, &edu->dma.dst, false);
282	break;
283	case 0x90:
284	dma_rw(edu, true, &val, &edu->dma.cnt, false);
285	break;
286	case 0x98:
287	if (!(val & EDU_DMA_RUN)) {
288	break;
289	}
290	dma_rw(edu, true, &val, &edu->dma.cmd, true);
291	break;
292	}
293	}
294
295	static const MemoryRegionOps edu_mmio_ops = {
296	.read = edu_mmio_read,
297	.write = edu_mmio_write,
298	.endianness = DEVICE_NATIVE_ENDIAN,
20fb3105 LQ	299	.valid = {
	300	.min_access_size = 4,
	301	.max_access_size = 8,
	302	},
	303	.impl = {
	304	.min_access_size = 4,
	305	.max_access_size = 8,
	306	},
	307
b30934cb JS	308	};
	309
	310	/*
631b22ea	311	* We purposely use a thread, so that users are forced to wait for the status
b30934cb JS	312	* register.
	313	*/
	314	static void edu_fact_thread(void opaque)
	315	{
	316	EduState *edu = opaque;
	317
	318	while (1) {
	319	uint32_t val, ret = 1;
	320
	321	qemu_mutex_lock(&edu->thr_mutex);
	322	while ((atomic_read(&edu->status) & EDU_STATUS_COMPUTING) == 0 &&
	323	!edu->stopping) {
	324	qemu_cond_wait(&edu->thr_cond, &edu->thr_mutex);
	325	}
	326
	327	if (edu->stopping) {
	328	qemu_mutex_unlock(&edu->thr_mutex);
	329	break;
	330	}
	331
	332	val = edu->fact;
	333	qemu_mutex_unlock(&edu->thr_mutex);
	334
	335	while (val > 0) {
	336	ret *= val--;
	337	}
	338
	339	/*
	340	* We should sleep for a random period here, so that students are
	341	* forced to check the status properly.
	342	*/
	343
	344	qemu_mutex_lock(&edu->thr_mutex);
	345	edu->fact = ret;
	346	qemu_mutex_unlock(&edu->thr_mutex);
	347	atomic_and(&edu->status, ~EDU_STATUS_COMPUTING);
	348
	349	if (atomic_read(&edu->status) & EDU_STATUS_IRQFACT) {
	350	qemu_mutex_lock_iothread();
	351	edu_raise_irq(edu, FACT_IRQ);
	352	qemu_mutex_unlock_iothread();
	353	}
	354	}
	355
	356	return NULL;
	357	}
	358
f922254c	359	static void pci_edu_realize(PCIDevice pdev, Error *errp)
b30934cb	360	{
a519e389	361	EduState *edu = EDU(pdev);
b30934cb JS	362	uint8_t *pci_conf = pdev->config;
b30934cb JS	363
c25a67f0 PB	364	pci_config_set_interrupt_pin(pci_conf, 1);
	365
	366	if (msi_init(pdev, 0, 1, true, false, errp)) {
	367	return;
	368	}
	369
b30934cb JS	370	timer_init_ms(&edu->dma_timer, QEMU_CLOCK_VIRTUAL, edu_dma_timer, edu);
	371
	372	qemu_mutex_init(&edu->thr_mutex);
	373	qemu_cond_init(&edu->thr_cond);
	374	qemu_thread_create(&edu->thread, "edu", edu_fact_thread,
	375	edu, QEMU_THREAD_JOINABLE);
	376
b30934cb	377	memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu,
de9b602e	378	"edu-mmio", 1 * MiB);
b30934cb	379	pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio);
b30934cb JS	380	}
	381
	382	static void pci_edu_uninit(PCIDevice *pdev)
	383	{
a519e389	384	EduState *edu = EDU(pdev);
b30934cb JS	385
	386	qemu_mutex_lock(&edu->thr_mutex);
	387	edu->stopping = true;
	388	qemu_mutex_unlock(&edu->thr_mutex);
	389	qemu_cond_signal(&edu->thr_cond);
	390	qemu_thread_join(&edu->thread);
	391
	392	qemu_cond_destroy(&edu->thr_cond);
	393	qemu_mutex_destroy(&edu->thr_mutex);
	394
	395	timer_del(&edu->dma_timer);
812e710a	396	msi_uninit(pdev);
b30934cb JS	397	}
b30934cb JS	398
d7bce999 EB	399	static void edu_obj_uint64(Object obj, Visitor v, const char *name,
d7bce999 EB	400	void opaque, Error *errp)
b30934cb JS	401	{
	402	uint64_t *val = opaque;
	403
51e72bc1	404	visit_type_uint64(v, name, val, errp);
b30934cb JS	405	}
	406
	407	static void edu_instance_init(Object *obj)
	408	{
	409	EduState *edu = EDU(obj);
	410
	411	edu->dma_mask = (1UL << 28) - 1;
	412	object_property_add(obj, "dma_mask", "uint64", edu_obj_uint64,
	413	edu_obj_uint64, NULL, &edu->dma_mask, NULL);
	414	}
	415
	416	static void edu_class_init(ObjectClass class, void data)
	417	{
aae04907	418	DeviceClass *dc = DEVICE_CLASS(class);
b30934cb JS	419	PCIDeviceClass *k = PCI_DEVICE_CLASS(class);
b30934cb JS	420
f922254c	421	k->realize = pci_edu_realize;
b30934cb JS	422	k->exit = pci_edu_uninit;
	423	k->vendor_id = PCI_VENDOR_ID_QEMU;
	424	k->device_id = 0x11e8;
	425	k->revision = 0x10;
	426	k->class_id = PCI_CLASS_OTHERS;
aae04907	427	set_bit(DEVICE_CATEGORY_MISC, dc->categories);
b30934cb JS	428	}
	429
	430	static void pci_edu_register_types(void)
	431	{
fd3b02c8 EH	432	static InterfaceInfo interfaces[] = {
	433	{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
	434	{ },
	435	};
b30934cb	436	static const TypeInfo edu_info = {
8371158b	437	.name = TYPE_PCI_EDU_DEVICE,
b30934cb JS	438	.parent = TYPE_PCI_DEVICE,
	439	.instance_size = sizeof(EduState),
	440	.instance_init = edu_instance_init,
	441	.class_init = edu_class_init,
fd3b02c8	442	.interfaces = interfaces,
b30934cb JS	443	};
	444
	445	type_register_static(&edu_info);
	446	}
	447	type_init(pci_edu_register_types)