[qemu.git] / hw / ppc / pnv_core.c

/*
 * QEMU PowerPC PowerNV CPU Core model
 *
 * Copyright (c) 2016, IBM Corporation.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public License
 * as published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/osdep.h"
#include "sysemu/sysemu.h"
#include "qapi/error.h"
#include "qemu/log.h"
#include "target/ppc/cpu.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/ppc/xics.h"

static const char *pnv_core_cpu_typename(PnvCore *pc)
{
    const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
    int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
    char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
    const char *cpu_type = object_class_get_name(object_class_by_name(s));
    g_free(s);
    return cpu_type;
}

static void pnv_cpu_reset(void *opaque)
{
    PowerPCCPU *cpu = opaque;
    CPUState *cs = CPU(cpu);
    CPUPPCState *env = &cpu->env;

    cpu_reset(cs);

    /*
     * the skiboot firmware elects a primary thread to initialize the
     * system and it can be any.
     */
    env->gpr[3] = PNV_FDT_ADDR;
    env->nip = 0x10;
    env->msr |= MSR_HVB; /* Hypervisor mode */
}

/*
 * These values are read by the PowerNV HW monitors under Linux
 */
#define PNV_XSCOM_EX_DTS_RESULT0     0x50000
#define PNV_XSCOM_EX_DTS_RESULT1     0x50001

static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr,
                                           unsigned int width)
{
    uint32_t offset = addr >> 3;
    uint64_t val = 0;

    /* The result should be 38 C */
    switch (offset) {
    case PNV_XSCOM_EX_DTS_RESULT0:
        val = 0x26f024f023f0000ull;
        break;
    case PNV_XSCOM_EX_DTS_RESULT1:
        val = 0x24f000000000000ull;
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
                  addr);
    }

    return val;
}

static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val,
                                        unsigned int width)
{
    qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
                  addr);
}

static const MemoryRegionOps pnv_core_power8_xscom_ops = {
    .read = pnv_core_power8_xscom_read,
    .write = pnv_core_power8_xscom_write,
    .valid.min_access_size = 8,
    .valid.max_access_size = 8,
    .impl.min_access_size = 8,
    .impl.max_access_size = 8,
    .endianness = DEVICE_BIG_ENDIAN,
};


/*
 * POWER9 core controls
 */
#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a

static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
                                           unsigned int width)
{
    uint32_t offset = addr >> 3;
    uint64_t val = 0;

    /* The result should be 38 C */
    switch (offset) {
    case PNV_XSCOM_EX_DTS_RESULT0:
        val = 0x26f024f023f0000ull;
        break;
    case PNV_XSCOM_EX_DTS_RESULT1:
        val = 0x24f000000000000ull;
        break;
    case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
    case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
        val = 0x0;
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
                  addr);
    }

    return val;
}

static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
                                        unsigned int width)
{
    uint32_t offset = addr >> 3;

    switch (offset) {
    case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
    case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
                      addr);
    }
}

static const MemoryRegionOps pnv_core_power9_xscom_ops = {
    .read = pnv_core_power9_xscom_read,
    .write = pnv_core_power9_xscom_write,
    .valid.min_access_size = 8,
    .valid.max_access_size = 8,
    .impl.min_access_size = 8,
    .impl.max_access_size = 8,
    .endianness = DEVICE_BIG_ENDIAN,
};

static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp)
{
    CPUPPCState *env = &cpu->env;
    int core_pir;
    int thread_index = 0; /* TODO: TCG supports only one thread */
    ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
    Error *local_err = NULL;
    PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);

    object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    pcc->intc_create(chip, cpu, &local_err);
    if (local_err) {
        error_propagate(errp, local_err);
        return;
    }

    core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);

    /*
     * The PIR of a thread is the core PIR + the thread index. We will
     * need to find a way to get the thread index when TCG supports
     * more than 1. We could use the object name ?
     */
    pir->default_value = core_pir + thread_index;

    /* Set time-base frequency to 512 MHz */
    cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);

    qemu_register_reset(pnv_cpu_reset, cpu);
}

static void pnv_core_realize(DeviceState *dev, Error **errp)
{
    PnvCore *pc = PNV_CORE(OBJECT(dev));
    PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
    CPUCore *cc = CPU_CORE(OBJECT(dev));
    const char *typename = pnv_core_cpu_typename(pc);
    Error *local_err = NULL;
    void *obj;
    int i, j;
    char name[32];
    Object *chip;

    chip = object_property_get_link(OBJECT(dev), "chip", &local_err);
    if (!chip) {
        error_propagate_prepend(errp, local_err,
                                "required link 'chip' not found: ");
        return;
    }

    pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
    for (i = 0; i < cc->nr_threads; i++) {
        PowerPCCPU *cpu;

        obj = object_new(typename);
        cpu = POWERPC_CPU(obj);

        pc->threads[i] = POWERPC_CPU(obj);

        snprintf(name, sizeof(name), "thread[%d]", i);
        object_property_add_child(OBJECT(pc), name, obj, &error_abort);
        object_property_add_alias(obj, "core-pir", OBJECT(pc),
                                  "pir", &error_abort);

        cpu->machine_data = g_new0(PnvCPUState, 1);

        object_unref(obj);
    }

    for (j = 0; j < cc->nr_threads; j++) {
        pnv_realize_vcpu(pc->threads[j], PNV_CHIP(chip), &local_err);
        if (local_err) {
            goto err;
        }
    }

    snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
    pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
                          pc, name, PNV_XSCOM_EX_SIZE);
    return;

err:
    while (--i >= 0) {
        obj = OBJECT(pc->threads[i]);
        object_unparent(obj);
    }
    g_free(pc->threads);
    error_propagate(errp, local_err);
}

static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
{
    PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);

    qemu_unregister_reset(pnv_cpu_reset, cpu);
    object_unparent(OBJECT(pnv_cpu_state(cpu)->intc));
    cpu_remove_sync(CPU(cpu));
    cpu->machine_data = NULL;
    g_free(pnv_cpu);
    object_unparent(OBJECT(cpu));
}

static void pnv_core_unrealize(DeviceState *dev, Error **errp)
{
    PnvCore *pc = PNV_CORE(dev);
    CPUCore *cc = CPU_CORE(dev);
    int i;

    for (i = 0; i < cc->nr_threads; i++) {
        pnv_unrealize_vcpu(pc->threads[i]);
    }
    g_free(pc->threads);
}

static Property pnv_core_properties[] = {
    DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void pnv_core_power8_class_init(ObjectClass *oc, void *data)
{
    PnvCoreClass *pcc = PNV_CORE_CLASS(oc);

    pcc->xscom_ops = &pnv_core_power8_xscom_ops;
}

static void pnv_core_power9_class_init(ObjectClass *oc, void *data)
{
    PnvCoreClass *pcc = PNV_CORE_CLASS(oc);

    pcc->xscom_ops = &pnv_core_power9_xscom_ops;
}

static void pnv_core_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = pnv_core_realize;
    dc->unrealize = pnv_core_unrealize;
    dc->props = pnv_core_properties;
}

#define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
    {                                           \
        .parent = TYPE_PNV_CORE,                \
        .name = PNV_CORE_TYPE_NAME(cpu_model),  \
        .class_init = pnv_core_##family##_class_init, \
    }

static const TypeInfo pnv_core_infos[] = {
    {
        .name           = TYPE_PNV_CORE,
        .parent         = TYPE_CPU_CORE,
        .instance_size  = sizeof(PnvCore),
        .class_size     = sizeof(PnvCoreClass),
        .class_init = pnv_core_class_init,
        .abstract       = true,
    },
    DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
    DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
    DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
    DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
};

DEFINE_TYPES(pnv_core_infos)

/*
 * POWER9 Quads
 */

#define P9X_EX_NCU_SPEC_BAR                     0x11010

static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
                                    unsigned int width)
{
    uint32_t offset = addr >> 3;
    uint64_t val = -1;

    switch (offset) {
    case P9X_EX_NCU_SPEC_BAR:
    case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
        val = 0;
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
                      offset);
    }

    return val;
}

static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
                                 unsigned int width)
{
    uint32_t offset = addr >> 3;

    switch (offset) {
    case P9X_EX_NCU_SPEC_BAR:
    case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
        break;
    default:
        qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
                  offset);
    }
}

static const MemoryRegionOps pnv_quad_xscom_ops = {
    .read = pnv_quad_xscom_read,
    .write = pnv_quad_xscom_write,
    .valid.min_access_size = 8,
    .valid.max_access_size = 8,
    .impl.min_access_size = 8,
    .impl.max_access_size = 8,
    .endianness = DEVICE_BIG_ENDIAN,
};

static void pnv_quad_realize(DeviceState *dev, Error **errp)
{
    PnvQuad *eq = PNV_QUAD(dev);
    char name[32];

    snprintf(name, sizeof(name), "xscom-quad.%d", eq->id);
    pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
                          eq, name, PNV9_XSCOM_EQ_SIZE);
}

static Property pnv_quad_properties[] = {
    DEFINE_PROP_UINT32("id", PnvQuad, id, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void pnv_quad_class_init(ObjectClass *oc, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(oc);

    dc->realize = pnv_quad_realize;
    dc->props = pnv_quad_properties;
}

static const TypeInfo pnv_quad_info = {
    .name          = TYPE_PNV_QUAD,
    .parent        = TYPE_DEVICE,
    .instance_size = sizeof(PnvQuad),
    .class_init    = pnv_quad_class_init,
};

static void pnv_core_register_types(void)
{
    type_register_static(&pnv_quad_info);
}

type_init(pnv_core_register_types)
Commit	Line	Data
d2fd9612 CLG	1	/*
	2	* QEMU PowerPC PowerNV CPU Core model
	3	*
	4	* Copyright (c) 2016, IBM Corporation.
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public License
	8	* as published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#include "qemu/osdep.h"
	20	#include "sysemu/sysemu.h"
	21	#include "qapi/error.h"
24ece072	22	#include "qemu/log.h"
fcf5ef2a	23	#include "target/ppc/cpu.h"
d2fd9612 CLG	24	#include "hw/ppc/ppc.h"
	25	#include "hw/ppc/pnv.h"
	26	#include "hw/ppc/pnv_core.h"
ec575aa0	27	#include "hw/ppc/pnv_xscom.h"
960fbd29	28	#include "hw/ppc/xics.h"
d2fd9612	29
35bdb9de IM	30	static const char pnv_core_cpu_typename(PnvCore pc)
	31	{
	32	const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
	33	int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
	34	char s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.s"), len, core_type);
	35	const char *cpu_type = object_class_get_name(object_class_by_name(s));
	36	g_free(s);
	37	return cpu_type;
	38	}
	39
b168a138	40	static void pnv_cpu_reset(void *opaque)
d2fd9612 CLG	41	{
	42	PowerPCCPU *cpu = opaque;
	43	CPUState *cs = CPU(cpu);
	44	CPUPPCState *env = &cpu->env;
	45
	46	cpu_reset(cs);
	47
	48	/*
	49	* the skiboot firmware elects a primary thread to initialize the
	50	* system and it can be any.
	51	*/
	52	env->gpr[3] = PNV_FDT_ADDR;
	53	env->nip = 0x10;
	54	env->msr \|= MSR_HVB; /* Hypervisor mode */
	55	}
	56
24ece072 CLG	57	/*
	58	* These values are read by the PowerNV HW monitors under Linux
	59	*/
	60	#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
	61	#define PNV_XSCOM_EX_DTS_RESULT1 0x50001
	62
90ef386c CLG	63	static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr,
90ef386c CLG	64	unsigned int width)
24ece072 CLG	65	{
	66	uint32_t offset = addr >> 3;
	67	uint64_t val = 0;
	68
	69	/* The result should be 38 C */
	70	switch (offset) {
	71	case PNV_XSCOM_EX_DTS_RESULT0:
	72	val = 0x26f024f023f0000ull;
	73	break;
	74	case PNV_XSCOM_EX_DTS_RESULT1:
	75	val = 0x24f000000000000ull;
	76	break;
	77	default:
c7e71a18	78	qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
24ece072 CLG	79	addr);
	80	}
	81
	82	return val;
	83	}
	84
90ef386c CLG	85	static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val,
90ef386c CLG	86	unsigned int width)
24ece072	87	{
c7e71a18	88	qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
24ece072 CLG	89	addr);
	90	}
	91
90ef386c CLG	92	static const MemoryRegionOps pnv_core_power8_xscom_ops = {
	93	.read = pnv_core_power8_xscom_read,
	94	.write = pnv_core_power8_xscom_write,
	95	.valid.min_access_size = 8,
	96	.valid.max_access_size = 8,
	97	.impl.min_access_size = 8,
	98	.impl.max_access_size = 8,
	99	.endianness = DEVICE_BIG_ENDIAN,
	100	};
	101
	102
	103	/*
	104	* POWER9 core controls
	105	*/
	106	#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
	107	#define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
	108
	109	static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
	110	unsigned int width)
	111	{
	112	uint32_t offset = addr >> 3;
	113	uint64_t val = 0;
	114
	115	/* The result should be 38 C */
	116	switch (offset) {
	117	case PNV_XSCOM_EX_DTS_RESULT0:
	118	val = 0x26f024f023f0000ull;
	119	break;
	120	case PNV_XSCOM_EX_DTS_RESULT1:
	121	val = 0x24f000000000000ull;
	122	break;
	123	case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
	124	case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
	125	val = 0x0;
	126	break;
	127	default:
	128	qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
	129	addr);
	130	}
	131
	132	return val;
	133	}
	134
	135	static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
	136	unsigned int width)
	137	{
	138	uint32_t offset = addr >> 3;
	139
	140	switch (offset) {
	141	case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
	142	case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
	143	break;
	144	default:
	145	qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
	146	addr);
	147	}
	148	}
	149
	150	static const MemoryRegionOps pnv_core_power9_xscom_ops = {
	151	.read = pnv_core_power9_xscom_read,
	152	.write = pnv_core_power9_xscom_write,
24ece072 CLG	153	.valid.min_access_size = 8,
	154	.valid.max_access_size = 8,
	155	.impl.min_access_size = 8,
	156	.impl.max_access_size = 8,
	157	.endianness = DEVICE_BIG_ENDIAN,
	158	};
	159
d35aefa9	160	static void pnv_realize_vcpu(PowerPCCPU cpu, PnvChip chip, Error **errp)
d2fd9612	161	{
3a247521 DG	162	CPUPPCState *env = &cpu->env;
	163	int core_pir;
	164	int thread_index = 0; /* TODO: TCG supports only one thread */
	165	ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
d2fd9612	166	Error *local_err = NULL;
d35aefa9	167	PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
960fbd29	168
3a247521	169	object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
960fbd29 CLG	170	if (local_err) {
	171	error_propagate(errp, local_err);
	172	return;
	173	}
d2fd9612	174
8fa1f4ef	175	pcc->intc_create(chip, cpu, &local_err);
d2fd9612 CLG	176	if (local_err) {
	177	error_propagate(errp, local_err);
	178	return;
	179	}
	180
3a247521 DG	181	core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort);
	182
	183	/*
	184	* The PIR of a thread is the core PIR + the thread index. We will
	185	* need to find a way to get the thread index when TCG supports
	186	* more than 1. We could use the object name ?
	187	*/
	188	pir->default_value = core_pir + thread_index;
	189
	190	/* Set time-base frequency to 512 MHz */
	191	cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
	192
	193	qemu_register_reset(pnv_cpu_reset, cpu);
d2fd9612 CLG	194	}
	195
	196	static void pnv_core_realize(DeviceState dev, Error *errp)
	197	{
	198	PnvCore *pc = PNV_CORE(OBJECT(dev));
90ef386c	199	PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
d2fd9612	200	CPUCore *cc = CPU_CORE(OBJECT(dev));
35bdb9de	201	const char *typename = pnv_core_cpu_typename(pc);
d2fd9612 CLG	202	Error *local_err = NULL;
	203	void *obj;
	204	int i, j;
	205	char name[32];
d35aefa9	206	Object *chip;
960fbd29	207
d35aefa9 CLG	208	chip = object_property_get_link(OBJECT(dev), "chip", &local_err);
d35aefa9 CLG	209	if (!chip) {
4b576648 MA	210	error_propagate_prepend(errp, local_err,
4b576648 MA	211	"required link 'chip' not found: ");
56f68439	212	return;
960fbd29	213	}
d2fd9612	214
08304a86	215	pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
d2fd9612	216	for (i = 0; i < cc->nr_threads; i++) {
8907fc25 CLG	217	PowerPCCPU *cpu;
8907fc25 CLG	218
08304a86	219	obj = object_new(typename);
8907fc25	220	cpu = POWERPC_CPU(obj);
d2fd9612	221
08304a86	222	pc->threads[i] = POWERPC_CPU(obj);
d2fd9612 CLG	223
d2fd9612 CLG	224	snprintf(name, sizeof(name), "thread[%d]", i);
937c2146	225	object_property_add_child(OBJECT(pc), name, obj, &error_abort);
d2fd9612	226	object_property_add_alias(obj, "core-pir", OBJECT(pc),
937c2146	227	"pir", &error_abort);
8907fc25 CLG	228
	229	cpu->machine_data = g_new0(PnvCPUState, 1);
	230
d2fd9612 CLG	231	object_unref(obj);
	232	}
	233
	234	for (j = 0; j < cc->nr_threads; j++) {
d35aefa9	235	pnv_realize_vcpu(pc->threads[j], PNV_CHIP(chip), &local_err);
d2fd9612 CLG	236	if (local_err) {
	237	goto err;
	238	}
	239	}
24ece072 CLG	240
24ece072 CLG	241	snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
90ef386c	242	pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
c035851a	243	pc, name, PNV_XSCOM_EX_SIZE);
d2fd9612 CLG	244	return;
	245
	246	err:
	247	while (--i >= 0) {
08304a86	248	obj = OBJECT(pc->threads[i]);
d2fd9612 CLG	249	object_unparent(obj);
	250	}
	251	g_free(pc->threads);
	252	error_propagate(errp, local_err);
	253	}
	254
5e22e292 DG	255	static void pnv_unrealize_vcpu(PowerPCCPU *cpu)
5e22e292 DG	256	{
8907fc25 CLG	257	PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
8907fc25 CLG	258
5e22e292	259	qemu_unregister_reset(pnv_cpu_reset, cpu);
956b8f46	260	object_unparent(OBJECT(pnv_cpu_state(cpu)->intc));
5e22e292	261	cpu_remove_sync(CPU(cpu));
8907fc25 CLG	262	cpu->machine_data = NULL;
8907fc25 CLG	263	g_free(pnv_cpu);
5e22e292 DG	264	object_unparent(OBJECT(cpu));
	265	}
	266
	267	static void pnv_core_unrealize(DeviceState dev, Error *errp)
	268	{
	269	PnvCore *pc = PNV_CORE(dev);
	270	CPUCore *cc = CPU_CORE(dev);
	271	int i;
	272
	273	for (i = 0; i < cc->nr_threads; i++) {
	274	pnv_unrealize_vcpu(pc->threads[i]);
	275	}
	276	g_free(pc->threads);
	277	}
	278
d2fd9612 CLG	279	static Property pnv_core_properties[] = {
	280	DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
	281	DEFINE_PROP_END_OF_LIST(),
	282	};
	283
90ef386c CLG	284	static void pnv_core_power8_class_init(ObjectClass oc, void data)
	285	{
	286	PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
	287
	288	pcc->xscom_ops = &pnv_core_power8_xscom_ops;
	289	}
	290
	291	static void pnv_core_power9_class_init(ObjectClass oc, void data)
	292	{
	293	PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
	294
	295	pcc->xscom_ops = &pnv_core_power9_xscom_ops;
	296	}
	297
d2fd9612 CLG	298	static void pnv_core_class_init(ObjectClass oc, void data)
	299	{
	300	DeviceClass *dc = DEVICE_CLASS(oc);
d2fd9612 CLG	301
d2fd9612 CLG	302	dc->realize = pnv_core_realize;
5e22e292	303	dc->unrealize = pnv_core_unrealize;
d2fd9612	304	dc->props = pnv_core_properties;
d2fd9612 CLG	305	}
d2fd9612 CLG	306
90ef386c	307	#define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
7383af1e IM	308	{ \
	309	.parent = TYPE_PNV_CORE, \
	310	.name = PNV_CORE_TYPE_NAME(cpu_model), \
90ef386c	311	.class_init = pnv_core_##family##_class_init, \
d2fd9612	312	}
d2fd9612	313
7383af1e IM	314	static const TypeInfo pnv_core_infos[] = {
	315	{
	316	.name = TYPE_PNV_CORE,
	317	.parent = TYPE_CPU_CORE,
	318	.instance_size = sizeof(PnvCore),
	319	.class_size = sizeof(PnvCoreClass),
	320	.class_init = pnv_core_class_init,
	321	.abstract = true,
	322	},
90ef386c CLG	323	DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
	324	DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
	325	DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
	326	DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
7383af1e	327	};
d2fd9612	328
7383af1e	329	DEFINE_TYPES(pnv_core_infos)
5dad902c CLG	330
	331	/*
	332	* POWER9 Quads
	333	*/
	334
	335	#define P9X_EX_NCU_SPEC_BAR 0x11010
	336
	337	static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
	338	unsigned int width)
	339	{
	340	uint32_t offset = addr >> 3;
	341	uint64_t val = -1;
	342
	343	switch (offset) {
	344	case P9X_EX_NCU_SPEC_BAR:
	345	case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
	346	val = 0;
	347	break;
	348	default:
	349	qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
	350	offset);
	351	}
	352
	353	return val;
	354	}
	355
	356	static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
	357	unsigned int width)
	358	{
	359	uint32_t offset = addr >> 3;
	360
	361	switch (offset) {
	362	case P9X_EX_NCU_SPEC_BAR:
	363	case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
	364	break;
	365	default:
	366	qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
	367	offset);
	368	}
	369	}
	370
	371	static const MemoryRegionOps pnv_quad_xscom_ops = {
	372	.read = pnv_quad_xscom_read,
	373	.write = pnv_quad_xscom_write,
	374	.valid.min_access_size = 8,
	375	.valid.max_access_size = 8,
	376	.impl.min_access_size = 8,
	377	.impl.max_access_size = 8,
	378	.endianness = DEVICE_BIG_ENDIAN,
	379	};
	380
	381	static void pnv_quad_realize(DeviceState dev, Error *errp)
	382	{
	383	PnvQuad *eq = PNV_QUAD(dev);
	384	char name[32];
	385
	386	snprintf(name, sizeof(name), "xscom-quad.%d", eq->id);
	387	pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
	388	eq, name, PNV9_XSCOM_EQ_SIZE);
	389	}
	390
	391	static Property pnv_quad_properties[] = {
	392	DEFINE_PROP_UINT32("id", PnvQuad, id, 0),
	393	DEFINE_PROP_END_OF_LIST(),
394	};
395
396	static void pnv_quad_class_init(ObjectClass oc, void data)
397	{
398	DeviceClass *dc = DEVICE_CLASS(oc);
399
400	dc->realize = pnv_quad_realize;
401	dc->props = pnv_quad_properties;
402	}
403
404	static const TypeInfo pnv_quad_info = {
405	.name = TYPE_PNV_QUAD,
406	.parent = TYPE_DEVICE,
407	.instance_size = sizeof(PnvQuad),
408	.class_init = pnv_quad_class_init,
409	};
410
411	static void pnv_core_register_types(void)
412	{
413	type_register_static(&pnv_quad_info);
414	}
415
416	type_init(pnv_core_register_types)