[qemu.git] / hw / timer / milkymist-sysctl.c

/*
 *  QEMU model of the Milkymist System Controller.
 *
 *  Copyright (c) 2010-2012 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Specification available at:
 *   http://www.milkymist.org/socdoc/sysctl.pdf
 */

#include "hw/hw.h"
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "trace.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "qemu/error-report.h"

enum {
    CTRL_ENABLE      = (1<<0),
    CTRL_AUTORESTART = (1<<1),
};

enum {
    ICAP_READY       = (1<<0),
};

enum {
    R_GPIO_IN         = 0,
    R_GPIO_OUT,
    R_GPIO_INTEN,
    R_TIMER0_CONTROL  = 4,
    R_TIMER0_COMPARE,
    R_TIMER0_COUNTER,
    R_TIMER1_CONTROL  = 8,
    R_TIMER1_COMPARE,
    R_TIMER1_COUNTER,
    R_ICAP = 16,
    R_DBG_SCRATCHPAD  = 20,
    R_DBG_WRITE_LOCK,
    R_CLK_FREQUENCY   = 29,
    R_CAPABILITIES,
    R_SYSTEM_ID,
    R_MAX
};

struct MilkymistSysctlState {
    SysBusDevice busdev;
    MemoryRegion regs_region;

    QEMUBH *bh0;
    QEMUBH *bh1;
    ptimer_state *ptimer0;
    ptimer_state *ptimer1;

    uint32_t freq_hz;
    uint32_t capabilities;
    uint32_t systemid;
    uint32_t strappings;

    uint32_t regs[R_MAX];

    qemu_irq gpio_irq;
    qemu_irq timer0_irq;
    qemu_irq timer1_irq;
};
typedef struct MilkymistSysctlState MilkymistSysctlState;

static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
{
    trace_milkymist_sysctl_icap_write(value);
    switch (value & 0xffff) {
    case 0x000e:
        qemu_system_shutdown_request();
        break;
    }
}

static uint64_t sysctl_read(void *opaque, hwaddr addr,
                            unsigned size)
{
    MilkymistSysctlState *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr) {
    case R_TIMER0_COUNTER:
        r = (uint32_t)ptimer_get_count(s->ptimer0);
        /* milkymist timer counts up */
        r = s->regs[R_TIMER0_COMPARE] - r;
        break;
    case R_TIMER1_COUNTER:
        r = (uint32_t)ptimer_get_count(s->ptimer1);
        /* milkymist timer counts up */
        r = s->regs[R_TIMER1_COMPARE] - r;
        break;
    case R_GPIO_IN:
    case R_GPIO_OUT:
    case R_GPIO_INTEN:
    case R_TIMER0_CONTROL:
    case R_TIMER0_COMPARE:
    case R_TIMER1_CONTROL:
    case R_TIMER1_COMPARE:
    case R_ICAP:
    case R_DBG_SCRATCHPAD:
    case R_DBG_WRITE_LOCK:
    case R_CLK_FREQUENCY:
    case R_CAPABILITIES:
    case R_SYSTEM_ID:
        r = s->regs[addr];
        break;

    default:
        error_report("milkymist_sysctl: read access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }

    trace_milkymist_sysctl_memory_read(addr << 2, r);

    return r;
}

static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
                         unsigned size)
{
    MilkymistSysctlState *s = opaque;

    trace_milkymist_sysctl_memory_write(addr, value);

    addr >>= 2;
    switch (addr) {
    case R_GPIO_OUT:
    case R_GPIO_INTEN:
    case R_TIMER0_COUNTER:
    case R_TIMER1_COUNTER:
    case R_DBG_SCRATCHPAD:
        s->regs[addr] = value;
        break;
    case R_TIMER0_COMPARE:
        ptimer_set_limit(s->ptimer0, value, 0);
        s->regs[addr] = value;
        break;
    case R_TIMER1_COMPARE:
        ptimer_set_limit(s->ptimer1, value, 0);
        s->regs[addr] = value;
        break;
    case R_TIMER0_CONTROL:
        s->regs[addr] = value;
        if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
            trace_milkymist_sysctl_start_timer0();
            ptimer_set_count(s->ptimer0,
                    s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
            ptimer_run(s->ptimer0, 0);
        } else {
            trace_milkymist_sysctl_stop_timer0();
            ptimer_stop(s->ptimer0);
        }
        break;
    case R_TIMER1_CONTROL:
        s->regs[addr] = value;
        if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
            trace_milkymist_sysctl_start_timer1();
            ptimer_set_count(s->ptimer1,
                    s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
            ptimer_run(s->ptimer1, 0);
        } else {
            trace_milkymist_sysctl_stop_timer1();
            ptimer_stop(s->ptimer1);
        }
        break;
    case R_ICAP:
        sysctl_icap_write(s, value);
        break;
    case R_DBG_WRITE_LOCK:
        s->regs[addr] = 1;
        break;
    case R_SYSTEM_ID:
        qemu_system_reset_request();
        break;

    case R_GPIO_IN:
    case R_CLK_FREQUENCY:
    case R_CAPABILITIES:
        error_report("milkymist_sysctl: write to read-only register 0x"
                TARGET_FMT_plx, addr << 2);
        break;

    default:
        error_report("milkymist_sysctl: write access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }
}

static const MemoryRegionOps sysctl_mmio_ops = {
    .read = sysctl_read,
    .write = sysctl_write,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void timer0_hit(void *opaque)
{
    MilkymistSysctlState *s = opaque;

    if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
        s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
        trace_milkymist_sysctl_stop_timer0();
        ptimer_stop(s->ptimer0);
    }

    trace_milkymist_sysctl_pulse_irq_timer0();
    qemu_irq_pulse(s->timer0_irq);
}

static void timer1_hit(void *opaque)
{
    MilkymistSysctlState *s = opaque;

    if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
        s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
        trace_milkymist_sysctl_stop_timer1();
        ptimer_stop(s->ptimer1);
    }

    trace_milkymist_sysctl_pulse_irq_timer1();
    qemu_irq_pulse(s->timer1_irq);
}

static void milkymist_sysctl_reset(DeviceState *d)
{
    MilkymistSysctlState *s =
            container_of(d, MilkymistSysctlState, busdev.qdev);
    int i;

    for (i = 0; i < R_MAX; i++) {
        s->regs[i] = 0;
    }

    ptimer_stop(s->ptimer0);
    ptimer_stop(s->ptimer1);

    /* defaults */
    s->regs[R_ICAP] = ICAP_READY;
    s->regs[R_SYSTEM_ID] = s->systemid;
    s->regs[R_CLK_FREQUENCY] = s->freq_hz;
    s->regs[R_CAPABILITIES] = s->capabilities;
    s->regs[R_GPIO_IN] = s->strappings;
}

static int milkymist_sysctl_init(SysBusDevice *dev)
{
    MilkymistSysctlState *s = FROM_SYSBUS(typeof(*s), dev);

    sysbus_init_irq(dev, &s->gpio_irq);
    sysbus_init_irq(dev, &s->timer0_irq);
    sysbus_init_irq(dev, &s->timer1_irq);

    s->bh0 = qemu_bh_new(timer0_hit, s);
    s->bh1 = qemu_bh_new(timer1_hit, s);
    s->ptimer0 = ptimer_init(s->bh0);
    s->ptimer1 = ptimer_init(s->bh1);
    ptimer_set_freq(s->ptimer0, s->freq_hz);
    ptimer_set_freq(s->ptimer1, s->freq_hz);

    memory_region_init_io(&s->regs_region, OBJECT(s), &sysctl_mmio_ops, s,
            "milkymist-sysctl", R_MAX * 4);
    sysbus_init_mmio(dev, &s->regs_region);

    return 0;
}

static const VMStateDescription vmstate_milkymist_sysctl = {
    .name = "milkymist-sysctl",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
        VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
        VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
        VMSTATE_END_OF_LIST()
    }
};

static Property milkymist_sysctl_properties[] = {
    DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
    freq_hz, 80000000),
    DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
    capabilities, 0x00000000),
    DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
    systemid, 0x10014d31),
    DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
    strappings, 0x00000001),
    DEFINE_PROP_END_OF_LIST(),
};

static void milkymist_sysctl_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = milkymist_sysctl_init;
    dc->reset = milkymist_sysctl_reset;
    dc->vmsd = &vmstate_milkymist_sysctl;
    dc->props = milkymist_sysctl_properties;
}

static const TypeInfo milkymist_sysctl_info = {
    .name          = "milkymist-sysctl",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MilkymistSysctlState),
    .class_init    = milkymist_sysctl_class_init,
};

static void milkymist_sysctl_register_types(void)
{
    type_register_static(&milkymist_sysctl_info);
}

type_init(milkymist_sysctl_register_types)
Commit	Line	Data
96832424 MW	1	/*
	2	* QEMU model of the Milkymist System Controller.
	3	*
060544d3	4	* Copyright (c) 2010-2012 Michael Walle <[email protected]>
96832424 MW	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*
	19	*
	20	* Specification available at:
	21	* http://www.milkymist.org/socdoc/sysctl.pdf
	22	*/
	23
83c9f4ca PB	24	#include "hw/hw.h"
83c9f4ca PB	25	#include "hw/sysbus.h"
9c17d615	26	#include "sysemu/sysemu.h"
96832424	27	#include "trace.h"
1de7afc9	28	#include "qemu/timer.h"
83c9f4ca	29	#include "hw/ptimer.h"
1de7afc9	30	#include "qemu/error-report.h"
96832424 MW	31
	32	enum {
	33	CTRL_ENABLE = (1<<0),
	34	CTRL_AUTORESTART = (1<<1),
	35	};
	36
	37	enum {
	38	ICAP_READY = (1<<0),
	39	};
	40
	41	enum {
060544d3	42	R_GPIO_IN = 0,
96832424 MW	43	R_GPIO_OUT,
96832424 MW	44	R_GPIO_INTEN,
060544d3	45	R_TIMER0_CONTROL = 4,
96832424 MW	46	R_TIMER0_COMPARE,
96832424 MW	47	R_TIMER0_COUNTER,
060544d3	48	R_TIMER1_CONTROL = 8,
96832424 MW	49	R_TIMER1_COMPARE,
96832424 MW	50	R_TIMER1_COUNTER,
060544d3 MW	51	R_ICAP = 16,
	52	R_DBG_SCRATCHPAD = 20,
	53	R_DBG_WRITE_LOCK,
	54	R_CLK_FREQUENCY = 29,
96832424 MW	55	R_CAPABILITIES,
	56	R_SYSTEM_ID,
	57	R_MAX
	58	};
	59
	60	struct MilkymistSysctlState {
	61	SysBusDevice busdev;
dfa87ccf	62	MemoryRegion regs_region;
96832424 MW	63
	64	QEMUBH *bh0;
	65	QEMUBH *bh1;
	66	ptimer_state *ptimer0;
	67	ptimer_state *ptimer1;
	68
	69	uint32_t freq_hz;
	70	uint32_t capabilities;
	71	uint32_t systemid;
	72	uint32_t strappings;
	73
	74	uint32_t regs[R_MAX];
	75
	76	qemu_irq gpio_irq;
	77	qemu_irq timer0_irq;
	78	qemu_irq timer1_irq;
	79	};
	80	typedef struct MilkymistSysctlState MilkymistSysctlState;
	81
	82	static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
	83	{
	84	trace_milkymist_sysctl_icap_write(value);
	85	switch (value & 0xffff) {
	86	case 0x000e:
	87	qemu_system_shutdown_request();
	88	break;
	89	}
	90	}
	91
a8170e5e	92	static uint64_t sysctl_read(void *opaque, hwaddr addr,
dfa87ccf	93	unsigned size)
96832424 MW	94	{
	95	MilkymistSysctlState *s = opaque;
	96	uint32_t r = 0;
	97
	98	addr >>= 2;
	99	switch (addr) {
	100	case R_TIMER0_COUNTER:
	101	r = (uint32_t)ptimer_get_count(s->ptimer0);
	102	/* milkymist timer counts up */
	103	r = s->regs[R_TIMER0_COMPARE] - r;
	104	break;
	105	case R_TIMER1_COUNTER:
	106	r = (uint32_t)ptimer_get_count(s->ptimer1);
	107	/* milkymist timer counts up */
	108	r = s->regs[R_TIMER1_COMPARE] - r;
	109	break;
	110	case R_GPIO_IN:
	111	case R_GPIO_OUT:
	112	case R_GPIO_INTEN:
	113	case R_TIMER0_CONTROL:
	114	case R_TIMER0_COMPARE:
	115	case R_TIMER1_CONTROL:
	116	case R_TIMER1_COMPARE:
	117	case R_ICAP:
060544d3 MW	118	case R_DBG_SCRATCHPAD:
	119	case R_DBG_WRITE_LOCK:
	120	case R_CLK_FREQUENCY:
96832424 MW	121	case R_CAPABILITIES:
	122	case R_SYSTEM_ID:
	123	r = s->regs[addr];
	124	break;
	125
	126	default:
dd3d6775	127	error_report("milkymist_sysctl: read access to unknown register 0x"
96832424 MW	128	TARGET_FMT_plx, addr << 2);
	129	break;
	130	}
	131
	132	trace_milkymist_sysctl_memory_read(addr << 2, r);
	133
	134	return r;
	135	}
	136
a8170e5e	137	static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
dfa87ccf	138	unsigned size)
96832424 MW	139	{
	140	MilkymistSysctlState *s = opaque;
	141
	142	trace_milkymist_sysctl_memory_write(addr, value);
	143
	144	addr >>= 2;
	145	switch (addr) {
	146	case R_GPIO_OUT:
	147	case R_GPIO_INTEN:
	148	case R_TIMER0_COUNTER:
96832424	149	case R_TIMER1_COUNTER:
060544d3	150	case R_DBG_SCRATCHPAD:
f3172a0e	151	s->regs[addr] = value;
96832424 MW	152	break;
	153	case R_TIMER0_COMPARE:
	154	ptimer_set_limit(s->ptimer0, value, 0);
	155	s->regs[addr] = value;
	156	break;
	157	case R_TIMER1_COMPARE:
	158	ptimer_set_limit(s->ptimer1, value, 0);
	159	s->regs[addr] = value;
	160	break;
	161	case R_TIMER0_CONTROL:
	162	s->regs[addr] = value;
	163	if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
f3172a0e MW	164	trace_milkymist_sysctl_start_timer0();
	165	ptimer_set_count(s->ptimer0,
	166	s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
96832424 MW	167	ptimer_run(s->ptimer0, 0);
96832424 MW	168	} else {
f3172a0e	169	trace_milkymist_sysctl_stop_timer0();
96832424 MW	170	ptimer_stop(s->ptimer0);
	171	}
	172	break;
	173	case R_TIMER1_CONTROL:
	174	s->regs[addr] = value;
	175	if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
	176	trace_milkymist_sysctl_start_timer1();
f3172a0e MW	177	ptimer_set_count(s->ptimer1,
f3172a0e MW	178	s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
96832424 MW	179	ptimer_run(s->ptimer1, 0);
	180	} else {
	181	trace_milkymist_sysctl_stop_timer1();
	182	ptimer_stop(s->ptimer1);
	183	}
	184	break;
	185	case R_ICAP:
	186	sysctl_icap_write(s, value);
	187	break;
060544d3 MW	188	case R_DBG_WRITE_LOCK:
	189	s->regs[addr] = 1;
	190	break;
96832424 MW	191	case R_SYSTEM_ID:
	192	qemu_system_reset_request();
	193	break;
	194
	195	case R_GPIO_IN:
060544d3	196	case R_CLK_FREQUENCY:
96832424 MW	197	case R_CAPABILITIES:
	198	error_report("milkymist_sysctl: write to read-only register 0x"
	199	TARGET_FMT_plx, addr << 2);
	200	break;
	201
	202	default:
dd3d6775	203	error_report("milkymist_sysctl: write access to unknown register 0x"
96832424 MW	204	TARGET_FMT_plx, addr << 2);
	205	break;
	206	}
	207	}
	208
dfa87ccf MW	209	static const MemoryRegionOps sysctl_mmio_ops = {
	210	.read = sysctl_read,
	211	.write = sysctl_write,
	212	.valid = {
	213	.min_access_size = 4,
	214	.max_access_size = 4,
	215	},
	216	.endianness = DEVICE_NATIVE_ENDIAN,
96832424 MW	217	};
	218
	219	static void timer0_hit(void *opaque)
	220	{
	221	MilkymistSysctlState *s = opaque;
	222
	223	if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
	224	s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
	225	trace_milkymist_sysctl_stop_timer0();
	226	ptimer_stop(s->ptimer0);
	227	}
	228
	229	trace_milkymist_sysctl_pulse_irq_timer0();
	230	qemu_irq_pulse(s->timer0_irq);
	231	}
	232
	233	static void timer1_hit(void *opaque)
	234	{
	235	MilkymistSysctlState *s = opaque;
	236
	237	if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
	238	s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
	239	trace_milkymist_sysctl_stop_timer1();
	240	ptimer_stop(s->ptimer1);
	241	}
	242
	243	trace_milkymist_sysctl_pulse_irq_timer1();
	244	qemu_irq_pulse(s->timer1_irq);
	245	}
	246
	247	static void milkymist_sysctl_reset(DeviceState *d)
	248	{
	249	MilkymistSysctlState *s =
	250	container_of(d, MilkymistSysctlState, busdev.qdev);
	251	int i;
	252
	253	for (i = 0; i < R_MAX; i++) {
	254	s->regs[i] = 0;
	255	}
	256
	257	ptimer_stop(s->ptimer0);
	258	ptimer_stop(s->ptimer1);
	259
	260	/* defaults */
	261	s->regs[R_ICAP] = ICAP_READY;
	262	s->regs[R_SYSTEM_ID] = s->systemid;
060544d3	263	s->regs[R_CLK_FREQUENCY] = s->freq_hz;
96832424 MW	264	s->regs[R_CAPABILITIES] = s->capabilities;
	265	s->regs[R_GPIO_IN] = s->strappings;
	266	}
	267
	268	static int milkymist_sysctl_init(SysBusDevice *dev)
	269	{
	270	MilkymistSysctlState s = FROM_SYSBUS(typeof(s), dev);
96832424 MW	271
	272	sysbus_init_irq(dev, &s->gpio_irq);
	273	sysbus_init_irq(dev, &s->timer0_irq);
	274	sysbus_init_irq(dev, &s->timer1_irq);
	275
	276	s->bh0 = qemu_bh_new(timer0_hit, s);
	277	s->bh1 = qemu_bh_new(timer1_hit, s);
	278	s->ptimer0 = ptimer_init(s->bh0);
	279	s->ptimer1 = ptimer_init(s->bh1);
	280	ptimer_set_freq(s->ptimer0, s->freq_hz);
	281	ptimer_set_freq(s->ptimer1, s->freq_hz);
	282
853dca12	283	memory_region_init_io(&s->regs_region, OBJECT(s), &sysctl_mmio_ops, s,
dfa87ccf	284	"milkymist-sysctl", R_MAX * 4);
750ecd44	285	sysbus_init_mmio(dev, &s->regs_region);
96832424 MW	286
	287	return 0;
	288	}
	289
	290	static const VMStateDescription vmstate_milkymist_sysctl = {
	291	.name = "milkymist-sysctl",
	292	.version_id = 1,
	293	.minimum_version_id = 1,
	294	.minimum_version_id_old = 1,
	295	.fields = (VMStateField[]) {
	296	VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
	297	VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
	298	VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
	299	VMSTATE_END_OF_LIST()
	300	}
	301	};
	302
999e12bb AL	303	static Property milkymist_sysctl_properties[] = {
	304	DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
	305	freq_hz, 80000000),
	306	DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
	307	capabilities, 0x00000000),
	308	DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
	309	systemid, 0x10014d31),
	310	DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
	311	strappings, 0x00000001),
	312	DEFINE_PROP_END_OF_LIST(),
	313	};
	314
	315	static void milkymist_sysctl_class_init(ObjectClass klass, void data)
	316	{
39bffca2	317	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	318	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	319
	320	k->init = milkymist_sysctl_init;
39bffca2 AL	321	dc->reset = milkymist_sysctl_reset;
	322	dc->vmsd = &vmstate_milkymist_sysctl;
	323	dc->props = milkymist_sysctl_properties;
999e12bb AL	324	}
999e12bb AL	325
8c43a6f0	326	static const TypeInfo milkymist_sysctl_info = {
39bffca2 AL	327	.name = "milkymist-sysctl",
	328	.parent = TYPE_SYS_BUS_DEVICE,
	329	.instance_size = sizeof(MilkymistSysctlState),
	330	.class_init = milkymist_sysctl_class_init,
96832424 MW	331	};
96832424 MW	332
83f7d43a	333	static void milkymist_sysctl_register_types(void)
96832424	334	{
39bffca2	335	type_register_static(&milkymist_sysctl_info);
96832424 MW	336	}
96832424 MW	337
83f7d43a	338	type_init(milkymist_sysctl_register_types)