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Commit | Line | Data |
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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
1590bbcb | 4 | * Copyright (c) 2012-2014 SUSE LINUX Products GmbH |
dd83b06a AF |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | ||
1ef26b1f | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
dd83b06a | 23 | #include "qemu-common.h" |
878096ee | 24 | #include "qom/cpu.h" |
b3946626 | 25 | #include "sysemu/hw_accel.h" |
066e9b27 | 26 | #include "qemu/notify.h" |
91b1df8c | 27 | #include "qemu/log.h" |
508127e2 | 28 | #include "exec/log.h" |
2cd53943 | 29 | #include "exec/cpu-common.h" |
9262685b | 30 | #include "qemu/error-report.h" |
066e9b27 | 31 | #include "sysemu/sysemu.h" |
ed860129 | 32 | #include "hw/boards.h" |
62a48a2a | 33 | #include "hw/qdev-properties.h" |
0ab8ed18 | 34 | #include "trace-root.h" |
066e9b27 | 35 | |
290dae46 PB |
36 | CPUInterruptHandler cpu_interrupt_handler; |
37 | ||
5ce46cb3 | 38 | CPUState *cpu_by_arch_id(int64_t id) |
69e5ff06 | 39 | { |
38fcbd3f AF |
40 | CPUState *cpu; |
41 | ||
42 | CPU_FOREACH(cpu) { | |
43 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
69e5ff06 | 44 | |
38fcbd3f | 45 | if (cc->get_arch_id(cpu) == id) { |
5ce46cb3 | 46 | return cpu; |
38fcbd3f AF |
47 | } |
48 | } | |
5ce46cb3 EH |
49 | return NULL; |
50 | } | |
51 | ||
52 | bool cpu_exists(int64_t id) | |
53 | { | |
54 | return !!cpu_by_arch_id(id); | |
69e5ff06 IM |
55 | } |
56 | ||
3c72234c IM |
57 | CPUState *cpu_create(const char *typename) |
58 | { | |
59 | Error *err = NULL; | |
60 | CPUState *cpu = CPU(object_new(typename)); | |
61 | object_property_set_bool(OBJECT(cpu), true, "realized", &err); | |
62 | if (err != NULL) { | |
63 | error_report_err(err); | |
64 | object_unref(OBJECT(cpu)); | |
4482e05c | 65 | exit(EXIT_FAILURE); |
3c72234c IM |
66 | } |
67 | return cpu; | |
68 | } | |
69 | ||
444d5590 AF |
70 | bool cpu_paging_enabled(const CPUState *cpu) |
71 | { | |
72 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
73 | ||
74 | return cc->get_paging_enabled(cpu); | |
75 | } | |
76 | ||
77 | static bool cpu_common_get_paging_enabled(const CPUState *cpu) | |
78 | { | |
6db297ea | 79 | return false; |
444d5590 AF |
80 | } |
81 | ||
a23bbfda AF |
82 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, |
83 | Error **errp) | |
84 | { | |
85 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
86 | ||
fbe95bfb | 87 | cc->get_memory_mapping(cpu, list, errp); |
a23bbfda AF |
88 | } |
89 | ||
90 | static void cpu_common_get_memory_mapping(CPUState *cpu, | |
91 | MemoryMappingList *list, | |
92 | Error **errp) | |
93 | { | |
94 | error_setg(errp, "Obtaining memory mappings is unsupported on this CPU."); | |
95 | } | |
96 | ||
8d04fb55 JK |
97 | /* Resetting the IRQ comes from across the code base so we take the |
98 | * BQL here if we need to. cpu_interrupt assumes it is held.*/ | |
d8ed887b AF |
99 | void cpu_reset_interrupt(CPUState *cpu, int mask) |
100 | { | |
8d04fb55 JK |
101 | bool need_lock = !qemu_mutex_iothread_locked(); |
102 | ||
103 | if (need_lock) { | |
104 | qemu_mutex_lock_iothread(); | |
105 | } | |
d8ed887b | 106 | cpu->interrupt_request &= ~mask; |
8d04fb55 JK |
107 | if (need_lock) { |
108 | qemu_mutex_unlock_iothread(); | |
109 | } | |
d8ed887b AF |
110 | } |
111 | ||
60a3e17a AF |
112 | void cpu_exit(CPUState *cpu) |
113 | { | |
027d9a7d | 114 | atomic_set(&cpu->exit_request, 1); |
ab096a75 PB |
115 | /* Ensure cpu_exec will see the exit request after TCG has exited. */ |
116 | smp_wmb(); | |
1aab16c2 | 117 | atomic_set(&cpu->icount_decr.u16.high, -1); |
60a3e17a AF |
118 | } |
119 | ||
c72bf468 JF |
120 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
121 | void *opaque) | |
122 | { | |
123 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
124 | ||
125 | return (*cc->write_elf32_qemunote)(f, cpu, opaque); | |
126 | } | |
127 | ||
128 | static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f, | |
129 | CPUState *cpu, void *opaque) | |
130 | { | |
b09afd58 | 131 | return 0; |
c72bf468 JF |
132 | } |
133 | ||
134 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
135 | int cpuid, void *opaque) | |
136 | { | |
137 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
138 | ||
139 | return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); | |
140 | } | |
141 | ||
142 | static int cpu_common_write_elf32_note(WriteCoreDumpFunction f, | |
143 | CPUState *cpu, int cpuid, | |
144 | void *opaque) | |
145 | { | |
146 | return -1; | |
147 | } | |
148 | ||
149 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
150 | void *opaque) | |
151 | { | |
152 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
153 | ||
154 | return (*cc->write_elf64_qemunote)(f, cpu, opaque); | |
155 | } | |
156 | ||
157 | static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f, | |
158 | CPUState *cpu, void *opaque) | |
159 | { | |
b09afd58 | 160 | return 0; |
c72bf468 JF |
161 | } |
162 | ||
163 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
164 | int cpuid, void *opaque) | |
165 | { | |
166 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
167 | ||
168 | return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); | |
169 | } | |
170 | ||
171 | static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, | |
172 | CPUState *cpu, int cpuid, | |
173 | void *opaque) | |
174 | { | |
175 | return -1; | |
176 | } | |
177 | ||
178 | ||
5b50e790 AF |
179 | static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg) |
180 | { | |
181 | return 0; | |
182 | } | |
183 | ||
184 | static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg) | |
185 | { | |
186 | return 0; | |
187 | } | |
188 | ||
568496c0 SF |
189 | static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp) |
190 | { | |
191 | /* If no extra check is required, QEMU watchpoint match can be considered | |
192 | * as an architectural match. | |
193 | */ | |
194 | return true; | |
195 | } | |
196 | ||
bf7663c4 GK |
197 | bool target_words_bigendian(void); |
198 | static bool cpu_common_virtio_is_big_endian(CPUState *cpu) | |
199 | { | |
200 | return target_words_bigendian(); | |
201 | } | |
5b50e790 | 202 | |
cffe7b32 | 203 | static void cpu_common_noop(CPUState *cpu) |
86025ee4 PM |
204 | { |
205 | } | |
206 | ||
9585db68 RH |
207 | static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req) |
208 | { | |
209 | return false; | |
210 | } | |
211 | ||
c86f106b AN |
212 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) |
213 | { | |
214 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
215 | GuestPanicInformation *res = NULL; | |
216 | ||
217 | if (cc->get_crash_info) { | |
218 | res = cc->get_crash_info(cpu); | |
219 | } | |
220 | return res; | |
221 | } | |
222 | ||
878096ee AF |
223 | void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, |
224 | int flags) | |
225 | { | |
226 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
227 | ||
228 | if (cc->dump_state) { | |
97577fd4 | 229 | cpu_synchronize_state(cpu); |
878096ee AF |
230 | cc->dump_state(cpu, f, cpu_fprintf, flags); |
231 | } | |
232 | } | |
233 | ||
234 | void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
235 | int flags) | |
236 | { | |
237 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
238 | ||
239 | if (cc->dump_statistics) { | |
240 | cc->dump_statistics(cpu, f, cpu_fprintf, flags); | |
241 | } | |
242 | } | |
243 | ||
dd83b06a AF |
244 | void cpu_reset(CPUState *cpu) |
245 | { | |
246 | CPUClass *klass = CPU_GET_CLASS(cpu); | |
247 | ||
248 | if (klass->reset != NULL) { | |
249 | (*klass->reset)(cpu); | |
250 | } | |
2cc2d082 LV |
251 | |
252 | trace_guest_cpu_reset(cpu); | |
dd83b06a AF |
253 | } |
254 | ||
255 | static void cpu_common_reset(CPUState *cpu) | |
256 | { | |
91b1df8c AF |
257 | CPUClass *cc = CPU_GET_CLASS(cpu); |
258 | ||
259 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
260 | qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index); | |
261 | log_cpu_state(cpu, cc->reset_dump_flags); | |
262 | } | |
263 | ||
259186a7 | 264 | cpu->interrupt_request = 0; |
259186a7 | 265 | cpu->halted = 0; |
93afeade AF |
266 | cpu->mem_io_pc = 0; |
267 | cpu->mem_io_vaddr = 0; | |
efee7340 | 268 | cpu->icount_extra = 0; |
28ecfd7a | 269 | cpu->icount_decr.u32 = 0; |
414b15c9 | 270 | cpu->can_do_io = 1; |
f9d8f667 | 271 | cpu->exception_index = -1; |
bac05aa9 | 272 | cpu->crash_occurred = false; |
9b990ee5 | 273 | cpu->cflags_next_tb = -1; |
ce7cf6a9 | 274 | |
ba7d3d18 | 275 | if (tcg_enabled()) { |
f3ced3c5 | 276 | cpu_tb_jmp_cache_clear(cpu); |
1f5c00cf | 277 | |
2cd53943 | 278 | tcg_flush_softmmu_tlb(cpu); |
ba7d3d18 | 279 | } |
dd83b06a AF |
280 | } |
281 | ||
8c2e1b00 AF |
282 | static bool cpu_common_has_work(CPUState *cs) |
283 | { | |
284 | return false; | |
285 | } | |
286 | ||
2b8c2754 AF |
287 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model) |
288 | { | |
99193d8f | 289 | CPUClass *cc = CPU_CLASS(object_class_by_name(typename)); |
2b8c2754 | 290 | |
99193d8f | 291 | assert(cpu_model && cc->class_by_name); |
2b8c2754 AF |
292 | return cc->class_by_name(cpu_model); |
293 | } | |
294 | ||
62a48a2a | 295 | static void cpu_common_parse_features(const char *typename, char *features, |
1590bbcb AF |
296 | Error **errp) |
297 | { | |
1590bbcb | 298 | char *val; |
62a48a2a | 299 | static bool cpu_globals_initialized; |
2278b939 IM |
300 | /* Single "key=value" string being parsed */ |
301 | char *featurestr = features ? strtok(features, ",") : NULL; | |
62a48a2a | 302 | |
2278b939 IM |
303 | /* should be called only once, catch invalid users */ |
304 | assert(!cpu_globals_initialized); | |
62a48a2a | 305 | cpu_globals_initialized = true; |
1590bbcb | 306 | |
1590bbcb AF |
307 | while (featurestr) { |
308 | val = strchr(featurestr, '='); | |
309 | if (val) { | |
62a48a2a | 310 | GlobalProperty *prop = g_new0(typeof(*prop), 1); |
1590bbcb AF |
311 | *val = 0; |
312 | val++; | |
62a48a2a IM |
313 | prop->driver = typename; |
314 | prop->property = g_strdup(featurestr); | |
315 | prop->value = g_strdup(val); | |
316 | prop->errp = &error_fatal; | |
317 | qdev_prop_register_global(prop); | |
1590bbcb AF |
318 | } else { |
319 | error_setg(errp, "Expected key=value format, found %s.", | |
320 | featurestr); | |
321 | return; | |
322 | } | |
323 | featurestr = strtok(NULL, ","); | |
324 | } | |
325 | } | |
326 | ||
4f658099 AF |
327 | static void cpu_common_realizefn(DeviceState *dev, Error **errp) |
328 | { | |
13eed94e | 329 | CPUState *cpu = CPU(dev); |
ed860129 PM |
330 | Object *machine = qdev_get_machine(); |
331 | ||
332 | /* qdev_get_machine() can return something that's not TYPE_MACHINE | |
333 | * if this is one of the user-only emulators; in that case there's | |
334 | * no need to check the ignore_memory_transaction_failures board flag. | |
335 | */ | |
336 | if (object_dynamic_cast(machine, TYPE_MACHINE)) { | |
337 | ObjectClass *oc = object_get_class(machine); | |
338 | MachineClass *mc = MACHINE_CLASS(oc); | |
339 | ||
340 | if (mc) { | |
341 | cpu->ignore_memory_transaction_failures = | |
342 | mc->ignore_memory_transaction_failures; | |
343 | } | |
344 | } | |
13eed94e IM |
345 | |
346 | if (dev->hotplugged) { | |
347 | cpu_synchronize_post_init(cpu); | |
6afb4721 | 348 | cpu_resume(cpu); |
13eed94e | 349 | } |
2bfe11c8 LV |
350 | |
351 | /* NOTE: latest generic point where the cpu is fully realized */ | |
352 | trace_init_vcpu(cpu); | |
4f658099 AF |
353 | } |
354 | ||
7bbc124e LV |
355 | static void cpu_common_unrealizefn(DeviceState *dev, Error **errp) |
356 | { | |
357 | CPUState *cpu = CPU(dev); | |
82e95ec8 LV |
358 | /* NOTE: latest generic point before the cpu is fully unrealized */ |
359 | trace_fini_vcpu(cpu); | |
7bbc124e LV |
360 | cpu_exec_unrealizefn(cpu); |
361 | } | |
362 | ||
a0e372f0 AF |
363 | static void cpu_common_initfn(Object *obj) |
364 | { | |
365 | CPUState *cpu = CPU(obj); | |
366 | CPUClass *cc = CPU_GET_CLASS(obj); | |
367 | ||
a07f953e | 368 | cpu->cpu_index = UNASSIGNED_CPU_INDEX; |
35143f01 | 369 | cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs; |
fa5376dd MAL |
370 | /* *-user doesn't have configurable SMP topology */ |
371 | /* the default value is changed by qemu_init_vcpu() for softmmu */ | |
372 | cpu->nr_cores = 1; | |
373 | cpu->nr_threads = 1; | |
374 | ||
376692b9 | 375 | qemu_mutex_init(&cpu->work_mutex); |
7c39163e EH |
376 | QTAILQ_INIT(&cpu->breakpoints); |
377 | QTAILQ_INIT(&cpu->watchpoints); | |
b7d48952 | 378 | |
39e329e3 | 379 | cpu_exec_initfn(cpu); |
a0e372f0 AF |
380 | } |
381 | ||
b7bca733 BR |
382 | static void cpu_common_finalize(Object *obj) |
383 | { | |
b7bca733 BR |
384 | } |
385 | ||
997395d3 IM |
386 | static int64_t cpu_common_get_arch_id(CPUState *cpu) |
387 | { | |
388 | return cpu->cpu_index; | |
389 | } | |
390 | ||
40612000 JB |
391 | static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len) |
392 | { | |
393 | return addr; | |
394 | } | |
395 | ||
290dae46 PB |
396 | static void generic_handle_interrupt(CPUState *cpu, int mask) |
397 | { | |
398 | cpu->interrupt_request |= mask; | |
399 | ||
400 | if (!qemu_cpu_is_self(cpu)) { | |
401 | qemu_cpu_kick(cpu); | |
402 | } | |
403 | } | |
404 | ||
405 | CPUInterruptHandler cpu_interrupt_handler = generic_handle_interrupt; | |
406 | ||
dd83b06a AF |
407 | static void cpu_class_init(ObjectClass *klass, void *data) |
408 | { | |
961f8395 | 409 | DeviceClass *dc = DEVICE_CLASS(klass); |
dd83b06a AF |
410 | CPUClass *k = CPU_CLASS(klass); |
411 | ||
1590bbcb | 412 | k->parse_features = cpu_common_parse_features; |
dd83b06a | 413 | k->reset = cpu_common_reset; |
997395d3 | 414 | k->get_arch_id = cpu_common_get_arch_id; |
8c2e1b00 | 415 | k->has_work = cpu_common_has_work; |
444d5590 | 416 | k->get_paging_enabled = cpu_common_get_paging_enabled; |
a23bbfda | 417 | k->get_memory_mapping = cpu_common_get_memory_mapping; |
c72bf468 JF |
418 | k->write_elf32_qemunote = cpu_common_write_elf32_qemunote; |
419 | k->write_elf32_note = cpu_common_write_elf32_note; | |
420 | k->write_elf64_qemunote = cpu_common_write_elf64_qemunote; | |
421 | k->write_elf64_note = cpu_common_write_elf64_note; | |
5b50e790 AF |
422 | k->gdb_read_register = cpu_common_gdb_read_register; |
423 | k->gdb_write_register = cpu_common_gdb_write_register; | |
bf7663c4 | 424 | k->virtio_is_big_endian = cpu_common_virtio_is_big_endian; |
cffe7b32 | 425 | k->debug_excp_handler = cpu_common_noop; |
568496c0 | 426 | k->debug_check_watchpoint = cpu_common_debug_check_watchpoint; |
cffe7b32 RH |
427 | k->cpu_exec_enter = cpu_common_noop; |
428 | k->cpu_exec_exit = cpu_common_noop; | |
9585db68 | 429 | k->cpu_exec_interrupt = cpu_common_exec_interrupt; |
40612000 | 430 | k->adjust_watchpoint_address = cpu_adjust_watchpoint_address; |
ba31cc72 | 431 | set_bit(DEVICE_CATEGORY_CPU, dc->categories); |
4f658099 | 432 | dc->realize = cpu_common_realizefn; |
7bbc124e | 433 | dc->unrealize = cpu_common_unrealizefn; |
c7e002c5 | 434 | dc->props = cpu_common_props; |
ffa95714 MA |
435 | /* |
436 | * Reason: CPUs still need special care by board code: wiring up | |
437 | * IRQs, adding reset handlers, halting non-first CPUs, ... | |
438 | */ | |
e90f2a8c | 439 | dc->user_creatable = false; |
dd83b06a AF |
440 | } |
441 | ||
961f8395 | 442 | static const TypeInfo cpu_type_info = { |
dd83b06a | 443 | .name = TYPE_CPU, |
961f8395 | 444 | .parent = TYPE_DEVICE, |
dd83b06a | 445 | .instance_size = sizeof(CPUState), |
a0e372f0 | 446 | .instance_init = cpu_common_initfn, |
b7bca733 | 447 | .instance_finalize = cpu_common_finalize, |
dd83b06a AF |
448 | .abstract = true, |
449 | .class_size = sizeof(CPUClass), | |
450 | .class_init = cpu_class_init, | |
451 | }; | |
452 | ||
453 | static void cpu_register_types(void) | |
454 | { | |
455 | type_register_static(&cpu_type_info); | |
456 | } | |
457 | ||
458 | type_init(cpu_register_types) |