[qemu.git] / hw / milkymist-memcard.c

/*
 *  QEMU model of the Milkymist SD Card Controller.
 *
 *  Copyright (c) 2010 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Specification available at:
 *   http://www.milkymist.org/socdoc/memcard.pdf
 */

#include "hw.h"
#include "sysbus.h"
#include "sysemu.h"
#include "trace.h"
#include "qemu-error.h"
#include "blockdev.h"
#include "sd.h"

enum {
    ENABLE_CMD_TX   = (1<<0),
    ENABLE_CMD_RX   = (1<<1),
    ENABLE_DAT_TX   = (1<<2),
    ENABLE_DAT_RX   = (1<<3),
};

enum {
    PENDING_CMD_TX   = (1<<0),
    PENDING_CMD_RX   = (1<<1),
    PENDING_DAT_TX   = (1<<2),
    PENDING_DAT_RX   = (1<<3),
};

enum {
    START_CMD_TX    = (1<<0),
    START_DAT_RX    = (1<<1),
};

enum {
    R_CLK2XDIV = 0,
    R_ENABLE,
    R_PENDING,
    R_START,
    R_CMD,
    R_DAT,
    R_MAX
};

struct MilkymistMemcardState {
    SysBusDevice busdev;
    MemoryRegion regs_region;
    SDState *card;

    int command_write_ptr;
    int response_read_ptr;
    int response_len;
    int ignore_next_cmd;
    int enabled;
    uint8_t command[6];
    uint8_t response[17];
    uint32_t regs[R_MAX];
};
typedef struct MilkymistMemcardState MilkymistMemcardState;

static void update_pending_bits(MilkymistMemcardState *s)
{
    /* transmits are instantaneous, thus tx pending bits are never set */
    s->regs[R_PENDING] = 0;
    /* if rx is enabled the corresponding pending bits are always set */
    if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
        s->regs[R_PENDING] |= PENDING_CMD_RX;
    }
    if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
        s->regs[R_PENDING] |= PENDING_DAT_RX;
    }
}

static void memcard_sd_command(MilkymistMemcardState *s)
{
    SDRequest req;

    req.cmd = s->command[0] & 0x3f;
    req.arg = (s->command[1] << 24) | (s->command[2] << 16)
              | (s->command[3] << 8) | s->command[4];
    req.crc = s->command[5];

    s->response[0] = req.cmd;
    s->response_len = sd_do_command(s->card, &req, s->response+1);
    s->response_read_ptr = 0;

    if (s->response_len == 16) {
        /* R2 response */
        s->response[0] = 0x3f;
        s->response_len += 1;
    } else if (s->response_len == 4) {
        /* no crc calculation, insert dummy byte */
        s->response[5] = 0;
        s->response_len += 2;
    }

    if (req.cmd == 0) {
        /* next write is a dummy byte to clock the initialization of the sd
         * card */
        s->ignore_next_cmd = 1;
    }
}

static uint64_t memcard_read(void *opaque, target_phys_addr_t addr,
                             unsigned size)
{
    MilkymistMemcardState *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr) {
    case R_CMD:
        if (!s->enabled) {
            r = 0xff;
        } else {
            r = s->response[s->response_read_ptr++];
            if (s->response_read_ptr > s->response_len) {
                error_report("milkymist_memcard: "
                        "read more cmd bytes than available. Clipping.");
                s->response_read_ptr = 0;
            }
        }
        break;
    case R_DAT:
        if (!s->enabled) {
            r = 0xffffffff;
        } else {
            r = 0;
            r |= sd_read_data(s->card) << 24;
            r |= sd_read_data(s->card) << 16;
            r |= sd_read_data(s->card) << 8;
            r |= sd_read_data(s->card);
        }
        break;
    case R_CLK2XDIV:
    case R_ENABLE:
    case R_PENDING:
    case R_START:
        r = s->regs[addr];
        break;

    default:
        error_report("milkymist_memcard: read access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }

    trace_milkymist_memcard_memory_read(addr << 2, r);

    return r;
}

static void memcard_write(void *opaque, target_phys_addr_t addr, uint64_t value,
                          unsigned size)
{
    MilkymistMemcardState *s = opaque;

    trace_milkymist_memcard_memory_write(addr, value);

    addr >>= 2;
    switch (addr) {
    case R_PENDING:
        /* clear rx pending bits */
        s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
        update_pending_bits(s);
        break;
    case R_CMD:
        if (!s->enabled) {
            break;
        }
        if (s->ignore_next_cmd) {
            s->ignore_next_cmd = 0;
            break;
        }
        s->command[s->command_write_ptr] = value & 0xff;
        s->command_write_ptr = (s->command_write_ptr + 1) % 6;
        if (s->command_write_ptr == 0) {
            memcard_sd_command(s);
        }
        break;
    case R_DAT:
        if (!s->enabled) {
            break;
        }
        sd_write_data(s->card, (value >> 24) & 0xff);
        sd_write_data(s->card, (value >> 16) & 0xff);
        sd_write_data(s->card, (value >> 8) & 0xff);
        sd_write_data(s->card, value & 0xff);
        break;
    case R_ENABLE:
        s->regs[addr] = value;
        update_pending_bits(s);
        break;
    case R_CLK2XDIV:
    case R_START:
        s->regs[addr] = value;
        break;

    default:
        error_report("milkymist_memcard: write access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }
}

static const MemoryRegionOps memcard_mmio_ops = {
    .read = memcard_read,
    .write = memcard_write,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void milkymist_memcard_reset(DeviceState *d)
{
    MilkymistMemcardState *s =
            container_of(d, MilkymistMemcardState, busdev.qdev);
    int i;

    s->command_write_ptr = 0;
    s->response_read_ptr = 0;
    s->response_len = 0;

    for (i = 0; i < R_MAX; i++) {
        s->regs[i] = 0;
    }
}

static int milkymist_memcard_init(SysBusDevice *dev)
{
    MilkymistMemcardState *s = FROM_SYSBUS(typeof(*s), dev);
    DriveInfo *dinfo;

    dinfo = drive_get_next(IF_SD);
    s->card = sd_init(dinfo ? dinfo->bdrv : NULL, 0);
    s->enabled = dinfo ? bdrv_is_inserted(dinfo->bdrv) : 0;

    memory_region_init_io(&s->regs_region, &memcard_mmio_ops, s,
            "milkymist-memcard", R_MAX * 4);
    sysbus_init_mmio(dev, &s->regs_region);

    return 0;
}

static const VMStateDescription vmstate_milkymist_memcard = {
    .name = "milkymist-memcard",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
        VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
        VMSTATE_INT32(response_len, MilkymistMemcardState),
        VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
        VMSTATE_INT32(enabled, MilkymistMemcardState),
        VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
        VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
        VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
        VMSTATE_END_OF_LIST()
    }
};

static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = milkymist_memcard_init;
    dc->reset = milkymist_memcard_reset;
    dc->vmsd = &vmstate_milkymist_memcard;
}

static TypeInfo milkymist_memcard_info = {
    .name          = "milkymist-memcard",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MilkymistMemcardState),
    .class_init    = milkymist_memcard_class_init,
};

static void milkymist_memcard_register_types(void)
{
    type_register_static(&milkymist_memcard_info);
}

type_init(milkymist_memcard_register_types)
Commit	Line	Data
b4e37d98 MW	1	/*
	2	* QEMU model of the Milkymist SD Card Controller.
	3	*
	4	* Copyright (c) 2010 Michael Walle <[email protected]>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*
	19	*
	20	* Specification available at:
	21	* http://www.milkymist.org/socdoc/memcard.pdf
	22	*/
	23
	24	#include "hw.h"
	25	#include "sysbus.h"
	26	#include "sysemu.h"
	27	#include "trace.h"
	28	#include "qemu-error.h"
	29	#include "blockdev.h"
	30	#include "sd.h"
	31
	32	enum {
	33	ENABLE_CMD_TX = (1<<0),
	34	ENABLE_CMD_RX = (1<<1),
	35	ENABLE_DAT_TX = (1<<2),
	36	ENABLE_DAT_RX = (1<<3),
	37	};
	38
	39	enum {
	40	PENDING_CMD_TX = (1<<0),
	41	PENDING_CMD_RX = (1<<1),
	42	PENDING_DAT_TX = (1<<2),
	43	PENDING_DAT_RX = (1<<3),
	44	};
	45
	46	enum {
	47	START_CMD_TX = (1<<0),
	48	START_DAT_RX = (1<<1),
	49	};
	50
	51	enum {
	52	R_CLK2XDIV = 0,
	53	R_ENABLE,
	54	R_PENDING,
	55	R_START,
	56	R_CMD,
	57	R_DAT,
	58	R_MAX
	59	};
	60
	61	struct MilkymistMemcardState {
	62	SysBusDevice busdev;
8c85d15b	63	MemoryRegion regs_region;
b4e37d98 MW	64	SDState *card;
	65
	66	int command_write_ptr;
	67	int response_read_ptr;
	68	int response_len;
	69	int ignore_next_cmd;
	70	int enabled;
	71	uint8_t command[6];
	72	uint8_t response[17];
	73	uint32_t regs[R_MAX];
	74	};
	75	typedef struct MilkymistMemcardState MilkymistMemcardState;
	76
	77	static void update_pending_bits(MilkymistMemcardState *s)
	78	{
	79	/* transmits are instantaneous, thus tx pending bits are never set */
	80	s->regs[R_PENDING] = 0;
	81	/* if rx is enabled the corresponding pending bits are always set */
	82	if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
	83	s->regs[R_PENDING] \|= PENDING_CMD_RX;
	84	}
	85	if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
	86	s->regs[R_PENDING] \|= PENDING_DAT_RX;
	87	}
	88	}
	89
	90	static void memcard_sd_command(MilkymistMemcardState *s)
	91	{
	92	SDRequest req;
	93
	94	req.cmd = s->command[0] & 0x3f;
	95	req.arg = (s->command[1] << 24) \| (s->command[2] << 16)
	96	\| (s->command[3] << 8) \| s->command[4];
	97	req.crc = s->command[5];
	98
	99	s->response[0] = req.cmd;
	100	s->response_len = sd_do_command(s->card, &req, s->response+1);
	101	s->response_read_ptr = 0;
	102
	103	if (s->response_len == 16) {
	104	/* R2 response */
	105	s->response[0] = 0x3f;
	106	s->response_len += 1;
	107	} else if (s->response_len == 4) {
	108	/* no crc calculation, insert dummy byte */
	109	s->response[5] = 0;
	110	s->response_len += 2;
	111	}
	112
	113	if (req.cmd == 0) {
	114	/* next write is a dummy byte to clock the initialization of the sd
	115	* card */
	116	s->ignore_next_cmd = 1;
	117	}
	118	}
	119
8c85d15b MW	120	static uint64_t memcard_read(void *opaque, target_phys_addr_t addr,
8c85d15b MW	121	unsigned size)
b4e37d98 MW	122	{
	123	MilkymistMemcardState *s = opaque;
	124	uint32_t r = 0;
	125
	126	addr >>= 2;
	127	switch (addr) {
	128	case R_CMD:
	129	if (!s->enabled) {
	130	r = 0xff;
	131	} else {
	132	r = s->response[s->response_read_ptr++];
	133	if (s->response_read_ptr > s->response_len) {
	134	error_report("milkymist_memcard: "
	135	"read more cmd bytes than available. Clipping.");
	136	s->response_read_ptr = 0;
	137	}
	138	}
	139	break;
	140	case R_DAT:
	141	if (!s->enabled) {
	142	r = 0xffffffff;
	143	} else {
	144	r = 0;
	145	r \|= sd_read_data(s->card) << 24;
	146	r \|= sd_read_data(s->card) << 16;
	147	r \|= sd_read_data(s->card) << 8;
	148	r \|= sd_read_data(s->card);
	149	}
	150	break;
	151	case R_CLK2XDIV:
	152	case R_ENABLE:
	153	case R_PENDING:
	154	case R_START:
	155	r = s->regs[addr];
	156	break;
	157
	158	default:
dd3d6775	159	error_report("milkymist_memcard: read access to unknown register 0x"
b4e37d98 MW	160	TARGET_FMT_plx, addr << 2);
	161	break;
	162	}
	163
	164	trace_milkymist_memcard_memory_read(addr << 2, r);
	165
	166	return r;
	167	}
	168
8c85d15b MW	169	static void memcard_write(void *opaque, target_phys_addr_t addr, uint64_t value,
8c85d15b MW	170	unsigned size)
b4e37d98 MW	171	{
	172	MilkymistMemcardState *s = opaque;
	173
	174	trace_milkymist_memcard_memory_write(addr, value);
	175
	176	addr >>= 2;
	177	switch (addr) {
	178	case R_PENDING:
	179	/* clear rx pending bits */
	180	s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX \| PENDING_DAT_RX));
	181	update_pending_bits(s);
	182	break;
	183	case R_CMD:
	184	if (!s->enabled) {
	185	break;
	186	}
	187	if (s->ignore_next_cmd) {
	188	s->ignore_next_cmd = 0;
	189	break;
	190	}
	191	s->command[s->command_write_ptr] = value & 0xff;
	192	s->command_write_ptr = (s->command_write_ptr + 1) % 6;
	193	if (s->command_write_ptr == 0) {
	194	memcard_sd_command(s);
	195	}
	196	break;
	197	case R_DAT:
	198	if (!s->enabled) {
	199	break;
	200	}
	201	sd_write_data(s->card, (value >> 24) & 0xff);
	202	sd_write_data(s->card, (value >> 16) & 0xff);
	203	sd_write_data(s->card, (value >> 8) & 0xff);
	204	sd_write_data(s->card, value & 0xff);
	205	break;
	206	case R_ENABLE:
	207	s->regs[addr] = value;
	208	update_pending_bits(s);
	209	break;
	210	case R_CLK2XDIV:
	211	case R_START:
	212	s->regs[addr] = value;
	213	break;
	214
	215	default:
dd3d6775	216	error_report("milkymist_memcard: write access to unknown register 0x"
b4e37d98 MW	217	TARGET_FMT_plx, addr << 2);
	218	break;
	219	}
	220	}
	221
8c85d15b MW	222	static const MemoryRegionOps memcard_mmio_ops = {
	223	.read = memcard_read,
	224	.write = memcard_write,
	225	.valid = {
	226	.min_access_size = 4,
	227	.max_access_size = 4,
	228	},
	229	.endianness = DEVICE_NATIVE_ENDIAN,
b4e37d98 MW	230	};
	231
	232	static void milkymist_memcard_reset(DeviceState *d)
	233	{
	234	MilkymistMemcardState *s =
	235	container_of(d, MilkymistMemcardState, busdev.qdev);
	236	int i;
	237
	238	s->command_write_ptr = 0;
	239	s->response_read_ptr = 0;
	240	s->response_len = 0;
	241
	242	for (i = 0; i < R_MAX; i++) {
	243	s->regs[i] = 0;
	244	}
	245	}
	246
	247	static int milkymist_memcard_init(SysBusDevice *dev)
	248	{
	249	MilkymistMemcardState s = FROM_SYSBUS(typeof(s), dev);
	250	DriveInfo *dinfo;
b4e37d98 MW	251
	252	dinfo = drive_get_next(IF_SD);
	253	s->card = sd_init(dinfo ? dinfo->bdrv : NULL, 0);
	254	s->enabled = dinfo ? bdrv_is_inserted(dinfo->bdrv) : 0;
	255
8c85d15b MW	256	memory_region_init_io(&s->regs_region, &memcard_mmio_ops, s,
8c85d15b MW	257	"milkymist-memcard", R_MAX * 4);
750ecd44	258	sysbus_init_mmio(dev, &s->regs_region);
b4e37d98 MW	259
	260	return 0;
	261	}
	262
	263	static const VMStateDescription vmstate_milkymist_memcard = {
	264	.name = "milkymist-memcard",
	265	.version_id = 1,
	266	.minimum_version_id = 1,
	267	.minimum_version_id_old = 1,
	268	.fields = (VMStateField[]) {
	269	VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
	270	VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
	271	VMSTATE_INT32(response_len, MilkymistMemcardState),
	272	VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
	273	VMSTATE_INT32(enabled, MilkymistMemcardState),
	274	VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
	275	VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
	276	VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
	277	VMSTATE_END_OF_LIST()
	278	}
	279	};
	280
999e12bb AL	281	static void milkymist_memcard_class_init(ObjectClass klass, void data)
999e12bb AL	282	{
39bffca2	283	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	284	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	285
	286	k->init = milkymist_memcard_init;
39bffca2 AL	287	dc->reset = milkymist_memcard_reset;
39bffca2 AL	288	dc->vmsd = &vmstate_milkymist_memcard;
999e12bb AL	289	}
999e12bb AL	290
39bffca2 AL	291	static TypeInfo milkymist_memcard_info = {
	292	.name = "milkymist-memcard",
	293	.parent = TYPE_SYS_BUS_DEVICE,
	294	.instance_size = sizeof(MilkymistMemcardState),
	295	.class_init = milkymist_memcard_class_init,
b4e37d98 MW	296	};
b4e37d98 MW	297
83f7d43a	298	static void milkymist_memcard_register_types(void)
b4e37d98	299	{
39bffca2	300	type_register_static(&milkymist_memcard_info);
b4e37d98 MW	301	}
b4e37d98 MW	302
83f7d43a	303	type_init(milkymist_memcard_register_types)