[qemu.git] / hw / ioh3420.c

/*
 * ioh3420.c
 * Intel X58 north bridge IOH
 * PCI Express root port device id 3420
 *
 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
 *                    VA Linux Systems Japan K.K.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "pci_ids.h"
#include "msi.h"
#include "pcie.h"
#include "ioh3420.h"

#define PCI_DEVICE_ID_IOH_EPORT         0x3420  /* D0:F0 express mode */
#define PCI_DEVICE_ID_IOH_REV           0x2
#define IOH_EP_SSVID_OFFSET             0x40
#define IOH_EP_SSVID_SVID               PCI_VENDOR_ID_INTEL
#define IOH_EP_SSVID_SSID               0
#define IOH_EP_MSI_OFFSET               0x60
#define IOH_EP_MSI_SUPPORTED_FLAGS      PCI_MSI_FLAGS_MASKBIT
#define IOH_EP_MSI_NR_VECTOR            2
#define IOH_EP_EXP_OFFSET               0x90
#define IOH_EP_AER_OFFSET               0x100

/*
 * If two MSI vector are allocated, Advanced Error Interrupt Message Number
 * is 1. otherwise 0.
 * 17.12.5.10 RPERRSTS,  32:27 bit Advanced Error Interrupt Message Number.
 */
static uint8_t ioh3420_aer_vector(const PCIDevice *d)
{
    switch (msi_nr_vectors_allocated(d)) {
    case 1:
        return 0;
    case 2:
        return 1;
    case 4:
    case 8:
    case 16:
    case 32:
    default:
        break;
    }
    abort();
    return 0;
}

static void ioh3420_aer_vector_update(PCIDevice *d)
{
    pcie_aer_root_set_vector(d, ioh3420_aer_vector(d));
}

static void ioh3420_write_config(PCIDevice *d,
                                   uint32_t address, uint32_t val, int len)
{
    uint32_t root_cmd =
        pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);

    pci_bridge_write_config(d, address, val, len);
    msi_write_config(d, address, val, len);
    ioh3420_aer_vector_update(d);
    pcie_cap_slot_write_config(d, address, val, len);
    pcie_aer_write_config(d, address, val, len);
    pcie_aer_root_write_config(d, address, val, len, root_cmd);
}

static void ioh3420_reset(DeviceState *qdev)
{
    PCIDevice *d = PCI_DEVICE(qdev);
    msi_reset(d);
    ioh3420_aer_vector_update(d);
    pcie_cap_root_reset(d);
    pcie_cap_deverr_reset(d);
    pcie_cap_slot_reset(d);
    pcie_aer_root_reset(d);
    pci_bridge_reset(qdev);
    pci_bridge_disable_base_limit(d);
}

static int ioh3420_initfn(PCIDevice *d)
{
    PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
    PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
    PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
    int rc;
    int tmp;

    rc = pci_bridge_initfn(d);
    if (rc < 0) {
        return rc;
    }

    pcie_port_init_reg(d);

    rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
                               IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
    if (rc < 0) {
        goto err_bridge;
    }
    rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
                  IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
                  IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
    if (rc < 0) {
        goto err_bridge;
    }
    rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port);
    if (rc < 0) {
        goto err_msi;
    }
    pcie_cap_deverr_init(d);
    pcie_cap_slot_init(d, s->slot);
    pcie_chassis_create(s->chassis);
    rc = pcie_chassis_add_slot(s);
    if (rc < 0) {
        goto err_pcie_cap;
        return rc;
    }
    pcie_cap_root_init(d);
    rc = pcie_aer_init(d, IOH_EP_AER_OFFSET);
    if (rc < 0) {
        goto err;
    }
    pcie_aer_root_init(d);
    ioh3420_aer_vector_update(d);
    return 0;

err:
    pcie_chassis_del_slot(s);
err_pcie_cap:
    pcie_cap_exit(d);
err_msi:
    msi_uninit(d);
err_bridge:
    tmp = pci_bridge_exitfn(d);
    assert(!tmp);
    return rc;
}

static int ioh3420_exitfn(PCIDevice *d)
{
    PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
    PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
    PCIESlot *s = DO_UPCAST(PCIESlot, port, p);

    pcie_aer_exit(d);
    pcie_chassis_del_slot(s);
    pcie_cap_exit(d);
    msi_uninit(d);
    return pci_bridge_exitfn(d);
}

PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,
                         const char *bus_name, pci_map_irq_fn map_irq,
                         uint8_t port, uint8_t chassis, uint16_t slot)
{
    PCIDevice *d;
    PCIBridge *br;
    DeviceState *qdev;

    d = pci_create_multifunction(bus, devfn, multifunction, "ioh3420");
    if (!d) {
        return NULL;
    }
    br = DO_UPCAST(PCIBridge, dev, d);

    qdev = &br->dev.qdev;
    pci_bridge_map_irq(br, bus_name, map_irq);
    qdev_prop_set_uint8(qdev, "port", port);
    qdev_prop_set_uint8(qdev, "chassis", chassis);
    qdev_prop_set_uint16(qdev, "slot", slot);
    qdev_init_nofail(qdev);

    return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
}

static const VMStateDescription vmstate_ioh3420 = {
    .name = "ioh-3240-express-root-port",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = pcie_cap_slot_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
        VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
                       vmstate_pcie_aer_log, PCIEAERLog),
        VMSTATE_END_OF_LIST()
    }
};

static Property ioh3420_properties[] = {
    DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
    DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
    DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
    DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
    port.br.dev.exp.aer_log.log_max,
    PCIE_AER_LOG_MAX_DEFAULT),
    DEFINE_PROP_END_OF_LIST(),
};

static void ioh3420_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->is_express = 1;
    k->is_bridge = 1;
    k->config_write = ioh3420_write_config;
    k->init = ioh3420_initfn;
    k->exit = ioh3420_exitfn;
    k->vendor_id = PCI_VENDOR_ID_INTEL;
    k->device_id = PCI_DEVICE_ID_IOH_EPORT;
    k->revision = PCI_DEVICE_ID_IOH_REV;
    dc->desc = "Intel IOH device id 3420 PCIE Root Port";
    dc->reset = ioh3420_reset;
    dc->vmsd = &vmstate_ioh3420;
    dc->props = ioh3420_properties;
}

static TypeInfo ioh3420_info = {
    .name          = "ioh3420",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIESlot),
    .class_init    = ioh3420_class_init,
};

static void ioh3420_register_types(void)
{
    type_register_static(&ioh3420_info);
}

type_init(ioh3420_register_types)

/*
 * Local variables:
 *  c-indent-level: 4
 *  c-basic-offset: 4
 *  tab-width: 8
 *  indent-tab-mode: nil
 * End:
 */
Commit	Line	Data
8135aeed IY	1	/*
	2	* ioh3420.c
	3	* Intel X58 north bridge IOH
	4	* PCI Express root port device id 3420
	5	*
	6	* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
	7	* VA Linux Systems Japan K.K.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along
	20	* with this program; if not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
	23	#include "pci_ids.h"
	24	#include "msi.h"
	25	#include "pcie.h"
	26	#include "ioh3420.h"
	27
	28	#define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */
	29	#define PCI_DEVICE_ID_IOH_REV 0x2
	30	#define IOH_EP_SSVID_OFFSET 0x40
	31	#define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL
	32	#define IOH_EP_SSVID_SSID 0
	33	#define IOH_EP_MSI_OFFSET 0x60
	34	#define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT
	35	#define IOH_EP_MSI_NR_VECTOR 2
	36	#define IOH_EP_EXP_OFFSET 0x90
	37	#define IOH_EP_AER_OFFSET 0x100
	38
61620c2f IY	39	/*
	40	* If two MSI vector are allocated, Advanced Error Interrupt Message Number
	41	* is 1. otherwise 0.
	42	* 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number.
	43	*/
	44	static uint8_t ioh3420_aer_vector(const PCIDevice *d)
	45	{
	46	switch (msi_nr_vectors_allocated(d)) {
	47	case 1:
	48	return 0;
	49	case 2:
	50	return 1;
	51	case 4:
	52	case 8:
	53	case 16:
	54	case 32:
	55	default:
	56	break;
	57	}
	58	abort();
	59	return 0;
	60	}
	61
	62	static void ioh3420_aer_vector_update(PCIDevice *d)
	63	{
	64	pcie_aer_root_set_vector(d, ioh3420_aer_vector(d));
	65	}
	66
8135aeed IY	67	static void ioh3420_write_config(PCIDevice *d,
	68	uint32_t address, uint32_t val, int len)
	69	{
61620c2f IY	70	uint32_t root_cmd =
	71	pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
	72
8135aeed IY	73	pci_bridge_write_config(d, address, val, len);
8135aeed IY	74	msi_write_config(d, address, val, len);
61620c2f	75	ioh3420_aer_vector_update(d);
6bde6aaa	76	pcie_cap_slot_write_config(d, address, val, len);
61620c2f IY	77	pcie_aer_write_config(d, address, val, len);
61620c2f IY	78	pcie_aer_root_write_config(d, address, val, len, root_cmd);
8135aeed IY	79	}
	80
	81	static void ioh3420_reset(DeviceState *qdev)
	82	{
40021f08	83	PCIDevice *d = PCI_DEVICE(qdev);
8135aeed	84	msi_reset(d);
61620c2f	85	ioh3420_aer_vector_update(d);
8135aeed IY	86	pcie_cap_root_reset(d);
	87	pcie_cap_deverr_reset(d);
	88	pcie_cap_slot_reset(d);
61620c2f	89	pcie_aer_root_reset(d);
8135aeed IY	90	pci_bridge_reset(qdev);
8135aeed IY	91	pci_bridge_disable_base_limit(d);
8135aeed IY	92	}
	93
	94	static int ioh3420_initfn(PCIDevice *d)
	95	{
	96	PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
	97	PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
	98	PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
	99	int rc;
61620c2f	100	int tmp;
8135aeed IY	101
	102	rc = pci_bridge_initfn(d);
	103	if (rc < 0) {
	104	return rc;
	105	}
	106
8135aeed IY	107	pcie_port_init_reg(d);
8135aeed IY	108
8135aeed IY	109	rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
	110	IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
	111	if (rc < 0) {
61620c2f	112	goto err_bridge;
8135aeed IY	113	}
	114	rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
	115	IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
	116	IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
	117	if (rc < 0) {
61620c2f	118	goto err_bridge;
8135aeed IY	119	}
	120	rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port);
	121	if (rc < 0) {
61620c2f	122	goto err_msi;
8135aeed IY	123	}
	124	pcie_cap_deverr_init(d);
	125	pcie_cap_slot_init(d, s->slot);
	126	pcie_chassis_create(s->chassis);
	127	rc = pcie_chassis_add_slot(s);
	128	if (rc < 0) {
61620c2f	129	goto err_pcie_cap;
8135aeed IY	130	return rc;
	131	}
	132	pcie_cap_root_init(d);
61620c2f IY	133	rc = pcie_aer_init(d, IOH_EP_AER_OFFSET);
	134	if (rc < 0) {
	135	goto err;
	136	}
	137	pcie_aer_root_init(d);
	138	ioh3420_aer_vector_update(d);
8135aeed	139	return 0;
61620c2f IY	140
	141	err:
	142	pcie_chassis_del_slot(s);
	143	err_pcie_cap:
	144	pcie_cap_exit(d);
	145	err_msi:
	146	msi_uninit(d);
	147	err_bridge:
	148	tmp = pci_bridge_exitfn(d);
	149	assert(!tmp);
	150	return rc;
8135aeed IY	151	}
	152
	153	static int ioh3420_exitfn(PCIDevice *d)
	154	{
61620c2f IY	155	PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
	156	PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
	157	PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
	158
	159	pcie_aer_exit(d);
	160	pcie_chassis_del_slot(s);
8135aeed	161	pcie_cap_exit(d);
61620c2f	162	msi_uninit(d);
8135aeed IY	163	return pci_bridge_exitfn(d);
	164	}
	165
	166	PCIESlot ioh3420_init(PCIBus bus, int devfn, bool multifunction,
	167	const char *bus_name, pci_map_irq_fn map_irq,
	168	uint8_t port, uint8_t chassis, uint16_t slot)
	169	{
	170	PCIDevice *d;
	171	PCIBridge *br;
	172	DeviceState *qdev;
	173
	174	d = pci_create_multifunction(bus, devfn, multifunction, "ioh3420");
	175	if (!d) {
	176	return NULL;
	177	}
	178	br = DO_UPCAST(PCIBridge, dev, d);
	179
	180	qdev = &br->dev.qdev;
	181	pci_bridge_map_irq(br, bus_name, map_irq);
	182	qdev_prop_set_uint8(qdev, "port", port);
	183	qdev_prop_set_uint8(qdev, "chassis", chassis);
	184	qdev_prop_set_uint16(qdev, "slot", slot);
	185	qdev_init_nofail(qdev);
	186
	187	return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
	188	}
	189
	190	static const VMStateDescription vmstate_ioh3420 = {
	191	.name = "ioh-3240-express-root-port",
	192	.version_id = 1,
	193	.minimum_version_id = 1,
	194	.minimum_version_id_old = 1,
6bde6aaa	195	.post_load = pcie_cap_slot_post_load,
8135aeed IY	196	.fields = (VMStateField[]) {
8135aeed IY	197	VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
61620c2f IY	198	VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
61620c2f IY	199	vmstate_pcie_aer_log, PCIEAERLog),
8135aeed IY	200	VMSTATE_END_OF_LIST()
	201	}
	202	};
	203
40021f08 AL	204	static Property ioh3420_properties[] = {
	205	DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
	206	DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
	207	DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
	208	DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
	209	port.br.dev.exp.aer_log.log_max,
	210	PCIE_AER_LOG_MAX_DEFAULT),
	211	DEFINE_PROP_END_OF_LIST(),
	212	};
	213
	214	static void ioh3420_class_init(ObjectClass klass, void data)
	215	{
39bffca2	216	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	217	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	218
	219	k->is_express = 1;
	220	k->is_bridge = 1;
	221	k->config_write = ioh3420_write_config;
	222	k->init = ioh3420_initfn;
	223	k->exit = ioh3420_exitfn;
	224	k->vendor_id = PCI_VENDOR_ID_INTEL;
	225	k->device_id = PCI_DEVICE_ID_IOH_EPORT;
	226	k->revision = PCI_DEVICE_ID_IOH_REV;
39bffca2 AL	227	dc->desc = "Intel IOH device id 3420 PCIE Root Port";
	228	dc->reset = ioh3420_reset;
	229	dc->vmsd = &vmstate_ioh3420;
	230	dc->props = ioh3420_properties;
40021f08 AL	231	}
40021f08 AL	232
39bffca2 AL	233	static TypeInfo ioh3420_info = {
	234	.name = "ioh3420",
	235	.parent = TYPE_PCI_DEVICE,
	236	.instance_size = sizeof(PCIESlot),
	237	.class_init = ioh3420_class_init,
8135aeed IY	238	};
8135aeed IY	239
83f7d43a	240	static void ioh3420_register_types(void)
8135aeed	241	{
39bffca2	242	type_register_static(&ioh3420_info);
8135aeed IY	243	}
8135aeed IY	244
83f7d43a	245	type_init(ioh3420_register_types)
8135aeed IY	246
	247	/*
	248	* Local variables:
	249	* c-indent-level: 4
	250	* c-basic-offset: 4
	251	* tab-width: 8
	252	* indent-tab-mode: nil
	253	* End:
	254	*/