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Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
[qemu.git] / target / arm / vfp.decode
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78e138bc
PM		 1# AArch32 VFP instruction descriptions (conditional insns)
2#
3# Copyright (c) 2019 Linaro, Ltd
4#
5# This library is free software; you can redistribute it and/or
6# modify it under the terms of the GNU Lesser General Public
7# License as published by the Free Software Foundation; either
8# version 2 of the License, or (at your option) any later version.
9#
10# This library is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13# Lesser General Public License for more details.
14#
15# You should have received a copy of the GNU Lesser General Public
16# License along with this library; if not, see <http://www.gnu.org/licenses/>.
17
18#
19# This file is processed by scripts/decodetree.py
20#
21# Encodings for the conditional VFP instructions are here:
22# generally anything matching A32
23# cccc 11.. .... .... .... 101. .... ....
24# and T32
25# 1110 110. .... .... .... 101. .... ....
26# 1110 1110 .... .... .... 101. .... ....
27# (but those patterns might also cover some Neon instructions,
28# which do not live in this file.)
9851ed92
PM		 29
30# VFP registers have an odd encoding with a four-bit field
31# and a one-bit field which are assembled in different orders
32# depending on whether the register is double or single precision.
33# Each individual instruction function must do the checks for
34# "double register selected but CPU does not have double support"
35# and "double register number has bit 4 set but CPU does not
36# support D16-D31" (which should UNDEF).
37%vm_dp 5:1 0:4
38%vm_sp 0:4 5:1
39%vn_dp 7:1 16:4
40%vn_sp 16:4 7:1
41%vd_dp 22:1 12:4
42%vd_sp 12:4 22:1
43
44%vmov_idx_b 21:1 5:2
45%vmov_idx_h 21:1 6:1
46
9bee50b4
PM		 47%vmov_imm 16:4 0:4
48
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RH		 49@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
50@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
51
52@vfp_dm_ss ................................ vm=%vm_sp vd=%vd_sp
53@vfp_dm_dd ................................ vm=%vm_dp vd=%vd_dp
54@vfp_dm_ds ................................ vm=%vm_sp vd=%vd_dp
55@vfp_dm_sd ................................ vm=%vm_dp vd=%vd_sp
56
9851ed92
PM		 57# VMOV scalar to general-purpose register; note that this does
58# include some Neon cases.
59VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \
60 vn=%vn_dp size=0 index=%vmov_idx_b
61VMOV_to_gp ---- 1110 u:1 0. 1 .... rt:4 1011 ..1 1 0000 \
62 vn=%vn_dp size=1 index=%vmov_idx_h
63VMOV_to_gp ---- 1110 0 0 index:1 1 .... rt:4 1011 .00 1 0000 \
64 vn=%vn_dp size=2 u=0
65
66VMOV_from_gp ---- 1110 0 1. 0 .... rt:4 1011 ... 1 0000 \
67 vn=%vn_dp size=0 index=%vmov_idx_b
68VMOV_from_gp ---- 1110 0 0. 0 .... rt:4 1011 ..1 1 0000 \
69 vn=%vn_dp size=1 index=%vmov_idx_h
70VMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1 0000 \
71 vn=%vn_dp size=2
72
73VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \
74 vn=%vn_dp
a9ab5001
PM		 75
76VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
906b60fa 77VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp
81f68110 78
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RH		 79VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp
80VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp
79b02a3b
PM		 81
82# Note that the half-precision variants of VLDR and VSTR are
83# not part of this decodetree at all because they have bits [9:8] == 0b01
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RH		 84VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp
85VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp
fa288de2
PM		 86
87# We split the load/store multiple up into two patterns to avoid
88# overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
89# grouping:
90# P=0 U=0 W=0 is 64-bit VMOV
91# P=1 W=0 is VLDR/VSTR
92# P=U W=1 is UNDEF
93# leaving P=0 U=1 W=x and P=1 U=0 W=1 for load/store multiple.
94# These include FSTM/FLDM.
95VLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \
96 vd=%vd_sp p=0 u=1
97VLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \
98 vd=%vd_dp p=0 u=1
99
100VLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \
101 vd=%vd_sp p=1 u=0 w=1
102VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
103 vd=%vd_dp p=1 u=0 w=1
266bd25c
PM		 104
105# 3-register VFP data-processing; bits [23,21:20,6] identify the operation.
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RH		 106VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s
107VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d
108
109VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s
110VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d
111
112VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s
113VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d
114
115VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s
116VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d
117
118VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s
119VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d
120
121VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s
122VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d
123
124VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s
125VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d
126
127VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s
128VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d
129
130VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
131VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
d4893b01 132
d486f830
RH		 133VFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s
134VFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s
135VFNMA_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s
136VFNMS_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s
137
138VFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d
139VFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d
140VFNMA_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d
141VFNMS_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d
b518c753 142
9bee50b4
PM		 143VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \
144 vd=%vd_sp imm=%vmov_imm
145VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \
146 vd=%vd_dp imm=%vmov_imm
90287e22 147
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RH		 148VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss
149VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd
17552b97 150
906b60fa
RH		 151VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss
152VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd
1882651a 153
906b60fa
RH		 154VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss
155VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd
b8474540 156
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RH		 157VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss
158VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd
386bba23
PM		 159
160VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \
161 vd=%vd_sp vm=%vm_sp
162VCMP_dp ---- 1110 1.11 010 z:1 .... 1011 e:1 1.0 .... \
163 vd=%vd_dp vm=%vm_dp
b623d803
PM		 164
165# VCVTT and VCVTB from f16: Vd format depends on size bit; Vm is always vm_sp
166VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \
167 vd=%vd_sp vm=%vm_sp
168VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \
169 vd=%vd_dp vm=%vm_sp
cdfd14e8 170
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RH		 171# VCVTB and VCVTT to f16: Vd format is always vd_sp;
172# Vm format depends on size bit
cdfd14e8
PM		 173VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \
174 vd=%vd_sp vm=%vm_sp
175VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \
176 vd=%vd_sp vm=%vm_dp
e25155f5 177
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RH		 178VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss
179VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd
e25155f5 180
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RH		 181VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss
182VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd
e25155f5 183
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RH		 184VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss
185VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd
6ed7e49c 186
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RH		 187# VCVT between single and double:
188# Vm precision depends on size; Vd is its reverse
189VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds
190VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd
8fc9d891
PM		 191
192# VCVT from integer to floating point: Vm always single; Vd depends on size
193VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \
194 vd=%vd_sp vm=%vm_sp
195VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \
196 vd=%vd_dp vm=%vm_sp
92073e94
PM		 197
198# VJCVT is always dp to sp
906b60fa 199VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd
e3d6f429
PM		 200
201# VCVT between floating-point and fixed-point. The immediate value
202# is in the same format as a Vm single-precision register number.
203# We assemble bits 18 (op), 16 (u) and 7 (sx) into a single opc field
204# for the convenience of the trans_VCVT_fix functions.
205%vcvt_fix_op 18:1 16:1 7:1
206VCVT_fix_sp ---- 1110 1.11 1.1. .... 1010 .1.0 .... \
207 vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
208VCVT_fix_dp ---- 1110 1.11 1.1. .... 1011 .1.0 .... \
209 vd=%vd_dp imm=%vm_sp opc=%vcvt_fix_op
3111bfc2
PM		 210
211# VCVT float to integer (VCVT and VCVTR): Vd always single; Vd depends on size
212VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \
213 vd=%vd_sp vm=%vm_sp
214VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \
215 vd=%vd_sp vm=%vm_dp
dc778a68
RH		 216
217VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
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