]>
Commit | Line | Data |
---|---|---|
eb035b48 PM |
1 | /* |
2 | * QEMU KVM support -- ARM specific functions. | |
3 | * | |
4 | * Copyright (c) 2012 Linaro Limited | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
7 | * See the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
11 | #ifndef QEMU_KVM_ARM_H | |
12 | #define QEMU_KVM_ARM_H | |
13 | ||
14 | #include "sysemu/kvm.h" | |
15 | #include "exec/memory.h" | |
1b20616f | 16 | #include "qemu/error-report.h" |
eb035b48 | 17 | |
d45efe47 EA |
18 | #define KVM_ARM_VGIC_V2 (1 << 0) |
19 | #define KVM_ARM_VGIC_V3 (1 << 1) | |
20 | ||
228d5e04 PS |
21 | /** |
22 | * kvm_arm_vcpu_init: | |
23 | * @cs: CPUState | |
24 | * | |
25 | * Initialize (or reinitialize) the VCPU by invoking the | |
26 | * KVM_ARM_VCPU_INIT ioctl with the CPU type and feature | |
27 | * bitmask specified in the CPUState. | |
28 | * | |
29 | * Returns: 0 if success else < 0 error code | |
30 | */ | |
31 | int kvm_arm_vcpu_init(CPUState *cs); | |
32 | ||
14e99e0f | 33 | /** |
d1ebbc9d | 34 | * kvm_arm_vcpu_finalize: |
14e99e0f | 35 | * @cs: CPUState |
d1ebbc9d | 36 | * @feature: feature to finalize |
14e99e0f AJ |
37 | * |
38 | * Finalizes the configuration of the specified VCPU feature by | |
39 | * invoking the KVM_ARM_VCPU_FINALIZE ioctl. Features requiring | |
40 | * this are documented in the "KVM_ARM_VCPU_FINALIZE" section of | |
41 | * KVM's API documentation. | |
42 | * | |
43 | * Returns: 0 if success else < 0 error code | |
44 | */ | |
45 | int kvm_arm_vcpu_finalize(CPUState *cs, int feature); | |
46 | ||
eb035b48 PM |
47 | /** |
48 | * kvm_arm_register_device: | |
49 | * @mr: memory region for this device | |
50 | * @devid: the KVM device ID | |
1da41cc1 CD |
51 | * @group: device control API group for setting addresses |
52 | * @attr: device control API address type | |
53 | * @dev_fd: device control device file descriptor (or -1 if not supported) | |
19d1bd0b | 54 | * @addr_ormask: value to be OR'ed with resolved address |
eb035b48 PM |
55 | * |
56 | * Remember the memory region @mr, and when it is mapped by the | |
57 | * machine model, tell the kernel that base address using the | |
1da41cc1 CD |
58 | * KVM_ARM_SET_DEVICE_ADDRESS ioctl or the newer device control API. @devid |
59 | * should be the ID of the device as defined by KVM_ARM_SET_DEVICE_ADDRESS or | |
60 | * the arm-vgic device in the device control API. | |
61 | * The machine model may map | |
62 | * and unmap the device multiple times; the kernel will only be told the final | |
63 | * address at the point where machine init is complete. | |
eb035b48 | 64 | */ |
1da41cc1 | 65 | void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid, uint64_t group, |
19d1bd0b | 66 | uint64_t attr, int dev_fd, uint64_t addr_ormask); |
eb035b48 | 67 | |
38df27c8 AB |
68 | /** |
69 | * kvm_arm_init_cpreg_list: | |
c8a44709 | 70 | * @cpu: ARMCPU |
38df27c8 | 71 | * |
c8a44709 | 72 | * Initialize the ARMCPU cpreg list according to the kernel's |
38df27c8 AB |
73 | * definition of what CPU registers it knows about (and throw away |
74 | * the previous TCG-created cpreg list). | |
75 | * | |
76 | * Returns: 0 if success, else < 0 error code | |
77 | */ | |
78 | int kvm_arm_init_cpreg_list(ARMCPU *cpu); | |
79 | ||
80 | /** | |
d1ebbc9d AJ |
81 | * kvm_arm_reg_syncs_via_cpreg_list: |
82 | * @regidx: KVM register index | |
38df27c8 AB |
83 | * |
84 | * Return true if this KVM register should be synchronized via the | |
85 | * cpreg list of arbitrary system registers, false if it is synchronized | |
86 | * by hand using code in kvm_arch_get/put_registers(). | |
87 | */ | |
88 | bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx); | |
89 | ||
4b7a6bf4 | 90 | /** |
d1ebbc9d AJ |
91 | * kvm_arm_cpreg_level: |
92 | * @regidx: KVM register index | |
4b7a6bf4 CD |
93 | * |
94 | * Return the level of this coprocessor/system register. Return value is | |
95 | * either KVM_PUT_RUNTIME_STATE, KVM_PUT_RESET_STATE, or KVM_PUT_FULL_STATE. | |
96 | */ | |
97 | int kvm_arm_cpreg_level(uint64_t regidx); | |
98 | ||
ff047453 PM |
99 | /** |
100 | * write_list_to_kvmstate: | |
101 | * @cpu: ARMCPU | |
4b7a6bf4 | 102 | * @level: the state level to sync |
ff047453 PM |
103 | * |
104 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
105 | * its value from the cpreg_values list into the kernel (via ioctl). | |
106 | * This updates KVM's working data structures from TCG data or | |
107 | * from incoming migration state. | |
108 | * | |
109 | * Returns: true if all register values were updated correctly, | |
110 | * false if some register was unknown to the kernel or could not | |
111 | * be written (eg constant register with the wrong value). | |
112 | * Note that we do not stop early on failure -- we will attempt | |
113 | * writing all registers in the list. | |
114 | */ | |
4b7a6bf4 | 115 | bool write_list_to_kvmstate(ARMCPU *cpu, int level); |
ff047453 PM |
116 | |
117 | /** | |
118 | * write_kvmstate_to_list: | |
119 | * @cpu: ARMCPU | |
120 | * | |
121 | * For each register listed in the ARMCPU cpreg_indexes list, write | |
122 | * its value from the kernel into the cpreg_values list. This is used to | |
123 | * copy info from KVM's working data structures into TCG or | |
124 | * for outbound migration. | |
125 | * | |
126 | * Returns: true if all register values were read correctly, | |
127 | * false if some register was unknown or could not be read. | |
128 | * Note that we do not stop early on failure -- we will attempt | |
129 | * reading all registers in the list. | |
130 | */ | |
131 | bool write_kvmstate_to_list(ARMCPU *cpu); | |
132 | ||
e5ac4200 AJ |
133 | /** |
134 | * kvm_arm_cpu_pre_save: | |
135 | * @cpu: ARMCPU | |
136 | * | |
137 | * Called after write_kvmstate_to_list() from cpu_pre_save() to update | |
138 | * the cpreg list with KVM CPU state. | |
139 | */ | |
140 | void kvm_arm_cpu_pre_save(ARMCPU *cpu); | |
141 | ||
142 | /** | |
143 | * kvm_arm_cpu_post_load: | |
144 | * @cpu: ARMCPU | |
145 | * | |
146 | * Called from cpu_post_load() to update KVM CPU state from the cpreg list. | |
147 | */ | |
148 | void kvm_arm_cpu_post_load(ARMCPU *cpu); | |
149 | ||
50a2c6e5 PB |
150 | /** |
151 | * kvm_arm_reset_vcpu: | |
152 | * @cpu: ARMCPU | |
153 | * | |
154 | * Called at reset time to kernel registers to their initial values. | |
155 | */ | |
156 | void kvm_arm_reset_vcpu(ARMCPU *cpu); | |
157 | ||
202ccb6b DG |
158 | /** |
159 | * kvm_arm_init_serror_injection: | |
160 | * @cs: CPUState | |
161 | * | |
162 | * Check whether KVM can set guest SError syndrome. | |
163 | */ | |
164 | void kvm_arm_init_serror_injection(CPUState *cs); | |
165 | ||
166 | /** | |
167 | * kvm_get_vcpu_events: | |
168 | * @cpu: ARMCPU | |
169 | * | |
170 | * Get VCPU related state from kvm. | |
d1ebbc9d AJ |
171 | * |
172 | * Returns: 0 if success else < 0 error code | |
202ccb6b DG |
173 | */ |
174 | int kvm_get_vcpu_events(ARMCPU *cpu); | |
175 | ||
176 | /** | |
177 | * kvm_put_vcpu_events: | |
178 | * @cpu: ARMCPU | |
179 | * | |
180 | * Put VCPU related state to kvm. | |
d1ebbc9d AJ |
181 | * |
182 | * Returns: 0 if success else < 0 error code | |
202ccb6b DG |
183 | */ |
184 | int kvm_put_vcpu_events(ARMCPU *cpu); | |
185 | ||
a96c0514 PM |
186 | #ifdef CONFIG_KVM |
187 | /** | |
188 | * kvm_arm_create_scratch_host_vcpu: | |
189 | * @cpus_to_try: array of QEMU_KVM_ARM_TARGET_* values (terminated with | |
190 | * QEMU_KVM_ARM_TARGET_NONE) to try as fallback if the kernel does not | |
2f340e9c PX |
191 | * know the PREFERRED_TARGET ioctl. Passing NULL is the same as passing |
192 | * an empty array. | |
a96c0514 | 193 | * @fdarray: filled in with kvmfd, vmfd, cpufd file descriptors in that order |
2f340e9c PX |
194 | * @init: filled in with the necessary values for creating a host |
195 | * vcpu. If NULL is provided, will not init the vCPU (though the cpufd | |
196 | * will still be set up). | |
a96c0514 PM |
197 | * |
198 | * Create a scratch vcpu in its own VM of the type preferred by the host | |
199 | * kernel (as would be used for '-cpu host'), for purposes of probing it | |
200 | * for capabilities. | |
201 | * | |
202 | * Returns: true on success (and fdarray and init are filled in), | |
203 | * false on failure (and fdarray and init are not valid). | |
204 | */ | |
205 | bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try, | |
206 | int *fdarray, | |
207 | struct kvm_vcpu_init *init); | |
208 | ||
209 | /** | |
210 | * kvm_arm_destroy_scratch_host_vcpu: | |
211 | * @fdarray: array of fds as set up by kvm_arm_create_scratch_host_vcpu | |
212 | * | |
213 | * Tear down the scratch vcpu created by kvm_arm_create_scratch_host_vcpu. | |
214 | */ | |
215 | void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); | |
216 | ||
217 | #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU | |
a96c0514 | 218 | |
c4487d76 PM |
219 | /** |
220 | * ARMHostCPUFeatures: information about the host CPU (identified | |
221 | * by asking the host kernel) | |
222 | */ | |
223 | typedef struct ARMHostCPUFeatures { | |
4674097c | 224 | ARMISARegisters isar; |
a96c0514 PM |
225 | uint64_t features; |
226 | uint32_t target; | |
227 | const char *dtb_compatible; | |
c4487d76 | 228 | } ARMHostCPUFeatures; |
a96c0514 PM |
229 | |
230 | /** | |
231 | * kvm_arm_get_host_cpu_features: | |
d1ebbc9d | 232 | * @ahcf: ARMHostCPUClass to fill in |
a96c0514 PM |
233 | * |
234 | * Probe the capabilities of the host kernel's preferred CPU and fill | |
235 | * in the ARMHostCPUClass struct accordingly. | |
d1ebbc9d AJ |
236 | * |
237 | * Returns true on success and false otherwise. | |
a96c0514 | 238 | */ |
c4487d76 | 239 | bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf); |
a96c0514 | 240 | |
6fa8a379 AJ |
241 | /** |
242 | * kvm_arm_sve_get_vls: | |
243 | * @cs: CPUState | |
244 | * @map: bitmap to fill in | |
245 | * | |
246 | * Get all the SVE vector lengths supported by the KVM host, setting | |
247 | * the bits corresponding to their length in quadwords minus one | |
248 | * (vq - 1) in @map up to ARM_MAX_VQ. | |
249 | */ | |
250 | void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map); | |
251 | ||
c4487d76 PM |
252 | /** |
253 | * kvm_arm_set_cpu_features_from_host: | |
254 | * @cpu: ARMCPU to set the features for | |
255 | * | |
256 | * Set up the ARMCPU struct fields up to match the information probed | |
257 | * from the host CPU. | |
258 | */ | |
259 | void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); | |
1a1753f7 | 260 | |
dea101a1 AJ |
261 | /** |
262 | * kvm_arm_add_vcpu_properties: | |
263 | * @obj: The CPU object to add the properties to | |
264 | * | |
265 | * Add all KVM specific CPU properties to the CPU object. These | |
266 | * are the CPU properties with "kvm-" prefixed names. | |
267 | */ | |
268 | void kvm_arm_add_vcpu_properties(Object *obj); | |
269 | ||
b9e758f0 AJ |
270 | /** |
271 | * kvm_arm_aarch32_supported: | |
272 | * @cs: CPUState | |
273 | * | |
274 | * Returns: true if the KVM VCPU can enable AArch32 mode | |
275 | * and false otherwise. | |
276 | */ | |
277 | bool kvm_arm_aarch32_supported(CPUState *cs); | |
278 | ||
ae502508 | 279 | /** |
d1ebbc9d | 280 | * kvm_arm_pmu_supported: |
ae502508 AJ |
281 | * @cs: CPUState |
282 | * | |
283 | * Returns: true if the KVM VCPU can enable its PMU | |
284 | * and false otherwise. | |
285 | */ | |
286 | bool kvm_arm_pmu_supported(CPUState *cs); | |
287 | ||
14e99e0f | 288 | /** |
d1ebbc9d | 289 | * kvm_arm_sve_supported: |
14e99e0f AJ |
290 | * @cs: CPUState |
291 | * | |
292 | * Returns true if the KVM VCPU can enable SVE and false otherwise. | |
293 | */ | |
294 | bool kvm_arm_sve_supported(CPUState *cs); | |
295 | ||
a27382e2 | 296 | /** |
d1ebbc9d | 297 | * kvm_arm_get_max_vm_ipa_size: |
a27382e2 | 298 | * @ms: Machine state handle |
d1ebbc9d AJ |
299 | * |
300 | * Returns the number of bits in the IPA address space supported by KVM | |
a27382e2 EA |
301 | */ |
302 | int kvm_arm_get_max_vm_ipa_size(MachineState *ms); | |
303 | ||
1a1753f7 | 304 | /** |
d1ebbc9d | 305 | * kvm_arm_sync_mpstate_to_kvm: |
1a1753f7 AB |
306 | * @cpu: ARMCPU |
307 | * | |
308 | * If supported set the KVM MP_STATE based on QEMU's model. | |
d1ebbc9d AJ |
309 | * |
310 | * Returns 0 on success and -1 on failure. | |
1a1753f7 AB |
311 | */ |
312 | int kvm_arm_sync_mpstate_to_kvm(ARMCPU *cpu); | |
313 | ||
314 | /** | |
d1ebbc9d | 315 | * kvm_arm_sync_mpstate_to_qemu: |
1a1753f7 AB |
316 | * @cpu: ARMCPU |
317 | * | |
318 | * If supported get the MP_STATE from KVM and store in QEMU's model. | |
d1ebbc9d AJ |
319 | * |
320 | * Returns 0 on success and aborts on failure. | |
1a1753f7 AB |
321 | */ |
322 | int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu); | |
323 | ||
e5ac4200 AJ |
324 | /** |
325 | * kvm_arm_get_virtual_time: | |
326 | * @cs: CPUState | |
327 | * | |
328 | * Gets the VCPU's virtual counter and stores it in the KVM CPU state. | |
329 | */ | |
330 | void kvm_arm_get_virtual_time(CPUState *cs); | |
331 | ||
332 | /** | |
333 | * kvm_arm_put_virtual_time: | |
334 | * @cs: CPUState | |
335 | * | |
336 | * Sets the VCPU's virtual counter to the value stored in the KVM CPU state. | |
337 | */ | |
338 | void kvm_arm_put_virtual_time(CPUState *cs); | |
339 | ||
340 | void kvm_arm_vm_state_change(void *opaque, int running, RunState state); | |
341 | ||
34e85cd9 PF |
342 | int kvm_arm_vgic_probe(void); |
343 | ||
b2bfe9f7 AJ |
344 | void kvm_arm_pmu_set_irq(CPUState *cs, int irq); |
345 | void kvm_arm_pmu_init(CPUState *cs); | |
f6530926 | 346 | int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); |
01fe6b60 | 347 | |
34e85cd9 PF |
348 | #else |
349 | ||
c4487d76 PM |
350 | static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) |
351 | { | |
d1ebbc9d AJ |
352 | /* |
353 | * This should never actually be called in the "not KVM" case, | |
c4487d76 PM |
354 | * but set up the fields to indicate an error anyway. |
355 | */ | |
356 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; | |
357 | cpu->host_cpu_probe_failed = true; | |
358 | } | |
359 | ||
dea101a1 AJ |
360 | static inline void kvm_arm_add_vcpu_properties(Object *obj) {} |
361 | ||
b9e758f0 AJ |
362 | static inline bool kvm_arm_aarch32_supported(CPUState *cs) |
363 | { | |
364 | return false; | |
365 | } | |
366 | ||
ae502508 AJ |
367 | static inline bool kvm_arm_pmu_supported(CPUState *cs) |
368 | { | |
369 | return false; | |
370 | } | |
371 | ||
14e99e0f AJ |
372 | static inline bool kvm_arm_sve_supported(CPUState *cs) |
373 | { | |
374 | return false; | |
375 | } | |
376 | ||
a27382e2 EA |
377 | static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms) |
378 | { | |
379 | return -ENOENT; | |
380 | } | |
381 | ||
34e85cd9 PF |
382 | static inline int kvm_arm_vgic_probe(void) |
383 | { | |
384 | return 0; | |
385 | } | |
386 | ||
b2bfe9f7 AJ |
387 | static inline void kvm_arm_pmu_set_irq(CPUState *cs, int irq) {} |
388 | static inline void kvm_arm_pmu_init(CPUState *cs) {} | |
01fe6b60 | 389 | |
6fa8a379 | 390 | static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) {} |
e5ac4200 AJ |
391 | |
392 | static inline void kvm_arm_get_virtual_time(CPUState *cs) {} | |
393 | static inline void kvm_arm_put_virtual_time(CPUState *cs) {} | |
a96c0514 PM |
394 | #endif |
395 | ||
e6fbcbc4 PF |
396 | static inline const char *gic_class_name(void) |
397 | { | |
398 | return kvm_irqchip_in_kernel() ? "kvm-arm-gic" : "arm_gic"; | |
399 | } | |
400 | ||
a7bf3034 PF |
401 | /** |
402 | * gicv3_class_name | |
403 | * | |
404 | * Return name of GICv3 class to use depending on whether KVM acceleration is | |
405 | * in use. May throw an error if the chosen implementation is not available. | |
406 | * | |
407 | * Returns: class name to use | |
408 | */ | |
1b20616f EA |
409 | static inline const char *gicv3_class_name(void) |
410 | { | |
411 | if (kvm_irqchip_in_kernel()) { | |
412 | #ifdef TARGET_AARCH64 | |
413 | return "kvm-arm-gicv3"; | |
414 | #else | |
415 | error_report("KVM GICv3 acceleration is not supported on this " | |
416 | "platform"); | |
417 | exit(1); | |
418 | #endif | |
419 | } else { | |
bd559478 CD |
420 | if (kvm_enabled()) { |
421 | error_report("Userspace GICv3 is not supported with KVM"); | |
422 | exit(1); | |
423 | } | |
1b20616f EA |
424 | return "arm-gicv3"; |
425 | } | |
426 | } | |
a7bf3034 | 427 | |
2ecb2027 AB |
428 | /** |
429 | * kvm_arm_handle_debug: | |
430 | * @cs: CPUState | |
431 | * @debug_exit: debug part of the KVM exit structure | |
432 | * | |
433 | * Returns: TRUE if the debug exception was handled. | |
434 | */ | |
435 | bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit); | |
436 | ||
e4482ab7 AB |
437 | /** |
438 | * kvm_arm_hw_debug_active: | |
439 | * @cs: CPU State | |
440 | * | |
441 | * Return: TRUE if any hardware breakpoints in use. | |
442 | */ | |
e4482ab7 AB |
443 | bool kvm_arm_hw_debug_active(CPUState *cs); |
444 | ||
445 | /** | |
446 | * kvm_arm_copy_hw_debug_data: | |
e4482ab7 AB |
447 | * @ptr: kvm_guest_debug_arch structure |
448 | * | |
449 | * Copy the architecture specific debug registers into the | |
450 | * kvm_guest_debug ioctl structure. | |
451 | */ | |
452 | struct kvm_guest_debug_arch; | |
e4482ab7 AB |
453 | void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr); |
454 | ||
386ce3c7 | 455 | /** |
d1ebbc9d | 456 | * its_class_name: |
386ce3c7 PF |
457 | * |
458 | * Return the ITS class name to use depending on whether KVM acceleration | |
459 | * and KVM CAP_SIGNAL_MSI are supported | |
460 | * | |
461 | * Returns: class name to use or NULL | |
462 | */ | |
463 | static inline const char *its_class_name(void) | |
464 | { | |
465 | if (kvm_irqchip_in_kernel()) { | |
466 | /* KVM implementation requires this capability */ | |
467 | return kvm_direct_msi_enabled() ? "arm-its-kvm" : NULL; | |
468 | } else { | |
469 | /* Software emulation is not implemented yet */ | |
470 | return NULL; | |
471 | } | |
472 | } | |
473 | ||
eb035b48 | 474 | #endif |