[qemu.git] / target / arm / gdbstub.c

/*
 * ARM gdb server stub
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 * Copyright (c) 2013 SUSE LINUX Products GmbH
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/gdbstub.h"

typedef struct RegisterSysregXmlParam {
    CPUState *cs;
    GString *s;
    int n;
} RegisterSysregXmlParam;

/* Old gdb always expect FPA registers.  Newer (xml-aware) gdb only expect
   whatever the target description contains.  Due to a historical mishap
   the FPA registers appear in between core integer regs and the CPSR.
   We hack round this by giving the FPA regs zero size when talking to a
   newer gdb.  */

int arm_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
    ARMCPU *cpu = ARM_CPU(cs);
    CPUARMState *env = &cpu->env;

    if (n < 16) {
        /* Core integer register.  */
        return gdb_get_reg32(mem_buf, env->regs[n]);
    }
    if (n < 24) {
        /* FPA registers.  */
        if (gdb_has_xml) {
            return 0;
        }
        memset(mem_buf, 0, 12);
        return 12;
    }
    switch (n) {
    case 24:
        /* FPA status register.  */
        if (gdb_has_xml) {
            return 0;
        }
        return gdb_get_reg32(mem_buf, 0);
    case 25:
        /* CPSR */
        return gdb_get_reg32(mem_buf, cpsr_read(env));
    }
    /* Unknown register.  */
    return 0;
}

int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
    ARMCPU *cpu = ARM_CPU(cs);
    CPUARMState *env = &cpu->env;
    uint32_t tmp;

    tmp = ldl_p(mem_buf);

    /* Mask out low bit of PC to workaround gdb bugs.  This will probably
       cause problems if we ever implement the Jazelle DBX extensions.  */
    if (n == 15) {
        tmp &= ~1;
    }

    if (n < 16) {
        /* Core integer register.  */
        env->regs[n] = tmp;
        return 4;
    }
    if (n < 24) { /* 16-23 */
        /* FPA registers (ignored).  */
        if (gdb_has_xml) {
            return 0;
        }
        return 12;
    }
    switch (n) {
    case 24:
        /* FPA status register (ignored).  */
        if (gdb_has_xml) {
            return 0;
        }
        return 4;
    case 25:
        /* CPSR */
        cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub);
        return 4;
    }
    /* Unknown register.  */
    return 0;
}

static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,
                                       ARMCPRegInfo *ri, uint32_t ri_key,
                                       int bitsize, int regnum)
{
    g_string_append_printf(s, "<reg name=\"%s\"", ri->name);
    g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
    g_string_append_printf(s, " regnum=\"%d\"", regnum);
    g_string_append_printf(s, " group=\"cp_regs\"/>");
    dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key;
    dyn_xml->num++;
}

static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
                                        gpointer p)
{
    uint32_t ri_key = *(uint32_t *)key;
    ARMCPRegInfo *ri = value;
    RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;
    GString *s = param->s;
    ARMCPU *cpu = ARM_CPU(param->cs);
    CPUARMState *env = &cpu->env;
    DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_sysreg_xml;

    if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) {
        if (arm_feature(env, ARM_FEATURE_AARCH64)) {
            if (ri->state == ARM_CP_STATE_AA64) {
                arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
                                           param->n++);
            }
        } else {
            if (ri->state == ARM_CP_STATE_AA32) {
                if (!arm_feature(env, ARM_FEATURE_EL3) &&
                    (ri->secure & ARM_CP_SECSTATE_S)) {
                    return;
                }
                if (ri->type & ARM_CP_64BIT) {
                    arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
                                               param->n++);
                } else {
                    arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32,
                                               param->n++);
                }
            }
        }
    }
}

int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
{
    ARMCPU *cpu = ARM_CPU(cs);
    GString *s = g_string_new(NULL);
    RegisterSysregXmlParam param = {cs, s, base_reg};

    cpu->dyn_sysreg_xml.num = 0;
    cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
    g_string_printf(s, "<?xml version=\"1.0\"?>");
    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
    g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
    g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, &param);
    g_string_append_printf(s, "</feature>");
    cpu->dyn_sysreg_xml.desc = g_string_free(s, false);
    return cpu->dyn_sysreg_xml.num;
}

struct TypeSize {
    const char *gdb_type;
    int  size;
    const char sz, suffix;
};

static const struct TypeSize vec_lanes[] = {
    /* quads */
    { "uint128", 128, 'q', 'u' },
    { "int128", 128, 'q', 's' },
    /* 64 bit */
    { "uint64", 64, 'd', 'u' },
    { "int64", 64, 'd', 's' },
    { "ieee_double", 64, 'd', 'f' },
    /* 32 bit */
    { "uint32", 32, 's', 'u' },
    { "int32", 32, 's', 's' },
    { "ieee_single", 32, 's', 'f' },
    /* 16 bit */
    { "uint16", 16, 'h', 'u' },
    { "int16", 16, 'h', 's' },
    { "ieee_half", 16, 'h', 'f' },
    /* bytes */
    { "uint8", 8, 'b', 'u' },
    { "int8", 8, 'b', 's' },
};


int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
{
    ARMCPU *cpu = ARM_CPU(cs);
    GString *s = g_string_new(NULL);
    DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
    g_autoptr(GString) ts = g_string_new("");
    int i, bits, reg_width = (cpu->sve_max_vq * 128);
    info->num = 0;
    g_string_printf(s, "<?xml version=\"1.0\"?>");
    g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
    g_string_append_printf(s, "<feature name=\"org.qemu.gdb.aarch64.sve\">");

    /* First define types and totals in a whole VL */
    for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
        int count = reg_width / vec_lanes[i].size;
        g_string_printf(ts, "vq%d%c%c", count,
                        vec_lanes[i].sz, vec_lanes[i].suffix);
        g_string_append_printf(s,
                               "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
                               ts->str, vec_lanes[i].gdb_type, count);
    }
    /*
     * Now define a union for each size group containing unsigned and
     * signed and potentially float versions of each size from 128 to
     * 8 bits.
     */
    for (bits = 128; bits >= 8; bits /= 2) {
        int count = reg_width / bits;
        g_string_append_printf(s, "<union id=\"vq%dn\">", count);
        for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
            if (vec_lanes[i].size == bits) {
                g_string_append_printf(s, "<field name=\"%c\" type=\"vq%d%c%c\"/>",
                                       vec_lanes[i].suffix,
                                       count,
                                       vec_lanes[i].sz, vec_lanes[i].suffix);
            }
        }
        g_string_append(s, "</union>");
    }
    /* And now the final union of unions */
    g_string_append(s, "<union id=\"vq\">");
    for (bits = 128; bits >= 8; bits /= 2) {
        int count = reg_width / bits;
        for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
            if (vec_lanes[i].size == bits) {
                g_string_append_printf(s, "<field name=\"%c\" type=\"vq%dn\"/>",
                                       vec_lanes[i].sz, count);
                break;
            }
        }
    }
    g_string_append(s, "</union>");

    /* Then define each register in parts for each vq */
    for (i = 0; i < 32; i++) {
        g_string_append_printf(s,
                               "<reg name=\"z%d\" bitsize=\"%d\""
                               " regnum=\"%d\" group=\"vector\""
                               " type=\"vq\"/>",
                               i, reg_width, base_reg++);
        info->num++;
    }
    /* fpscr & status registers */
    g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
                           " regnum=\"%d\" group=\"float\""
                           " type=\"int\"/>", base_reg++);
    g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
                           " regnum=\"%d\" group=\"float\""
                           " type=\"int\"/>", base_reg++);
    info->num += 2;
    /*
     * Predicate registers aren't so big they are worth splitting up
     * but we do need to define a type to hold the array of quad
     * references.
     */
    g_string_append_printf(s,
                           "<vector id=\"vqp\" type=\"uint16\" count=\"%d\"/>",
                           cpu->sve_max_vq);
    for (i = 0; i < 16; i++) {
        g_string_append_printf(s,
                               "<reg name=\"p%d\" bitsize=\"%d\""
                               " regnum=\"%d\" group=\"vector\""
                               " type=\"vqp\"/>",
                               i, cpu->sve_max_vq * 16, base_reg++);
        info->num++;
    }
    g_string_append_printf(s,
                           "<reg name=\"ffr\" bitsize=\"%d\""
                           " regnum=\"%d\" group=\"vector\""
                           " type=\"vqp\"/>",
                           cpu->sve_max_vq * 16, base_reg++);
    g_string_append_printf(s,
                           "<reg name=\"vg\" bitsize=\"64\""
                           " regnum=\"%d\" group=\"vector\""
                           " type=\"uint32\"/>",
                           base_reg++);
    info->num += 2;
    g_string_append_printf(s, "</feature>");
    cpu->dyn_svereg_xml.desc = g_string_free(s, false);

    return cpu->dyn_svereg_xml.num;
}


const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
{
    ARMCPU *cpu = ARM_CPU(cs);

    if (strcmp(xmlname, "system-registers.xml") == 0) {
        return cpu->dyn_sysreg_xml.desc;
    } else if (strcmp(xmlname, "sve-registers.xml") == 0) {
        return cpu->dyn_svereg_xml.desc;
    }
    return NULL;
}
Commit	Line	Data
58850dad AF	1	/*
	2	* ARM gdb server stub
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	* Copyright (c) 2013 SUSE LINUX Products GmbH
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
74c21bd0	20	#include "qemu/osdep.h"
33c11879	21	#include "cpu.h"
5b50e790	22	#include "exec/gdbstub.h"
58850dad	23
200bf5b7 AB	24	typedef struct RegisterSysregXmlParam {
	25	CPUState *cs;
	26	GString *s;
32d6e32a	27	int n;
200bf5b7 AB	28	} RegisterSysregXmlParam;
200bf5b7 AB	29
58850dad AF	30	/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
	31	whatever the target description contains. Due to a historical mishap
	32	the FPA registers appear in between core integer regs and the CPSR.
	33	We hack round this by giving the FPA regs zero size when talking to a
	34	newer gdb. */
	35
a010bdbe	36	int arm_cpu_gdb_read_register(CPUState cs, GByteArray mem_buf, int n)
58850dad	37	{
5b50e790 AF	38	ARMCPU *cpu = ARM_CPU(cs);
	39	CPUARMState *env = &cpu->env;
	40
58850dad AF	41	if (n < 16) {
58850dad AF	42	/* Core integer register. */
986a2998	43	return gdb_get_reg32(mem_buf, env->regs[n]);
58850dad AF	44	}
	45	if (n < 24) {
	46	/* FPA registers. */
	47	if (gdb_has_xml) {
	48	return 0;
	49	}
	50	memset(mem_buf, 0, 12);
	51	return 12;
	52	}
	53	switch (n) {
	54	case 24:
	55	/* FPA status register. */
	56	if (gdb_has_xml) {
	57	return 0;
	58	}
986a2998	59	return gdb_get_reg32(mem_buf, 0);
58850dad AF	60	case 25:
58850dad AF	61	/* CPSR */
986a2998	62	return gdb_get_reg32(mem_buf, cpsr_read(env));
58850dad AF	63	}
	64	/* Unknown register. */
	65	return 0;
	66	}
	67
5b50e790	68	int arm_cpu_gdb_write_register(CPUState cs, uint8_t mem_buf, int n)
58850dad	69	{
5b50e790 AF	70	ARMCPU *cpu = ARM_CPU(cs);
5b50e790 AF	71	CPUARMState *env = &cpu->env;
58850dad AF	72	uint32_t tmp;
	73
	74	tmp = ldl_p(mem_buf);
	75
	76	/* Mask out low bit of PC to workaround gdb bugs. This will probably
	77	cause problems if we ever implement the Jazelle DBX extensions. */
	78	if (n == 15) {
	79	tmp &= ~1;
	80	}
	81
	82	if (n < 16) {
	83	/* Core integer register. */
	84	env->regs[n] = tmp;
	85	return 4;
	86	}
	87	if (n < 24) { /* 16-23 */
	88	/* FPA registers (ignored). */
	89	if (gdb_has_xml) {
	90	return 0;
	91	}
	92	return 12;
	93	}
	94	switch (n) {
	95	case 24:
	96	/* FPA status register (ignored). */
	97	if (gdb_has_xml) {
	98	return 0;
	99	}
	100	return 4;
	101	case 25:
	102	/* CPSR */
50866ba5	103	cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub);
58850dad AF	104	return 4;
	105	}
	106	/* Unknown register. */
	107	return 0;
	108	}
200bf5b7	109
448d4d14 AB	110	static void arm_gen_one_xml_sysreg_tag(GString s, DynamicGDBXMLInfo dyn_xml,
448d4d14 AB	111	ARMCPRegInfo *ri, uint32_t ri_key,
32d6e32a	112	int bitsize, int regnum)
200bf5b7 AB	113	{
	114	g_string_append_printf(s, "<reg name=\"%s\"", ri->name);
	115	g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
32d6e32a	116	g_string_append_printf(s, " regnum=\"%d\"", regnum);
200bf5b7	117	g_string_append_printf(s, " group=\"cp_regs\"/>");
448d4d14 AB	118	dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key;
448d4d14 AB	119	dyn_xml->num++;
200bf5b7 AB	120	}
	121
	122	static void arm_register_sysreg_for_xml(gpointer key, gpointer value,
	123	gpointer p)
	124	{
	125	uint32_t ri_key = (uint32_t )key;
	126	ARMCPRegInfo *ri = value;
	127	RegisterSysregXmlParam param = (RegisterSysregXmlParam )p;
	128	GString *s = param->s;
	129	ARMCPU *cpu = ARM_CPU(param->cs);
	130	CPUARMState *env = &cpu->env;
448d4d14	131	DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_sysreg_xml;
200bf5b7 AB	132
	133	if (!(ri->type & (ARM_CP_NO_RAW \| ARM_CP_NO_GDB))) {
	134	if (arm_feature(env, ARM_FEATURE_AARCH64)) {
	135	if (ri->state == ARM_CP_STATE_AA64) {
32d6e32a AB	136	arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
32d6e32a AB	137	param->n++);
200bf5b7 AB	138	}
	139	} else {
	140	if (ri->state == ARM_CP_STATE_AA32) {
	141	if (!arm_feature(env, ARM_FEATURE_EL3) &&
	142	(ri->secure & ARM_CP_SECSTATE_S)) {
	143	return;
	144	}
	145	if (ri->type & ARM_CP_64BIT) {
32d6e32a AB	146	arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,
32d6e32a AB	147	param->n++);
200bf5b7	148	} else {
32d6e32a AB	149	arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32,
32d6e32a AB	150	param->n++);
200bf5b7 AB	151	}
	152	}
	153	}
	154	}
	155	}
	156
32d6e32a	157	int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)
200bf5b7 AB	158	{
	159	ARMCPU *cpu = ARM_CPU(cs);
	160	GString *s = g_string_new(NULL);
32d6e32a	161	RegisterSysregXmlParam param = {cs, s, base_reg};
200bf5b7	162
448d4d14 AB	163	cpu->dyn_sysreg_xml.num = 0;
448d4d14 AB	164	cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
200bf5b7 AB	165	g_string_printf(s, "<?xml version=\"1.0\"?>");
	166	g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
	167	g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
	168	g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, &param);
	169	g_string_append_printf(s, "</feature>");
448d4d14 AB	170	cpu->dyn_sysreg_xml.desc = g_string_free(s, false);
448d4d14 AB	171	return cpu->dyn_sysreg_xml.num;
200bf5b7 AB	172	}
200bf5b7 AB	173
d12379c5 AB	174	struct TypeSize {
	175	const char *gdb_type;
	176	int size;
	177	const char sz, suffix;
	178	};
	179
	180	static const struct TypeSize vec_lanes[] = {
	181	/* quads */
	182	{ "uint128", 128, 'q', 'u' },
	183	{ "int128", 128, 'q', 's' },
	184	/* 64 bit */
	185	{ "uint64", 64, 'd', 'u' },
	186	{ "int64", 64, 'd', 's' },
	187	{ "ieee_double", 64, 'd', 'f' },
	188	/* 32 bit */
	189	{ "uint32", 32, 's', 'u' },
	190	{ "int32", 32, 's', 's' },
	191	{ "ieee_single", 32, 's', 'f' },
	192	/* 16 bit */
	193	{ "uint16", 16, 'h', 'u' },
	194	{ "int16", 16, 'h', 's' },
	195	{ "ieee_half", 16, 'h', 'f' },
	196	/* bytes */
	197	{ "uint8", 8, 'b', 'u' },
	198	{ "int8", 8, 'b', 's' },
	199	};
	200
	201
	202	int arm_gen_dynamic_svereg_xml(CPUState *cs, int base_reg)
	203	{
	204	ARMCPU *cpu = ARM_CPU(cs);
	205	GString *s = g_string_new(NULL);
	206	DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;
	207	g_autoptr(GString) ts = g_string_new("");
	208	int i, bits, reg_width = (cpu->sve_max_vq * 128);
	209	info->num = 0;
	210	g_string_printf(s, "<?xml version=\"1.0\"?>");
	211	g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
	212	g_string_append_printf(s, "<feature name=\"org.qemu.gdb.aarch64.sve\">");
	213
	214	/* First define types and totals in a whole VL */
	215	for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
	216	int count = reg_width / vec_lanes[i].size;
	217	g_string_printf(ts, "vq%d%c%c", count,
	218	vec_lanes[i].sz, vec_lanes[i].suffix);
	219	g_string_append_printf(s,
	220	"<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
	221	ts->str, vec_lanes[i].gdb_type, count);
	222	}
	223	/*
	224	* Now define a union for each size group containing unsigned and
	225	* signed and potentially float versions of each size from 128 to
	226	* 8 bits.
	227	*/
	228	for (bits = 128; bits >= 8; bits /= 2) {
	229	int count = reg_width / bits;
	230	g_string_append_printf(s, "<union id=\"vq%dn\">", count);
	231	for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
	232	if (vec_lanes[i].size == bits) {
	233	g_string_append_printf(s, "<field name=\"%c\" type=\"vq%d%c%c\"/>",
	234	vec_lanes[i].suffix,
	235	count,
	236	vec_lanes[i].sz, vec_lanes[i].suffix);
	237	}
238	}
239	g_string_append(s, "</union>");
240	}
241	/* And now the final union of unions */
242	g_string_append(s, "<union id=\"vq\">");
243	for (bits = 128; bits >= 8; bits /= 2) {
244	int count = reg_width / bits;
245	for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
246	if (vec_lanes[i].size == bits) {
247	g_string_append_printf(s, "<field name=\"%c\" type=\"vq%dn\"/>",
248	vec_lanes[i].sz, count);
249	break;
250	}
251	}
252	}
253	g_string_append(s, "</union>");
254
255	/* Then define each register in parts for each vq */
256	for (i = 0; i < 32; i++) {
257	g_string_append_printf(s,
258	"<reg name=\"z%d\" bitsize=\"%d\""
259	" regnum=\"%d\" group=\"vector\""
260	" type=\"vq\"/>",
261	i, reg_width, base_reg++);
262	info->num++;
263	}
264	/* fpscr & status registers */
265	g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""
266	" regnum=\"%d\" group=\"float\""
267	" type=\"int\"/>", base_reg++);
268	g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""
269	" regnum=\"%d\" group=\"float\""
270	" type=\"int\"/>", base_reg++);
271	info->num += 2;
272	/*
273	* Predicate registers aren't so big they are worth splitting up
274	* but we do need to define a type to hold the array of quad
275	* references.
276	*/
277	g_string_append_printf(s,
278	"<vector id=\"vqp\" type=\"uint16\" count=\"%d\"/>",
279	cpu->sve_max_vq);
280	for (i = 0; i < 16; i++) {
281	g_string_append_printf(s,
282	"<reg name=\"p%d\" bitsize=\"%d\""
283	" regnum=\"%d\" group=\"vector\""
284	" type=\"vqp\"/>",
285	i, cpu->sve_max_vq * 16, base_reg++);
286	info->num++;
287	}
288	g_string_append_printf(s,
289	"<reg name=\"ffr\" bitsize=\"%d\""
290	" regnum=\"%d\" group=\"vector\""
291	" type=\"vqp\"/>",
292	cpu->sve_max_vq * 16, base_reg++);
293	g_string_append_printf(s,
294	"<reg name=\"vg\" bitsize=\"64\""
295	" regnum=\"%d\" group=\"vector\""
296	" type=\"uint32\"/>",
297	base_reg++);
298	info->num += 2;
299	g_string_append_printf(s, "</feature>");
300	cpu->dyn_svereg_xml.desc = g_string_free(s, false);
301
302	return cpu->dyn_svereg_xml.num;
303	}
304
305
200bf5b7 AB	306	const char arm_gdb_get_dynamic_xml(CPUState cs, const char *xmlname)
	307	{
	308	ARMCPU *cpu = ARM_CPU(cs);
	309
	310	if (strcmp(xmlname, "system-registers.xml") == 0) {
448d4d14	311	return cpu->dyn_sysreg_xml.desc;
d12379c5 AB	312	} else if (strcmp(xmlname, "sve-registers.xml") == 0) {
d12379c5 AB	313	return cpu->dyn_svereg_xml.desc;
200bf5b7 AB	314	}
	315	return NULL;
	316	}