[qemu.git] / hw / display / milkymist-vgafb.c


/*
 *  QEMU model of the Milkymist VGA framebuffer.
 *
 *  Copyright (c) 2010-2012 Michael Walle <[email protected]>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Specification available at:
 *   http://www.milkymist.org/socdoc/vgafb.pdf
 */

#include "hw/hw.h"
#include "hw/sysbus.h"
#include "trace.h"
#include "ui/console.h"
#include "framebuffer.h"
#include "ui/pixel_ops.h"
#include "qemu/error-report.h"

#define BITS 8
#include "milkymist-vgafb_template.h"
#define BITS 15
#include "milkymist-vgafb_template.h"
#define BITS 16
#include "milkymist-vgafb_template.h"
#define BITS 24
#include "milkymist-vgafb_template.h"
#define BITS 32
#include "milkymist-vgafb_template.h"

enum {
    R_CTRL = 0,
    R_HRES,
    R_HSYNC_START,
    R_HSYNC_END,
    R_HSCAN,
    R_VRES,
    R_VSYNC_START,
    R_VSYNC_END,
    R_VSCAN,
    R_BASEADDRESS,
    R_BASEADDRESS_ACT,
    R_BURST_COUNT,
    R_DDC,
    R_SOURCE_CLOCK,
    R_MAX
};

enum {
    CTRL_RESET = (1<<0),
};

struct MilkymistVgafbState {
    SysBusDevice busdev;
    MemoryRegion regs_region;
    QemuConsole *con;

    int invalidate;
    uint32_t fb_offset;
    uint32_t fb_mask;

    uint32_t regs[R_MAX];
};
typedef struct MilkymistVgafbState MilkymistVgafbState;

static int vgafb_enabled(MilkymistVgafbState *s)
{
    return !(s->regs[R_CTRL] & CTRL_RESET);
}

static void vgafb_update_display(void *opaque)
{
    MilkymistVgafbState *s = opaque;
    DisplaySurface *surface = qemu_console_surface(s->con);
    int first = 0;
    int last = 0;
    drawfn fn;

    if (!vgafb_enabled(s)) {
        return;
    }

    int dest_width = s->regs[R_HRES];

    switch (surface_bits_per_pixel(surface)) {
    case 0:
        return;
    case 8:
        fn = draw_line_8;
        break;
    case 15:
        fn = draw_line_15;
        dest_width *= 2;
        break;
    case 16:
        fn = draw_line_16;
        dest_width *= 2;
        break;
    case 24:
        fn = draw_line_24;
        dest_width *= 3;
        break;
    case 32:
        fn = draw_line_32;
        dest_width *= 4;
        break;
    default:
        hw_error("milkymist_vgafb: bad color depth\n");
        break;
    }

    framebuffer_update_display(surface, sysbus_address_space(&s->busdev),
                               s->regs[R_BASEADDRESS] + s->fb_offset,
                               s->regs[R_HRES],
                               s->regs[R_VRES],
                               s->regs[R_HRES] * 2,
                               dest_width,
                               0,
                               s->invalidate,
                               fn,
                               NULL,
                               &first, &last);

    if (first >= 0) {
        dpy_gfx_update(s->con, 0, first, s->regs[R_HRES], last - first + 1);
    }
    s->invalidate = 0;
}

static void vgafb_invalidate_display(void *opaque)
{
    MilkymistVgafbState *s = opaque;
    s->invalidate = 1;
}

static void vgafb_resize(MilkymistVgafbState *s)
{
    if (!vgafb_enabled(s)) {
        return;
    }

    qemu_console_resize(s->con, s->regs[R_HRES], s->regs[R_VRES]);
    s->invalidate = 1;
}

static uint64_t vgafb_read(void *opaque, hwaddr addr,
                           unsigned size)
{
    MilkymistVgafbState *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr) {
    case R_CTRL:
    case R_HRES:
    case R_HSYNC_START:
    case R_HSYNC_END:
    case R_HSCAN:
    case R_VRES:
    case R_VSYNC_START:
    case R_VSYNC_END:
    case R_VSCAN:
    case R_BASEADDRESS:
    case R_BURST_COUNT:
    case R_DDC:
    case R_SOURCE_CLOCK:
        r = s->regs[addr];
    break;
    case R_BASEADDRESS_ACT:
        r = s->regs[R_BASEADDRESS];
    break;

    default:
        error_report("milkymist_vgafb: read access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }

    trace_milkymist_vgafb_memory_read(addr << 2, r);

    return r;
}

static void vgafb_write(void *opaque, hwaddr addr, uint64_t value,
                        unsigned size)
{
    MilkymistVgafbState *s = opaque;

    trace_milkymist_vgafb_memory_write(addr, value);

    addr >>= 2;
    switch (addr) {
    case R_CTRL:
        s->regs[addr] = value;
        vgafb_resize(s);
        break;
    case R_HSYNC_START:
    case R_HSYNC_END:
    case R_HSCAN:
    case R_VSYNC_START:
    case R_VSYNC_END:
    case R_VSCAN:
    case R_BURST_COUNT:
    case R_DDC:
    case R_SOURCE_CLOCK:
        s->regs[addr] = value;
        break;
    case R_BASEADDRESS:
        if (value & 0x1f) {
            error_report("milkymist_vgafb: framebuffer base address have to "
                     "be 32 byte aligned");
            break;
        }
        s->regs[addr] = value & s->fb_mask;
        s->invalidate = 1;
        break;
    case R_HRES:
    case R_VRES:
        s->regs[addr] = value;
        vgafb_resize(s);
        break;
    case R_BASEADDRESS_ACT:
        error_report("milkymist_vgafb: write to read-only register 0x"
                TARGET_FMT_plx, addr << 2);
        break;

    default:
        error_report("milkymist_vgafb: write access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }
}

static const MemoryRegionOps vgafb_mmio_ops = {
    .read = vgafb_read,
    .write = vgafb_write,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void milkymist_vgafb_reset(DeviceState *d)
{
    MilkymistVgafbState *s = container_of(d, MilkymistVgafbState, busdev.qdev);
    int i;

    for (i = 0; i < R_MAX; i++) {
        s->regs[i] = 0;
    }

    /* defaults */
    s->regs[R_CTRL] = CTRL_RESET;
    s->regs[R_HRES] = 640;
    s->regs[R_VRES] = 480;
    s->regs[R_BASEADDRESS] = 0;
}

static const GraphicHwOps vgafb_ops = {
    .invalidate  = vgafb_invalidate_display,
    .gfx_update  = vgafb_update_display,
};

static int milkymist_vgafb_init(SysBusDevice *dev)
{
    MilkymistVgafbState *s = FROM_SYSBUS(typeof(*s), dev);

    memory_region_init_io(&s->regs_region, &vgafb_mmio_ops, s,
            "milkymist-vgafb", R_MAX * 4);
    sysbus_init_mmio(dev, &s->regs_region);

    s->con = graphic_console_init(DEVICE(dev), &vgafb_ops, s);

    return 0;
}

static int vgafb_post_load(void *opaque, int version_id)
{
    vgafb_invalidate_display(opaque);
    return 0;
}

static const VMStateDescription vmstate_milkymist_vgafb = {
    .name = "milkymist-vgafb",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = vgafb_post_load,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, MilkymistVgafbState, R_MAX),
        VMSTATE_END_OF_LIST()
    }
};

static Property milkymist_vgafb_properties[] = {
    DEFINE_PROP_UINT32("fb_offset", MilkymistVgafbState, fb_offset, 0x0),
    DEFINE_PROP_UINT32("fb_mask", MilkymistVgafbState, fb_mask, 0xffffffff),
    DEFINE_PROP_END_OF_LIST(),
};

static void milkymist_vgafb_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = milkymist_vgafb_init;
    dc->reset = milkymist_vgafb_reset;
    dc->vmsd = &vmstate_milkymist_vgafb;
    dc->props = milkymist_vgafb_properties;
}

static const TypeInfo milkymist_vgafb_info = {
    .name          = "milkymist-vgafb",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MilkymistVgafbState),
    .class_init    = milkymist_vgafb_class_init,
};

static void milkymist_vgafb_register_types(void)
{
    type_register_static(&milkymist_vgafb_info);
}

type_init(milkymist_vgafb_register_types)
Commit	Line	Data
d23948b1 MW	1
	2	/*
	3	* QEMU model of the Milkymist VGA framebuffer.
	4	*
a3b6181e	5	* Copyright (c) 2010-2012 Michael Walle <[email protected]>
d23948b1 MW	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*
	20	*
	21	* Specification available at:
	22	* http://www.milkymist.org/socdoc/vgafb.pdf
	23	*/
	24
83c9f4ca PB	25	#include "hw/hw.h"
83c9f4ca PB	26	#include "hw/sysbus.h"
d23948b1	27	#include "trace.h"
28ecbaee	28	#include "ui/console.h"
47b43a1f	29	#include "framebuffer.h"
28ecbaee	30	#include "ui/pixel_ops.h"
1de7afc9	31	#include "qemu/error-report.h"
d23948b1 MW	32
d23948b1 MW	33	#define BITS 8
47b43a1f	34	#include "milkymist-vgafb_template.h"
d23948b1	35	#define BITS 15
47b43a1f	36	#include "milkymist-vgafb_template.h"
d23948b1	37	#define BITS 16
47b43a1f	38	#include "milkymist-vgafb_template.h"
d23948b1	39	#define BITS 24
47b43a1f	40	#include "milkymist-vgafb_template.h"
d23948b1	41	#define BITS 32
47b43a1f	42	#include "milkymist-vgafb_template.h"
d23948b1 MW	43
	44	enum {
	45	R_CTRL = 0,
	46	R_HRES,
	47	R_HSYNC_START,
	48	R_HSYNC_END,
	49	R_HSCAN,
	50	R_VRES,
	51	R_VSYNC_START,
	52	R_VSYNC_END,
	53	R_VSCAN,
	54	R_BASEADDRESS,
	55	R_BASEADDRESS_ACT,
	56	R_BURST_COUNT,
a3b6181e	57	R_DDC,
d23948b1 MW	58	R_SOURCE_CLOCK,
	59	R_MAX
	60	};
	61
	62	enum {
	63	CTRL_RESET = (1<<0),
	64	};
	65
	66	struct MilkymistVgafbState {
	67	SysBusDevice busdev;
883abf8d	68	MemoryRegion regs_region;
c78f7137	69	QemuConsole *con;
d23948b1 MW	70
	71	int invalidate;
	72	uint32_t fb_offset;
	73	uint32_t fb_mask;
	74
	75	uint32_t regs[R_MAX];
	76	};
	77	typedef struct MilkymistVgafbState MilkymistVgafbState;
	78
	79	static int vgafb_enabled(MilkymistVgafbState *s)
	80	{
	81	return !(s->regs[R_CTRL] & CTRL_RESET);
	82	}
	83
	84	static void vgafb_update_display(void *opaque)
	85	{
	86	MilkymistVgafbState *s = opaque;
c78f7137	87	DisplaySurface *surface = qemu_console_surface(s->con);
d23948b1 MW	88	int first = 0;
	89	int last = 0;
	90	drawfn fn;
	91
	92	if (!vgafb_enabled(s)) {
	93	return;
	94	}
	95
	96	int dest_width = s->regs[R_HRES];
	97
c78f7137	98	switch (surface_bits_per_pixel(surface)) {
d23948b1 MW	99	case 0:
	100	return;
	101	case 8:
	102	fn = draw_line_8;
	103	break;
	104	case 15:
	105	fn = draw_line_15;
	106	dest_width *= 2;
	107	break;
	108	case 16:
	109	fn = draw_line_16;
	110	dest_width *= 2;
	111	break;
	112	case 24:
	113	fn = draw_line_24;
	114	dest_width *= 3;
	115	break;
	116	case 32:
	117	fn = draw_line_32;
	118	dest_width *= 4;
	119	break;
	120	default:
	121	hw_error("milkymist_vgafb: bad color depth\n");
	122	break;
	123	}
	124
c78f7137	125	framebuffer_update_display(surface, sysbus_address_space(&s->busdev),
d23948b1 MW	126	s->regs[R_BASEADDRESS] + s->fb_offset,
	127	s->regs[R_HRES],
	128	s->regs[R_VRES],
	129	s->regs[R_HRES] * 2,
	130	dest_width,
	131	0,
	132	s->invalidate,
	133	fn,
	134	NULL,
	135	&first, &last);
	136
	137	if (first >= 0) {
c78f7137	138	dpy_gfx_update(s->con, 0, first, s->regs[R_HRES], last - first + 1);
d23948b1 MW	139	}
	140	s->invalidate = 0;
	141	}
	142
	143	static void vgafb_invalidate_display(void *opaque)
	144	{
	145	MilkymistVgafbState *s = opaque;
	146	s->invalidate = 1;
	147	}
	148
	149	static void vgafb_resize(MilkymistVgafbState *s)
	150	{
	151	if (!vgafb_enabled(s)) {
	152	return;
	153	}
	154
c78f7137	155	qemu_console_resize(s->con, s->regs[R_HRES], s->regs[R_VRES]);
d23948b1 MW	156	s->invalidate = 1;
	157	}
	158
a8170e5e	159	static uint64_t vgafb_read(void *opaque, hwaddr addr,
883abf8d	160	unsigned size)
d23948b1 MW	161	{
	162	MilkymistVgafbState *s = opaque;
	163	uint32_t r = 0;
	164
	165	addr >>= 2;
	166	switch (addr) {
	167	case R_CTRL:
	168	case R_HRES:
	169	case R_HSYNC_START:
	170	case R_HSYNC_END:
	171	case R_HSCAN:
	172	case R_VRES:
	173	case R_VSYNC_START:
	174	case R_VSYNC_END:
	175	case R_VSCAN:
	176	case R_BASEADDRESS:
	177	case R_BURST_COUNT:
a3b6181e	178	case R_DDC:
d23948b1 MW	179	case R_SOURCE_CLOCK:
	180	r = s->regs[addr];
	181	break;
	182	case R_BASEADDRESS_ACT:
	183	r = s->regs[R_BASEADDRESS];
	184	break;
	185
	186	default:
	187	error_report("milkymist_vgafb: read access to unknown register 0x"
	188	TARGET_FMT_plx, addr << 2);
	189	break;
	190	}
	191
	192	trace_milkymist_vgafb_memory_read(addr << 2, r);
	193
	194	return r;
	195	}
	196
a8170e5e	197	static void vgafb_write(void *opaque, hwaddr addr, uint64_t value,
883abf8d	198	unsigned size)
d23948b1 MW	199	{
	200	MilkymistVgafbState *s = opaque;
	201
	202	trace_milkymist_vgafb_memory_write(addr, value);
	203
	204	addr >>= 2;
	205	switch (addr) {
	206	case R_CTRL:
c07050dd MW	207	s->regs[addr] = value;
	208	vgafb_resize(s);
	209	break;
d23948b1 MW	210	case R_HSYNC_START:
	211	case R_HSYNC_END:
	212	case R_HSCAN:
	213	case R_VSYNC_START:
	214	case R_VSYNC_END:
	215	case R_VSCAN:
	216	case R_BURST_COUNT:
a3b6181e	217	case R_DDC:
d23948b1 MW	218	case R_SOURCE_CLOCK:
	219	s->regs[addr] = value;
	220	break;
	221	case R_BASEADDRESS:
	222	if (value & 0x1f) {
	223	error_report("milkymist_vgafb: framebuffer base address have to "
	224	"be 32 byte aligned");
	225	break;
	226	}
	227	s->regs[addr] = value & s->fb_mask;
	228	s->invalidate = 1;
	229	break;
	230	case R_HRES:
	231	case R_VRES:
	232	s->regs[addr] = value;
	233	vgafb_resize(s);
	234	break;
	235	case R_BASEADDRESS_ACT:
	236	error_report("milkymist_vgafb: write to read-only register 0x"
	237	TARGET_FMT_plx, addr << 2);
	238	break;
	239
	240	default:
	241	error_report("milkymist_vgafb: write access to unknown register 0x"
	242	TARGET_FMT_plx, addr << 2);
	243	break;
	244	}
	245	}
	246
883abf8d MW	247	static const MemoryRegionOps vgafb_mmio_ops = {
	248	.read = vgafb_read,
	249	.write = vgafb_write,
	250	.valid = {
	251	.min_access_size = 4,
	252	.max_access_size = 4,
	253	},
	254	.endianness = DEVICE_NATIVE_ENDIAN,
d23948b1 MW	255	};
	256
	257	static void milkymist_vgafb_reset(DeviceState *d)
	258	{
	259	MilkymistVgafbState *s = container_of(d, MilkymistVgafbState, busdev.qdev);
	260	int i;
	261
	262	for (i = 0; i < R_MAX; i++) {
	263	s->regs[i] = 0;
	264	}
	265
	266	/* defaults */
	267	s->regs[R_CTRL] = CTRL_RESET;
	268	s->regs[R_HRES] = 640;
	269	s->regs[R_VRES] = 480;
	270	s->regs[R_BASEADDRESS] = 0;
	271	}
	272
380cd056 GH	273	static const GraphicHwOps vgafb_ops = {
	274	.invalidate = vgafb_invalidate_display,
	275	.gfx_update = vgafb_update_display,
	276	};
	277
d23948b1 MW	278	static int milkymist_vgafb_init(SysBusDevice *dev)
	279	{
	280	MilkymistVgafbState s = FROM_SYSBUS(typeof(s), dev);
d23948b1	281
883abf8d MW	282	memory_region_init_io(&s->regs_region, &vgafb_mmio_ops, s,
883abf8d MW	283	"milkymist-vgafb", R_MAX * 4);
750ecd44	284	sysbus_init_mmio(dev, &s->regs_region);
d23948b1	285
aa2beaa1	286	s->con = graphic_console_init(DEVICE(dev), &vgafb_ops, s);
d23948b1 MW	287
	288	return 0;
	289	}
	290
	291	static int vgafb_post_load(void *opaque, int version_id)
	292	{
	293	vgafb_invalidate_display(opaque);
	294	return 0;
	295	}
	296
	297	static const VMStateDescription vmstate_milkymist_vgafb = {
	298	.name = "milkymist-vgafb",
	299	.version_id = 1,
	300	.minimum_version_id = 1,
	301	.minimum_version_id_old = 1,
	302	.post_load = vgafb_post_load,
	303	.fields = (VMStateField[]) {
	304	VMSTATE_UINT32_ARRAY(regs, MilkymistVgafbState, R_MAX),
	305	VMSTATE_END_OF_LIST()
	306	}
	307	};
	308
999e12bb AL	309	static Property milkymist_vgafb_properties[] = {
	310	DEFINE_PROP_UINT32("fb_offset", MilkymistVgafbState, fb_offset, 0x0),
	311	DEFINE_PROP_UINT32("fb_mask", MilkymistVgafbState, fb_mask, 0xffffffff),
	312	DEFINE_PROP_END_OF_LIST(),
	313	};
	314
	315	static void milkymist_vgafb_class_init(ObjectClass klass, void data)
	316	{
39bffca2	317	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	318	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	319
	320	k->init = milkymist_vgafb_init;
39bffca2 AL	321	dc->reset = milkymist_vgafb_reset;
	322	dc->vmsd = &vmstate_milkymist_vgafb;
	323	dc->props = milkymist_vgafb_properties;
999e12bb AL	324	}
999e12bb AL	325
8c43a6f0	326	static const TypeInfo milkymist_vgafb_info = {
39bffca2 AL	327	.name = "milkymist-vgafb",
	328	.parent = TYPE_SYS_BUS_DEVICE,
	329	.instance_size = sizeof(MilkymistVgafbState),
	330	.class_init = milkymist_vgafb_class_init,
d23948b1 MW	331	};
d23948b1 MW	332
83f7d43a	333	static void milkymist_vgafb_register_types(void)
d23948b1	334	{
39bffca2	335	type_register_static(&milkymist_vgafb_info);
d23948b1 MW	336	}
d23948b1 MW	337
83f7d43a	338	type_init(milkymist_vgafb_register_types)