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96d0e26c WG |
1 | /* |
2 | * NUMA parameter parsing routines | |
3 | * | |
4 | * Copyright (c) 2014 Fujitsu Ltd. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
e35704ba | 25 | #include "sysemu/numa.h" |
96d0e26c WG |
26 | #include "exec/cpu-common.h" |
27 | #include "qemu/bitmap.h" | |
28 | #include "qom/cpu.h" | |
2b631ec2 WG |
29 | #include "qemu/error-report.h" |
30 | #include "include/exec/cpu-common.h" /* for RAM_ADDR_FMT */ | |
0042109a WG |
31 | #include "qapi-visit.h" |
32 | #include "qapi/opts-visitor.h" | |
33 | #include "qapi/dealloc-visitor.h" | |
dfabb8b9 | 34 | #include "hw/boards.h" |
7febe36f | 35 | #include "sysemu/hostmem.h" |
76b5d850 | 36 | #include "qmp-commands.h" |
5b009e40 | 37 | #include "hw/mem/pc-dimm.h" |
7dcd1d70 EH |
38 | #include "qemu/option.h" |
39 | #include "qemu/config-file.h" | |
0042109a WG |
40 | |
41 | QemuOptsList qemu_numa_opts = { | |
42 | .name = "numa", | |
43 | .implied_opt_name = "type", | |
44 | .head = QTAILQ_HEAD_INITIALIZER(qemu_numa_opts.head), | |
45 | .desc = { { 0 } } /* validated with OptsVisitor */ | |
46 | }; | |
47 | ||
7febe36f | 48 | static int have_memdevs = -1; |
25712ffe EH |
49 | static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one. |
50 | * For all nodes, nodeid < max_numa_nodeid | |
51 | */ | |
de1a7c84 | 52 | int nb_numa_nodes; |
de1a7c84 | 53 | NodeInfo numa_info[MAX_NODES]; |
7febe36f | 54 | |
fa9ea81d BR |
55 | void numa_set_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node) |
56 | { | |
672558d2 | 57 | struct numa_addr_range *range; |
fa9ea81d | 58 | |
abafabd8 BR |
59 | /* |
60 | * Memory-less nodes can come here with 0 size in which case, | |
61 | * there is nothing to do. | |
62 | */ | |
63 | if (!size) { | |
64 | return; | |
65 | } | |
66 | ||
672558d2 | 67 | range = g_malloc0(sizeof(*range)); |
fa9ea81d BR |
68 | range->mem_start = addr; |
69 | range->mem_end = addr + size - 1; | |
70 | QLIST_INSERT_HEAD(&numa_info[node].addr, range, entry); | |
71 | } | |
72 | ||
73 | void numa_unset_mem_node_id(ram_addr_t addr, uint64_t size, uint32_t node) | |
74 | { | |
75 | struct numa_addr_range *range, *next; | |
76 | ||
77 | QLIST_FOREACH_SAFE(range, &numa_info[node].addr, entry, next) { | |
78 | if (addr == range->mem_start && (addr + size - 1) == range->mem_end) { | |
79 | QLIST_REMOVE(range, entry); | |
80 | g_free(range); | |
81 | return; | |
82 | } | |
83 | } | |
84 | } | |
85 | ||
abafabd8 BR |
86 | static void numa_set_mem_ranges(void) |
87 | { | |
88 | int i; | |
89 | ram_addr_t mem_start = 0; | |
90 | ||
91 | /* | |
92 | * Deduce start address of each node and use it to store | |
93 | * the address range info in numa_info address range list | |
94 | */ | |
95 | for (i = 0; i < nb_numa_nodes; i++) { | |
96 | numa_set_mem_node_id(mem_start, numa_info[i].node_mem, i); | |
97 | mem_start += numa_info[i].node_mem; | |
98 | } | |
99 | } | |
100 | ||
e75e2a14 BR |
101 | /* |
102 | * Check if @addr falls under NUMA @node. | |
103 | */ | |
104 | static bool numa_addr_belongs_to_node(ram_addr_t addr, uint32_t node) | |
105 | { | |
106 | struct numa_addr_range *range; | |
107 | ||
108 | QLIST_FOREACH(range, &numa_info[node].addr, entry) { | |
109 | if (addr >= range->mem_start && addr <= range->mem_end) { | |
110 | return true; | |
111 | } | |
112 | } | |
113 | return false; | |
114 | } | |
115 | ||
116 | /* | |
117 | * Given an address, return the index of the NUMA node to which the | |
118 | * address belongs to. | |
119 | */ | |
120 | uint32_t numa_get_node(ram_addr_t addr, Error **errp) | |
121 | { | |
122 | uint32_t i; | |
123 | ||
124 | /* For non NUMA configurations, check if the addr falls under node 0 */ | |
125 | if (!nb_numa_nodes) { | |
126 | if (numa_addr_belongs_to_node(addr, 0)) { | |
127 | return 0; | |
128 | } | |
129 | } | |
130 | ||
131 | for (i = 0; i < nb_numa_nodes; i++) { | |
132 | if (numa_addr_belongs_to_node(addr, i)) { | |
133 | return i; | |
134 | } | |
135 | } | |
136 | ||
137 | error_setg(errp, "Address 0x" RAM_ADDR_FMT " doesn't belong to any " | |
138 | "NUMA node", addr); | |
139 | return -1; | |
140 | } | |
141 | ||
0042109a | 142 | static void numa_node_parse(NumaNodeOptions *node, QemuOpts *opts, Error **errp) |
96d0e26c | 143 | { |
0042109a WG |
144 | uint16_t nodenr; |
145 | uint16List *cpus = NULL; | |
96d0e26c | 146 | |
0042109a WG |
147 | if (node->has_nodeid) { |
148 | nodenr = node->nodeid; | |
96d0e26c | 149 | } else { |
0042109a | 150 | nodenr = nb_numa_nodes; |
96d0e26c WG |
151 | } |
152 | ||
0042109a WG |
153 | if (nodenr >= MAX_NODES) { |
154 | error_setg(errp, "Max number of NUMA nodes reached: %" | |
01bbbcf4 | 155 | PRIu16 "", nodenr); |
0042109a | 156 | return; |
96d0e26c WG |
157 | } |
158 | ||
1945b9d8 EH |
159 | if (numa_info[nodenr].present) { |
160 | error_setg(errp, "Duplicate NUMA nodeid: %" PRIu16, nodenr); | |
161 | return; | |
162 | } | |
163 | ||
0042109a | 164 | for (cpus = node->cpus; cpus; cpus = cpus->next) { |
8979c945 EH |
165 | if (cpus->value >= max_cpus) { |
166 | error_setg(errp, | |
167 | "CPU index (%" PRIu16 ")" | |
168 | " should be smaller than maxcpus (%d)", | |
169 | cpus->value, max_cpus); | |
0042109a WG |
170 | return; |
171 | } | |
172 | bitmap_set(numa_info[nodenr].node_cpu, cpus->value, 1); | |
96d0e26c WG |
173 | } |
174 | ||
7febe36f | 175 | if (node->has_mem && node->has_memdev) { |
01bbbcf4 | 176 | error_setg(errp, "qemu: cannot specify both mem= and memdev="); |
7febe36f PB |
177 | return; |
178 | } | |
179 | ||
180 | if (have_memdevs == -1) { | |
181 | have_memdevs = node->has_memdev; | |
182 | } | |
183 | if (node->has_memdev != have_memdevs) { | |
184 | error_setg(errp, "qemu: memdev option must be specified for either " | |
01bbbcf4 | 185 | "all or no nodes"); |
7febe36f PB |
186 | return; |
187 | } | |
188 | ||
0042109a WG |
189 | if (node->has_mem) { |
190 | uint64_t mem_size = node->mem; | |
191 | const char *mem_str = qemu_opt_get(opts, "mem"); | |
192 | /* Fix up legacy suffix-less format */ | |
193 | if (g_ascii_isdigit(mem_str[strlen(mem_str) - 1])) { | |
194 | mem_size <<= 20; | |
195 | } | |
196 | numa_info[nodenr].node_mem = mem_size; | |
197 | } | |
7febe36f PB |
198 | if (node->has_memdev) { |
199 | Object *o; | |
200 | o = object_resolve_path_type(node->memdev, TYPE_MEMORY_BACKEND, NULL); | |
201 | if (!o) { | |
202 | error_setg(errp, "memdev=%s is ambiguous", node->memdev); | |
203 | return; | |
204 | } | |
205 | ||
206 | object_ref(o); | |
207 | numa_info[nodenr].node_mem = object_property_get_int(o, "size", NULL); | |
208 | numa_info[nodenr].node_memdev = MEMORY_BACKEND(o); | |
209 | } | |
1af878e0 EH |
210 | numa_info[nodenr].present = true; |
211 | max_numa_nodeid = MAX(max_numa_nodeid, nodenr + 1); | |
96d0e26c WG |
212 | } |
213 | ||
28d0de7a | 214 | static int parse_numa(void *opaque, QemuOpts *opts, Error **errp) |
96d0e26c | 215 | { |
0042109a WG |
216 | NumaOptions *object = NULL; |
217 | Error *err = NULL; | |
96d0e26c | 218 | |
0042109a WG |
219 | { |
220 | OptsVisitor *ov = opts_visitor_new(opts); | |
221 | visit_type_NumaOptions(opts_get_visitor(ov), &object, NULL, &err); | |
222 | opts_visitor_cleanup(ov); | |
96d0e26c | 223 | } |
96d0e26c | 224 | |
0042109a WG |
225 | if (err) { |
226 | goto error; | |
227 | } | |
96d0e26c | 228 | |
0042109a WG |
229 | switch (object->kind) { |
230 | case NUMA_OPTIONS_KIND_NODE: | |
231 | numa_node_parse(object->node, opts, &err); | |
232 | if (err) { | |
233 | goto error; | |
96d0e26c | 234 | } |
0042109a WG |
235 | nb_numa_nodes++; |
236 | break; | |
237 | default: | |
238 | abort(); | |
239 | } | |
96d0e26c | 240 | |
0042109a | 241 | return 0; |
96d0e26c | 242 | |
0042109a | 243 | error: |
29b762f5 | 244 | error_report_err(err); |
0042109a WG |
245 | |
246 | if (object) { | |
247 | QapiDeallocVisitor *dv = qapi_dealloc_visitor_new(); | |
248 | visit_type_NumaOptions(qapi_dealloc_get_visitor(dv), | |
249 | &object, NULL, NULL); | |
250 | qapi_dealloc_visitor_cleanup(dv); | |
96d0e26c | 251 | } |
0042109a WG |
252 | |
253 | return -1; | |
96d0e26c WG |
254 | } |
255 | ||
3ef71975 EH |
256 | static char *enumerate_cpus(unsigned long *cpus, int max_cpus) |
257 | { | |
258 | int cpu; | |
259 | bool first = true; | |
260 | GString *s = g_string_new(NULL); | |
261 | ||
262 | for (cpu = find_first_bit(cpus, max_cpus); | |
263 | cpu < max_cpus; | |
264 | cpu = find_next_bit(cpus, max_cpus, cpu + 1)) { | |
265 | g_string_append_printf(s, "%s%d", first ? "" : " ", cpu); | |
266 | first = false; | |
267 | } | |
268 | return g_string_free(s, FALSE); | |
269 | } | |
270 | ||
271 | static void validate_numa_cpus(void) | |
272 | { | |
273 | int i; | |
274 | DECLARE_BITMAP(seen_cpus, MAX_CPUMASK_BITS); | |
275 | ||
276 | bitmap_zero(seen_cpus, MAX_CPUMASK_BITS); | |
277 | for (i = 0; i < nb_numa_nodes; i++) { | |
278 | if (bitmap_intersects(seen_cpus, numa_info[i].node_cpu, | |
279 | MAX_CPUMASK_BITS)) { | |
280 | bitmap_and(seen_cpus, seen_cpus, | |
281 | numa_info[i].node_cpu, MAX_CPUMASK_BITS); | |
282 | error_report("CPU(s) present in multiple NUMA nodes: %s", | |
a8f15a27 | 283 | enumerate_cpus(seen_cpus, max_cpus)); |
3ef71975 EH |
284 | exit(EXIT_FAILURE); |
285 | } | |
286 | bitmap_or(seen_cpus, seen_cpus, | |
287 | numa_info[i].node_cpu, MAX_CPUMASK_BITS); | |
288 | } | |
549fc54b EH |
289 | |
290 | if (!bitmap_full(seen_cpus, max_cpus)) { | |
291 | char *msg; | |
292 | bitmap_complement(seen_cpus, seen_cpus, max_cpus); | |
293 | msg = enumerate_cpus(seen_cpus, max_cpus); | |
294 | error_report("warning: CPU(s) not present in any NUMA nodes: %s", msg); | |
295 | error_report("warning: All CPU(s) up to maxcpus should be described " | |
296 | "in NUMA config"); | |
297 | g_free(msg); | |
298 | } | |
3ef71975 EH |
299 | } |
300 | ||
57924bcd | 301 | void parse_numa_opts(MachineClass *mc) |
96d0e26c | 302 | { |
12d6e464 EH |
303 | int i; |
304 | ||
28d0de7a | 305 | if (qemu_opts_foreach(qemu_find_opts("numa"), parse_numa, NULL, NULL)) { |
7dcd1d70 EH |
306 | exit(1); |
307 | } | |
308 | ||
12d6e464 EH |
309 | assert(max_numa_nodeid <= MAX_NODES); |
310 | ||
311 | /* No support for sparse NUMA node IDs yet: */ | |
312 | for (i = max_numa_nodeid - 1; i >= 0; i--) { | |
313 | /* Report large node IDs first, to make mistakes easier to spot */ | |
314 | if (!numa_info[i].present) { | |
315 | error_report("numa: Node ID missing: %d", i); | |
316 | exit(1); | |
317 | } | |
318 | } | |
319 | ||
320 | /* This must be always true if all nodes are present: */ | |
321 | assert(nb_numa_nodes == max_numa_nodeid); | |
322 | ||
96d0e26c | 323 | if (nb_numa_nodes > 0) { |
2b631ec2 | 324 | uint64_t numa_total; |
96d0e26c WG |
325 | |
326 | if (nb_numa_nodes > MAX_NODES) { | |
327 | nb_numa_nodes = MAX_NODES; | |
328 | } | |
329 | ||
9851d0fe | 330 | /* If no memory size is given for any node, assume the default case |
96d0e26c WG |
331 | * and distribute the available memory equally across all nodes |
332 | */ | |
333 | for (i = 0; i < nb_numa_nodes; i++) { | |
8c85901e | 334 | if (numa_info[i].node_mem != 0) { |
96d0e26c WG |
335 | break; |
336 | } | |
337 | } | |
338 | if (i == nb_numa_nodes) { | |
339 | uint64_t usedmem = 0; | |
340 | ||
d75e2f68 | 341 | /* On Linux, each node's border has to be 8MB aligned, |
96d0e26c WG |
342 | * the final node gets the rest. |
343 | */ | |
344 | for (i = 0; i < nb_numa_nodes - 1; i++) { | |
8c85901e WG |
345 | numa_info[i].node_mem = (ram_size / nb_numa_nodes) & |
346 | ~((1 << 23UL) - 1); | |
347 | usedmem += numa_info[i].node_mem; | |
96d0e26c | 348 | } |
8c85901e | 349 | numa_info[i].node_mem = ram_size - usedmem; |
96d0e26c WG |
350 | } |
351 | ||
2b631ec2 WG |
352 | numa_total = 0; |
353 | for (i = 0; i < nb_numa_nodes; i++) { | |
8c85901e | 354 | numa_total += numa_info[i].node_mem; |
2b631ec2 WG |
355 | } |
356 | if (numa_total != ram_size) { | |
c68233ae HT |
357 | error_report("total memory for NUMA nodes (0x%" PRIx64 ")" |
358 | " should equal RAM size (0x" RAM_ADDR_FMT ")", | |
2b631ec2 WG |
359 | numa_total, ram_size); |
360 | exit(1); | |
361 | } | |
362 | ||
fa9ea81d BR |
363 | for (i = 0; i < nb_numa_nodes; i++) { |
364 | QLIST_INIT(&numa_info[i].addr); | |
365 | } | |
366 | ||
abafabd8 BR |
367 | numa_set_mem_ranges(); |
368 | ||
96d0e26c | 369 | for (i = 0; i < nb_numa_nodes; i++) { |
8c85901e | 370 | if (!bitmap_empty(numa_info[i].node_cpu, MAX_CPUMASK_BITS)) { |
96d0e26c WG |
371 | break; |
372 | } | |
373 | } | |
57924bcd IM |
374 | /* Historically VCPUs were assigned in round-robin order to NUMA |
375 | * nodes. However it causes issues with guest not handling it nice | |
376 | * in case where cores/threads from a multicore CPU appear on | |
377 | * different nodes. So allow boards to override default distribution | |
378 | * rule grouping VCPUs by socket so that VCPUs from the same socket | |
379 | * would be on the same node. | |
96d0e26c WG |
380 | */ |
381 | if (i == nb_numa_nodes) { | |
382 | for (i = 0; i < max_cpus; i++) { | |
57924bcd IM |
383 | unsigned node_id = i % nb_numa_nodes; |
384 | if (mc->cpu_index_to_socket_id) { | |
385 | node_id = mc->cpu_index_to_socket_id(i) % nb_numa_nodes; | |
386 | } | |
387 | ||
388 | set_bit(i, numa_info[node_id].node_cpu); | |
96d0e26c WG |
389 | } |
390 | } | |
3ef71975 EH |
391 | |
392 | validate_numa_cpus(); | |
abafabd8 BR |
393 | } else { |
394 | numa_set_mem_node_id(0, ram_size, 0); | |
96d0e26c WG |
395 | } |
396 | } | |
397 | ||
dde11116 | 398 | void numa_post_machine_init(void) |
96d0e26c WG |
399 | { |
400 | CPUState *cpu; | |
401 | int i; | |
402 | ||
403 | CPU_FOREACH(cpu) { | |
404 | for (i = 0; i < nb_numa_nodes; i++) { | |
8c85901e | 405 | if (test_bit(cpu->cpu_index, numa_info[i].node_cpu)) { |
96d0e26c WG |
406 | cpu->numa_node = i; |
407 | } | |
408 | } | |
409 | } | |
410 | } | |
dfabb8b9 | 411 | |
7febe36f PB |
412 | static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner, |
413 | const char *name, | |
414 | uint64_t ram_size) | |
415 | { | |
0b183fc8 PB |
416 | if (mem_path) { |
417 | #ifdef __linux__ | |
7f56e740 | 418 | Error *err = NULL; |
dbcb8981 | 419 | memory_region_init_ram_from_file(mr, owner, name, ram_size, false, |
7f56e740 PB |
420 | mem_path, &err); |
421 | ||
422 | /* Legacy behavior: if allocation failed, fall back to | |
423 | * regular RAM allocation. | |
424 | */ | |
c3ba3095 | 425 | if (err) { |
29b762f5 | 426 | error_report_err(err); |
f8ed85ac | 427 | memory_region_init_ram(mr, owner, name, ram_size, &error_fatal); |
7f56e740 | 428 | } |
0b183fc8 PB |
429 | #else |
430 | fprintf(stderr, "-mem-path not supported on this host\n"); | |
431 | exit(1); | |
432 | #endif | |
433 | } else { | |
f8ed85ac | 434 | memory_region_init_ram(mr, owner, name, ram_size, &error_fatal); |
0b183fc8 | 435 | } |
7febe36f PB |
436 | vmstate_register_ram_global(mr); |
437 | } | |
438 | ||
dfabb8b9 PB |
439 | void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner, |
440 | const char *name, | |
441 | uint64_t ram_size) | |
442 | { | |
7febe36f PB |
443 | uint64_t addr = 0; |
444 | int i; | |
445 | ||
446 | if (nb_numa_nodes == 0 || !have_memdevs) { | |
447 | allocate_system_memory_nonnuma(mr, owner, name, ram_size); | |
448 | return; | |
449 | } | |
450 | ||
451 | memory_region_init(mr, owner, name, ram_size); | |
452 | for (i = 0; i < MAX_NODES; i++) { | |
453 | Error *local_err = NULL; | |
454 | uint64_t size = numa_info[i].node_mem; | |
455 | HostMemoryBackend *backend = numa_info[i].node_memdev; | |
456 | if (!backend) { | |
457 | continue; | |
458 | } | |
459 | MemoryRegion *seg = host_memory_backend_get_memory(backend, &local_err); | |
460 | if (local_err) { | |
29b762f5 | 461 | error_report_err(local_err); |
7febe36f PB |
462 | exit(1); |
463 | } | |
464 | ||
0462faee HT |
465 | if (memory_region_is_mapped(seg)) { |
466 | char *path = object_get_canonical_path_component(OBJECT(backend)); | |
467 | error_report("memory backend %s is used multiple times. Each " | |
468 | "-numa option must use a different memdev value.", | |
469 | path); | |
470 | exit(1); | |
471 | } | |
472 | ||
7febe36f PB |
473 | memory_region_add_subregion(mr, addr, seg); |
474 | vmstate_register_ram_global(seg); | |
475 | addr += size; | |
476 | } | |
dfabb8b9 | 477 | } |
76b5d850 | 478 | |
5b009e40 HZ |
479 | static void numa_stat_memory_devices(uint64_t node_mem[]) |
480 | { | |
481 | MemoryDeviceInfoList *info_list = NULL; | |
482 | MemoryDeviceInfoList **prev = &info_list; | |
483 | MemoryDeviceInfoList *info; | |
484 | ||
485 | qmp_pc_dimm_device_list(qdev_get_machine(), &prev); | |
486 | for (info = info_list; info; info = info->next) { | |
487 | MemoryDeviceInfo *value = info->value; | |
488 | ||
489 | if (value) { | |
490 | switch (value->kind) { | |
491 | case MEMORY_DEVICE_INFO_KIND_DIMM: | |
492 | node_mem[value->dimm->node] += value->dimm->size; | |
493 | break; | |
494 | default: | |
495 | break; | |
496 | } | |
497 | } | |
498 | } | |
499 | qapi_free_MemoryDeviceInfoList(info_list); | |
500 | } | |
501 | ||
502 | void query_numa_node_mem(uint64_t node_mem[]) | |
503 | { | |
504 | int i; | |
505 | ||
506 | if (nb_numa_nodes <= 0) { | |
507 | return; | |
508 | } | |
509 | ||
510 | numa_stat_memory_devices(node_mem); | |
511 | for (i = 0; i < nb_numa_nodes; i++) { | |
512 | node_mem[i] += numa_info[i].node_mem; | |
513 | } | |
514 | } | |
515 | ||
76b5d850 HT |
516 | static int query_memdev(Object *obj, void *opaque) |
517 | { | |
518 | MemdevList **list = opaque; | |
b0e90181 | 519 | MemdevList *m = NULL; |
76b5d850 HT |
520 | Error *err = NULL; |
521 | ||
522 | if (object_dynamic_cast(obj, TYPE_MEMORY_BACKEND)) { | |
b0e90181 | 523 | m = g_malloc0(sizeof(*m)); |
76b5d850 HT |
524 | |
525 | m->value = g_malloc0(sizeof(*m->value)); | |
526 | ||
527 | m->value->size = object_property_get_int(obj, "size", | |
528 | &err); | |
529 | if (err) { | |
530 | goto error; | |
531 | } | |
532 | ||
533 | m->value->merge = object_property_get_bool(obj, "merge", | |
534 | &err); | |
535 | if (err) { | |
536 | goto error; | |
537 | } | |
538 | ||
539 | m->value->dump = object_property_get_bool(obj, "dump", | |
540 | &err); | |
541 | if (err) { | |
542 | goto error; | |
543 | } | |
544 | ||
545 | m->value->prealloc = object_property_get_bool(obj, | |
546 | "prealloc", &err); | |
547 | if (err) { | |
548 | goto error; | |
549 | } | |
550 | ||
551 | m->value->policy = object_property_get_enum(obj, | |
552 | "policy", | |
a3590dac | 553 | "HostMemPolicy", |
76b5d850 HT |
554 | &err); |
555 | if (err) { | |
556 | goto error; | |
557 | } | |
558 | ||
559 | object_property_get_uint16List(obj, "host-nodes", | |
560 | &m->value->host_nodes, &err); | |
561 | if (err) { | |
562 | goto error; | |
563 | } | |
564 | ||
565 | m->next = *list; | |
566 | *list = m; | |
567 | } | |
568 | ||
569 | return 0; | |
570 | error: | |
b0e90181 CF |
571 | g_free(m->value); |
572 | g_free(m); | |
573 | ||
76b5d850 HT |
574 | return -1; |
575 | } | |
576 | ||
577 | MemdevList *qmp_query_memdev(Error **errp) | |
578 | { | |
579 | Object *obj; | |
ecaf54a0 | 580 | MemdevList *list = NULL; |
76b5d850 | 581 | |
bc2256c4 | 582 | obj = object_get_objects_root(); |
76b5d850 HT |
583 | if (obj == NULL) { |
584 | return NULL; | |
585 | } | |
586 | ||
587 | if (object_child_foreach(obj, query_memdev, &list) != 0) { | |
588 | goto error; | |
589 | } | |
590 | ||
591 | return list; | |
592 | ||
593 | error: | |
ecaf54a0 | 594 | qapi_free_MemdevList(list); |
76b5d850 HT |
595 | return NULL; |
596 | } |