[qemu.git] / hw / misc / tz-ppc.c

/*
 * ARM TrustZone peripheral protection controller emulation
 *
 * Copyright (c) 2018 Linaro Limited
 * Written by Peter Maydell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 or
 * (at your option) any later version.
 */

#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qapi/error.h"
#include "trace.h"
#include "hw/sysbus.h"
#include "hw/registerfields.h"
#include "hw/misc/tz-ppc.h"

static void tz_ppc_update_irq(TZPPC *s)
{
    bool level = s->irq_status && s->irq_enable;

    trace_tz_ppc_update_irq(level);
    qemu_set_irq(s->irq, level);
}

static void tz_ppc_cfg_nonsec(void *opaque, int n, int level)
{
    TZPPC *s = TZ_PPC(opaque);

    assert(n < TZ_NUM_PORTS);
    trace_tz_ppc_cfg_nonsec(n, level);
    s->cfg_nonsec[n] = level;
}

static void tz_ppc_cfg_ap(void *opaque, int n, int level)
{
    TZPPC *s = TZ_PPC(opaque);

    assert(n < TZ_NUM_PORTS);
    trace_tz_ppc_cfg_ap(n, level);
    s->cfg_ap[n] = level;
}

static void tz_ppc_cfg_sec_resp(void *opaque, int n, int level)
{
    TZPPC *s = TZ_PPC(opaque);

    trace_tz_ppc_cfg_sec_resp(level);
    s->cfg_sec_resp = level;
}

static void tz_ppc_irq_enable(void *opaque, int n, int level)
{
    TZPPC *s = TZ_PPC(opaque);

    trace_tz_ppc_irq_enable(level);
    s->irq_enable = level;
    tz_ppc_update_irq(s);
}

static void tz_ppc_irq_clear(void *opaque, int n, int level)
{
    TZPPC *s = TZ_PPC(opaque);

    trace_tz_ppc_irq_clear(level);

    s->irq_clear = level;
    if (level) {
        s->irq_status = false;
        tz_ppc_update_irq(s);
    }
}

static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs)
{
    /* Check whether to allow an access to port n; return true if
     * the check passes, and false if the transaction must be blocked.
     * If the latter, the caller must check cfg_sec_resp to determine
     * whether to abort or RAZ/WI the transaction.
     * The checks are:
     *  + nonsec_mask suppresses any check of the secure attribute
     *  + otherwise, block if cfg_nonsec is 1 and transaction is secure,
     *    or if cfg_nonsec is 0 and transaction is non-secure
     *  + block if transaction is usermode and cfg_ap is 0
     */
    if ((attrs.secure == s->cfg_nonsec[n] && !(s->nonsec_mask & (1 << n))) ||
        (attrs.user && !s->cfg_ap[n])) {
        /* Block the transaction. */
        if (!s->irq_clear) {
            /* Note that holding irq_clear high suppresses interrupts */
            s->irq_status = true;
            tz_ppc_update_irq(s);
        }
        return false;
    }
    return true;
}

static MemTxResult tz_ppc_read(void *opaque, hwaddr addr, uint64_t *pdata,
                               unsigned size, MemTxAttrs attrs)
{
    TZPPCPort *p = opaque;
    TZPPC *s = p->ppc;
    int n = p - s->port;
    AddressSpace *as = &p->downstream_as;
    uint64_t data;
    MemTxResult res;

    if (!tz_ppc_check(s, n, attrs)) {
        trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user);
        if (s->cfg_sec_resp) {
            return MEMTX_ERROR;
        } else {
            *pdata = 0;
            return MEMTX_OK;
        }
    }

    switch (size) {
    case 1:
        data = address_space_ldub(as, addr, attrs, &res);
        break;
    case 2:
        data = address_space_lduw_le(as, addr, attrs, &res);
        break;
    case 4:
        data = address_space_ldl_le(as, addr, attrs, &res);
        break;
    case 8:
        data = address_space_ldq_le(as, addr, attrs, &res);
        break;
    default:
        g_assert_not_reached();
    }
    *pdata = data;
    return res;
}

static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val,
                                unsigned size, MemTxAttrs attrs)
{
    TZPPCPort *p = opaque;
    TZPPC *s = p->ppc;
    AddressSpace *as = &p->downstream_as;
    int n = p - s->port;
    MemTxResult res;

    if (!tz_ppc_check(s, n, attrs)) {
        trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user);
        if (s->cfg_sec_resp) {
            return MEMTX_ERROR;
        } else {
            return MEMTX_OK;
        }
    }

    switch (size) {
    case 1:
        address_space_stb(as, addr, val, attrs, &res);
        break;
    case 2:
        address_space_stw_le(as, addr, val, attrs, &res);
        break;
    case 4:
        address_space_stl_le(as, addr, val, attrs, &res);
        break;
    case 8:
        address_space_stq_le(as, addr, val, attrs, &res);
        break;
    default:
        g_assert_not_reached();
    }
    return res;
}

static const MemoryRegionOps tz_ppc_ops = {
    .read_with_attrs = tz_ppc_read,
    .write_with_attrs = tz_ppc_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void tz_ppc_reset(DeviceState *dev)
{
    TZPPC *s = TZ_PPC(dev);

    trace_tz_ppc_reset();
    s->cfg_sec_resp = false;
    memset(s->cfg_nonsec, 0, sizeof(s->cfg_nonsec));
    memset(s->cfg_ap, 0, sizeof(s->cfg_ap));
}

static void tz_ppc_init(Object *obj)
{
    DeviceState *dev = DEVICE(obj);
    TZPPC *s = TZ_PPC(obj);

    qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS);
    qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS);
    qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1);
    qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1);
    qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1);
    qdev_init_gpio_out_named(dev, &s->irq, "irq", 1);
}

static void tz_ppc_realize(DeviceState *dev, Error **errp)
{
    Object *obj = OBJECT(dev);
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    TZPPC *s = TZ_PPC(dev);
    int i;

    /* We can't create the upstream end of the port until realize,
     * as we don't know the size of the MR used as the downstream until then.
     */
    for (i = 0; i < TZ_NUM_PORTS; i++) {
        TZPPCPort *port = &s->port[i];
        char *name;
        uint64_t size;

        if (!port->downstream) {
            continue;
        }

        name = g_strdup_printf("tz-ppc-port[%d]", i);

        port->ppc = s;
        address_space_init(&port->downstream_as, port->downstream, name);

        size = memory_region_size(port->downstream);
        memory_region_init_io(&port->upstream, obj, &tz_ppc_ops,
                              port, name, size);
        sysbus_init_mmio(sbd, &port->upstream);
        g_free(name);
    }
}

static const VMStateDescription tz_ppc_vmstate = {
    .name = "tz-ppc",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16),
        VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16),
        VMSTATE_BOOL(cfg_sec_resp, TZPPC),
        VMSTATE_BOOL(irq_enable, TZPPC),
        VMSTATE_BOOL(irq_clear, TZPPC),
        VMSTATE_BOOL(irq_status, TZPPC),
        VMSTATE_END_OF_LIST()
    }
};

#define DEFINE_PORT(N)                                          \
    DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \
                     TYPE_MEMORY_REGION, MemoryRegion *)

static Property tz_ppc_properties[] = {
    DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0),
    DEFINE_PORT(0),
    DEFINE_PORT(1),
    DEFINE_PORT(2),
    DEFINE_PORT(3),
    DEFINE_PORT(4),
    DEFINE_PORT(5),
    DEFINE_PORT(6),
    DEFINE_PORT(7),
    DEFINE_PORT(8),
    DEFINE_PORT(9),
    DEFINE_PORT(10),
    DEFINE_PORT(11),
    DEFINE_PORT(12),
    DEFINE_PORT(13),
    DEFINE_PORT(14),
    DEFINE_PORT(15),
    DEFINE_PROP_END_OF_LIST(),
};

static void tz_ppc_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = tz_ppc_realize;
    dc->vmsd = &tz_ppc_vmstate;
    dc->reset = tz_ppc_reset;
    dc->props = tz_ppc_properties;
}

static const TypeInfo tz_ppc_info = {
    .name = TYPE_TZ_PPC,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(TZPPC),
    .instance_init = tz_ppc_init,
    .class_init = tz_ppc_class_init,
};

static void tz_ppc_register_types(void)
{
    type_register_static(&tz_ppc_info);
}

type_init(tz_ppc_register_types);
Commit	Line	Data
9eb8040c PM	1	/*
	2	* ARM TrustZone peripheral protection controller emulation
	3	*
	4	* Copyright (c) 2018 Linaro Limited
	5	* Written by Peter Maydell
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include "qemu/osdep.h"
	13	#include "qemu/log.h"
	14	#include "qapi/error.h"
	15	#include "trace.h"
	16	#include "hw/sysbus.h"
	17	#include "hw/registerfields.h"
	18	#include "hw/misc/tz-ppc.h"
	19
	20	static void tz_ppc_update_irq(TZPPC *s)
	21	{
	22	bool level = s->irq_status && s->irq_enable;
	23
	24	trace_tz_ppc_update_irq(level);
	25	qemu_set_irq(s->irq, level);
	26	}
	27
	28	static void tz_ppc_cfg_nonsec(void *opaque, int n, int level)
	29	{
	30	TZPPC *s = TZ_PPC(opaque);
	31
	32	assert(n < TZ_NUM_PORTS);
	33	trace_tz_ppc_cfg_nonsec(n, level);
	34	s->cfg_nonsec[n] = level;
	35	}
	36
	37	static void tz_ppc_cfg_ap(void *opaque, int n, int level)
	38	{
	39	TZPPC *s = TZ_PPC(opaque);
	40
	41	assert(n < TZ_NUM_PORTS);
	42	trace_tz_ppc_cfg_ap(n, level);
	43	s->cfg_ap[n] = level;
	44	}
	45
	46	static void tz_ppc_cfg_sec_resp(void *opaque, int n, int level)
	47	{
	48	TZPPC *s = TZ_PPC(opaque);
	49
	50	trace_tz_ppc_cfg_sec_resp(level);
	51	s->cfg_sec_resp = level;
	52	}
	53
	54	static void tz_ppc_irq_enable(void *opaque, int n, int level)
	55	{
	56	TZPPC *s = TZ_PPC(opaque);
	57
	58	trace_tz_ppc_irq_enable(level);
	59	s->irq_enable = level;
	60	tz_ppc_update_irq(s);
	61	}
	62
	63	static void tz_ppc_irq_clear(void *opaque, int n, int level)
	64	{
65	TZPPC *s = TZ_PPC(opaque);
66
67	trace_tz_ppc_irq_clear(level);
68
69	s->irq_clear = level;
70	if (level) {
71	s->irq_status = false;
72	tz_ppc_update_irq(s);
73	}
74	}
75
76	static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs)
77	{
78	/* Check whether to allow an access to port n; return true if
79	* the check passes, and false if the transaction must be blocked.
80	* If the latter, the caller must check cfg_sec_resp to determine
81	* whether to abort or RAZ/WI the transaction.
82	* The checks are:
83	* + nonsec_mask suppresses any check of the secure attribute
84	* + otherwise, block if cfg_nonsec is 1 and transaction is secure,
85	* or if cfg_nonsec is 0 and transaction is non-secure
86	* + block if transaction is usermode and cfg_ap is 0
87	*/
88	if ((attrs.secure == s->cfg_nonsec[n] && !(s->nonsec_mask & (1 << n))) \|\|
89	(attrs.user && !s->cfg_ap[n])) {
90	/* Block the transaction. */
91	if (!s->irq_clear) {
92	/* Note that holding irq_clear high suppresses interrupts */
93	s->irq_status = true;
94	tz_ppc_update_irq(s);
95	}
96	return false;
97	}
98	return true;
99	}
100
101	static MemTxResult tz_ppc_read(void opaque, hwaddr addr, uint64_t pdata,
102	unsigned size, MemTxAttrs attrs)
103	{
104	TZPPCPort *p = opaque;
105	TZPPC *s = p->ppc;
106	int n = p - s->port;
107	AddressSpace *as = &p->downstream_as;
108	uint64_t data;
109	MemTxResult res;
110
111	if (!tz_ppc_check(s, n, attrs)) {
112	trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user);
113	if (s->cfg_sec_resp) {
114	return MEMTX_ERROR;
115	} else {
116	*pdata = 0;
117	return MEMTX_OK;
118	}
119	}
120
121	switch (size) {
122	case 1:
123	data = address_space_ldub(as, addr, attrs, &res);
124	break;
125	case 2:
126	data = address_space_lduw_le(as, addr, attrs, &res);
127	break;
128	case 4:
129	data = address_space_ldl_le(as, addr, attrs, &res);
130	break;
131	case 8:
132	data = address_space_ldq_le(as, addr, attrs, &res);
133	break;
134	default:
135	g_assert_not_reached();
136	}
137	*pdata = data;
138	return res;
139	}
140
141	static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val,
142	unsigned size, MemTxAttrs attrs)
143	{
144	TZPPCPort *p = opaque;
145	TZPPC *s = p->ppc;
146	AddressSpace *as = &p->downstream_as;
147	int n = p - s->port;
148	MemTxResult res;
149
150	if (!tz_ppc_check(s, n, attrs)) {
151	trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user);
152	if (s->cfg_sec_resp) {
153	return MEMTX_ERROR;
154	} else {
155	return MEMTX_OK;
156	}
157	}
158
159	switch (size) {
160	case 1:
161	address_space_stb(as, addr, val, attrs, &res);
162	break;
163	case 2:
164	address_space_stw_le(as, addr, val, attrs, &res);
165	break;
166	case 4:
167	address_space_stl_le(as, addr, val, attrs, &res);
168	break;
169	case 8:
170	address_space_stq_le(as, addr, val, attrs, &res);
171	break;
172	default:
173	g_assert_not_reached();
174	}
175	return res;
176	}
177
178	static const MemoryRegionOps tz_ppc_ops = {
179	.read_with_attrs = tz_ppc_read,
180	.write_with_attrs = tz_ppc_write,
181	.endianness = DEVICE_LITTLE_ENDIAN,
182	};
183
184	static void tz_ppc_reset(DeviceState *dev)
185	{
186	TZPPC *s = TZ_PPC(dev);
187
188	trace_tz_ppc_reset();
189	s->cfg_sec_resp = false;
190	memset(s->cfg_nonsec, 0, sizeof(s->cfg_nonsec));
191	memset(s->cfg_ap, 0, sizeof(s->cfg_ap));
192	}
193
194	static void tz_ppc_init(Object *obj)
195	{
196	DeviceState *dev = DEVICE(obj);
197	TZPPC *s = TZ_PPC(obj);
198
199	qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS);
200	qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS);
201	qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1);
202	qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1);
203	qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1);
204	qdev_init_gpio_out_named(dev, &s->irq, "irq", 1);
205	}
206
207	static void tz_ppc_realize(DeviceState dev, Error *errp)
208	{
209	Object *obj = OBJECT(dev);
210	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
211	TZPPC *s = TZ_PPC(dev);
212	int i;
213
214	/* We can't create the upstream end of the port until realize,
215	* as we don't know the size of the MR used as the downstream until then.
216	*/
217	for (i = 0; i < TZ_NUM_PORTS; i++) {
218	TZPPCPort *port = &s->port[i];
219	char *name;
220	uint64_t size;
221
222	if (!port->downstream) {
223	continue;
224	}
225
226	name = g_strdup_printf("tz-ppc-port[%d]", i);
227
228	port->ppc = s;
229	address_space_init(&port->downstream_as, port->downstream, name);
230
231	size = memory_region_size(port->downstream);
232	memory_region_init_io(&port->upstream, obj, &tz_ppc_ops,
233	port, name, size);
234	sysbus_init_mmio(sbd, &port->upstream);
235	g_free(name);
236	}
237	}
238
239	static const VMStateDescription tz_ppc_vmstate = {
240	.name = "tz-ppc",
241	.version_id = 1,
242	.minimum_version_id = 1,
243	.fields = (VMStateField[]) {
244	VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16),
245	VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16),
246	VMSTATE_BOOL(cfg_sec_resp, TZPPC),
247	VMSTATE_BOOL(irq_enable, TZPPC),
248	VMSTATE_BOOL(irq_clear, TZPPC),
249	VMSTATE_BOOL(irq_status, TZPPC),
250	VMSTATE_END_OF_LIST()
251	}
252	};
253
254	#define DEFINE_PORT(N) \
255	DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \
256	TYPE_MEMORY_REGION, MemoryRegion *)
257
258	static Property tz_ppc_properties[] = {
259	DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0),
260	DEFINE_PORT(0),
261	DEFINE_PORT(1),
262	DEFINE_PORT(2),
263	DEFINE_PORT(3),
264	DEFINE_PORT(4),
265	DEFINE_PORT(5),
266	DEFINE_PORT(6),
267	DEFINE_PORT(7),
268	DEFINE_PORT(8),
269	DEFINE_PORT(9),
270	DEFINE_PORT(10),
271	DEFINE_PORT(11),
272	DEFINE_PORT(12),
273	DEFINE_PORT(13),
274	DEFINE_PORT(14),
275	DEFINE_PORT(15),
276	DEFINE_PROP_END_OF_LIST(),
277	};
278
279	static void tz_ppc_class_init(ObjectClass klass, void data)
280	{
281	DeviceClass *dc = DEVICE_CLASS(klass);
282
283	dc->realize = tz_ppc_realize;
284	dc->vmsd = &tz_ppc_vmstate;
285	dc->reset = tz_ppc_reset;
286	dc->props = tz_ppc_properties;
287	}
288
289	static const TypeInfo tz_ppc_info = {
290	.name = TYPE_TZ_PPC,
291	.parent = TYPE_SYS_BUS_DEVICE,
292	.instance_size = sizeof(TZPPC),
293	.instance_init = tz_ppc_init,
294	.class_init = tz_ppc_class_init,
295	};
296
297	static void tz_ppc_register_types(void)
298	{
299	type_register_static(&tz_ppc_info);
300	}
301
302	type_init(tz_ppc_register_types);