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e4dc6d2c MW |
1 | /* |
2 | * QEMU model of the Milkymist High Performance Dynamic Memory Controller. | |
3 | * | |
4 | * Copyright (c) 2010 Michael Walle <[email protected]> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | * | |
20 | * Specification available at: | |
6dbbe243 | 21 | * http://milkymist.walle.cc/socdoc/hpdmc.pdf |
e4dc6d2c MW |
22 | */ |
23 | ||
ea99dde1 | 24 | #include "qemu/osdep.h" |
83c9f4ca PB |
25 | #include "hw/hw.h" |
26 | #include "hw/sysbus.h" | |
e4dc6d2c | 27 | #include "trace.h" |
1de7afc9 | 28 | #include "qemu/error-report.h" |
e4dc6d2c MW |
29 | |
30 | enum { | |
31 | R_SYSTEM = 0, | |
32 | R_BYPASS, | |
33 | R_TIMING, | |
34 | R_IODELAY, | |
35 | R_MAX | |
36 | }; | |
37 | ||
38 | enum { | |
39 | IODELAY_DQSDELAY_RDY = (1<<5), | |
40 | IODELAY_PLL1_LOCKED = (1<<6), | |
41 | IODELAY_PLL2_LOCKED = (1<<7), | |
42 | }; | |
43 | ||
829617a9 AF |
44 | #define TYPE_MILKYMIST_HPDMC "milkymist-hpdmc" |
45 | #define MILKYMIST_HPDMC(obj) \ | |
46 | OBJECT_CHECK(MilkymistHpdmcState, (obj), TYPE_MILKYMIST_HPDMC) | |
47 | ||
e4dc6d2c | 48 | struct MilkymistHpdmcState { |
829617a9 AF |
49 | SysBusDevice parent_obj; |
50 | ||
321c17ae | 51 | MemoryRegion regs_region; |
e4dc6d2c MW |
52 | |
53 | uint32_t regs[R_MAX]; | |
54 | }; | |
55 | typedef struct MilkymistHpdmcState MilkymistHpdmcState; | |
56 | ||
a8170e5e | 57 | static uint64_t hpdmc_read(void *opaque, hwaddr addr, |
321c17ae | 58 | unsigned size) |
e4dc6d2c MW |
59 | { |
60 | MilkymistHpdmcState *s = opaque; | |
61 | uint32_t r = 0; | |
62 | ||
63 | addr >>= 2; | |
64 | switch (addr) { | |
65 | case R_SYSTEM: | |
66 | case R_BYPASS: | |
67 | case R_TIMING: | |
68 | case R_IODELAY: | |
69 | r = s->regs[addr]; | |
70 | break; | |
71 | ||
72 | default: | |
73 | error_report("milkymist_hpdmc: read access to unknown register 0x" | |
74 | TARGET_FMT_plx, addr << 2); | |
75 | break; | |
76 | } | |
77 | ||
78 | trace_milkymist_hpdmc_memory_read(addr << 2, r); | |
79 | ||
80 | return r; | |
81 | } | |
82 | ||
a8170e5e | 83 | static void hpdmc_write(void *opaque, hwaddr addr, uint64_t value, |
321c17ae | 84 | unsigned size) |
e4dc6d2c MW |
85 | { |
86 | MilkymistHpdmcState *s = opaque; | |
87 | ||
88 | trace_milkymist_hpdmc_memory_write(addr, value); | |
89 | ||
90 | addr >>= 2; | |
91 | switch (addr) { | |
92 | case R_SYSTEM: | |
93 | case R_BYPASS: | |
94 | case R_TIMING: | |
95 | s->regs[addr] = value; | |
96 | break; | |
97 | case R_IODELAY: | |
98 | /* ignore writes */ | |
99 | break; | |
100 | ||
101 | default: | |
102 | error_report("milkymist_hpdmc: write access to unknown register 0x" | |
103 | TARGET_FMT_plx, addr << 2); | |
104 | break; | |
105 | } | |
106 | } | |
107 | ||
321c17ae MW |
108 | static const MemoryRegionOps hpdmc_mmio_ops = { |
109 | .read = hpdmc_read, | |
110 | .write = hpdmc_write, | |
111 | .valid = { | |
112 | .min_access_size = 4, | |
113 | .max_access_size = 4, | |
114 | }, | |
115 | .endianness = DEVICE_NATIVE_ENDIAN, | |
e4dc6d2c MW |
116 | }; |
117 | ||
118 | static void milkymist_hpdmc_reset(DeviceState *d) | |
119 | { | |
829617a9 | 120 | MilkymistHpdmcState *s = MILKYMIST_HPDMC(d); |
e4dc6d2c MW |
121 | int i; |
122 | ||
123 | for (i = 0; i < R_MAX; i++) { | |
124 | s->regs[i] = 0; | |
125 | } | |
126 | ||
127 | /* defaults */ | |
128 | s->regs[R_IODELAY] = IODELAY_DQSDELAY_RDY | IODELAY_PLL1_LOCKED | |
129 | | IODELAY_PLL2_LOCKED; | |
130 | } | |
131 | ||
0f2eabce | 132 | static void milkymist_hpdmc_realize(DeviceState *dev, Error **errp) |
e4dc6d2c | 133 | { |
829617a9 | 134 | MilkymistHpdmcState *s = MILKYMIST_HPDMC(dev); |
e4dc6d2c | 135 | |
3c161542 | 136 | memory_region_init_io(&s->regs_region, OBJECT(dev), &hpdmc_mmio_ops, s, |
321c17ae | 137 | "milkymist-hpdmc", R_MAX * 4); |
0f2eabce | 138 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->regs_region); |
e4dc6d2c MW |
139 | } |
140 | ||
141 | static const VMStateDescription vmstate_milkymist_hpdmc = { | |
142 | .name = "milkymist-hpdmc", | |
143 | .version_id = 1, | |
144 | .minimum_version_id = 1, | |
35d08458 | 145 | .fields = (VMStateField[]) { |
e4dc6d2c MW |
146 | VMSTATE_UINT32_ARRAY(regs, MilkymistHpdmcState, R_MAX), |
147 | VMSTATE_END_OF_LIST() | |
148 | } | |
149 | }; | |
150 | ||
999e12bb AL |
151 | static void milkymist_hpdmc_class_init(ObjectClass *klass, void *data) |
152 | { | |
39bffca2 | 153 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 154 | |
0f2eabce | 155 | dc->realize = milkymist_hpdmc_realize; |
39bffca2 AL |
156 | dc->reset = milkymist_hpdmc_reset; |
157 | dc->vmsd = &vmstate_milkymist_hpdmc; | |
999e12bb AL |
158 | } |
159 | ||
8c43a6f0 | 160 | static const TypeInfo milkymist_hpdmc_info = { |
829617a9 | 161 | .name = TYPE_MILKYMIST_HPDMC, |
39bffca2 AL |
162 | .parent = TYPE_SYS_BUS_DEVICE, |
163 | .instance_size = sizeof(MilkymistHpdmcState), | |
164 | .class_init = milkymist_hpdmc_class_init, | |
e4dc6d2c MW |
165 | }; |
166 | ||
83f7d43a | 167 | static void milkymist_hpdmc_register_types(void) |
e4dc6d2c | 168 | { |
39bffca2 | 169 | type_register_static(&milkymist_hpdmc_info); |
e4dc6d2c MW |
170 | } |
171 | ||
83f7d43a | 172 | type_init(milkymist_hpdmc_register_types) |