[qemu.git] / hw / ppc / ppc440_pcix.c

/*
 * Emulation of the ibm,plb-pcix PCI controller
 * This is found in some 440 SoCs e.g. the 460EX.
 *
 * Copyright (c) 2016-2018 BALATON Zoltan
 *
 * Derived from ppc4xx_pci.c and pci-host/ppce500.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc4xx.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "exec/address-spaces.h"
#include "trace.h"
#include "qom/object.h"

struct PLBOutMap {
    uint64_t la;
    uint64_t pcia;
    uint32_t sa;
    MemoryRegion mr;
};

struct PLBInMap {
    uint64_t sa;
    uint64_t la;
    MemoryRegion mr;
};

#define TYPE_PPC440_PCIX_HOST_BRIDGE "ppc440-pcix-host"
typedef struct PPC440PCIXState PPC440PCIXState;
DECLARE_INSTANCE_CHECKER(PPC440PCIXState, PPC440_PCIX_HOST_BRIDGE,
                         TYPE_PPC440_PCIX_HOST_BRIDGE)

#define PPC440_PCIX_NR_POMS 3
#define PPC440_PCIX_NR_PIMS 3

struct PPC440PCIXState {
    PCIHostState parent_obj;

    PCIDevice *dev;
    struct PLBOutMap pom[PPC440_PCIX_NR_POMS];
    struct PLBInMap pim[PPC440_PCIX_NR_PIMS];
    uint32_t sts;
    qemu_irq irq;
    AddressSpace bm_as;
    MemoryRegion bm;

    MemoryRegion container;
    MemoryRegion iomem;
    MemoryRegion busmem;
};

#define PPC440_REG_BASE     0x80000
#define PPC440_REG_SIZE     0xff

#define PCIC0_CFGADDR       0x0
#define PCIC0_CFGDATA       0x4

#define PCIX0_POM0LAL       0x68
#define PCIX0_POM0LAH       0x6c
#define PCIX0_POM0SA        0x70
#define PCIX0_POM0PCIAL     0x74
#define PCIX0_POM0PCIAH     0x78
#define PCIX0_POM1LAL       0x7c
#define PCIX0_POM1LAH       0x80
#define PCIX0_POM1SA        0x84
#define PCIX0_POM1PCIAL     0x88
#define PCIX0_POM1PCIAH     0x8c
#define PCIX0_POM2SA        0x90

#define PCIX0_PIM0SAL       0x98
#define PCIX0_PIM0LAL       0x9c
#define PCIX0_PIM0LAH       0xa0
#define PCIX0_PIM1SA        0xa4
#define PCIX0_PIM1LAL       0xa8
#define PCIX0_PIM1LAH       0xac
#define PCIX0_PIM2SAL       0xb0
#define PCIX0_PIM2LAL       0xb4
#define PCIX0_PIM2LAH       0xb8
#define PCIX0_PIM0SAH       0xf8
#define PCIX0_PIM2SAH       0xfc

#define PCIX0_STS           0xe0

#define PCI_ALL_SIZE        (PPC440_REG_BASE + PPC440_REG_SIZE)

static void ppc440_pcix_clear_region(MemoryRegion *parent,
                                     MemoryRegion *mem)
{
    if (memory_region_is_mapped(mem)) {
        memory_region_del_subregion(parent, mem);
        object_unparent(OBJECT(mem));
    }
}

/* DMA mapping */
static void ppc440_pcix_update_pim(PPC440PCIXState *s, int idx)
{
    MemoryRegion *mem = &s->pim[idx].mr;
    char *name;
    uint64_t size;

    /* Before we modify anything, unmap and destroy the region */
    ppc440_pcix_clear_region(&s->bm, mem);

    if (!(s->pim[idx].sa & 1)) {
        /* Not enabled, nothing to do */
        return;
    }

    name = g_strdup_printf("PCI Inbound Window %d", idx);
    size = ~(s->pim[idx].sa & ~7ULL) + 1;
    memory_region_init_alias(mem, OBJECT(s), name, get_system_memory(),
                             s->pim[idx].la, size);
    memory_region_add_subregion_overlap(&s->bm, 0, mem, -1);
    g_free(name);

    trace_ppc440_pcix_update_pim(idx, size, s->pim[idx].la);
}

/* BAR mapping */
static void ppc440_pcix_update_pom(PPC440PCIXState *s, int idx)
{
    MemoryRegion *mem = &s->pom[idx].mr;
    MemoryRegion *address_space_mem = get_system_memory();
    char *name;
    uint32_t size;

    /* Before we modify anything, unmap and destroy the region */
    ppc440_pcix_clear_region(address_space_mem, mem);

    if (!(s->pom[idx].sa & 1)) {
        /* Not enabled, nothing to do */
        return;
    }

    name = g_strdup_printf("PCI Outbound Window %d", idx);
    size = ~(s->pom[idx].sa & 0xfffffffe) + 1;
    if (!size) {
        size = 0xffffffff;
    }
    memory_region_init_alias(mem, OBJECT(s), name, &s->busmem,
                             s->pom[idx].pcia, size);
    memory_region_add_subregion(address_space_mem, s->pom[idx].la, mem);
    g_free(name);

    trace_ppc440_pcix_update_pom(idx, size, s->pom[idx].la, s->pom[idx].pcia);
}

static void ppc440_pcix_reg_write4(void *opaque, hwaddr addr,
                                   uint64_t val, unsigned size)
{
    struct PPC440PCIXState *s = opaque;

    trace_ppc440_pcix_reg_read(addr, val);
    switch (addr) {
    case PCI_VENDOR_ID ... PCI_MAX_LAT:
        stl_le_p(s->dev->config + addr, val);
        break;

    case PCIX0_POM0LAL:
        s->pom[0].la &= 0xffffffff00000000ULL;
        s->pom[0].la |= val;
        ppc440_pcix_update_pom(s, 0);
        break;
    case PCIX0_POM0LAH:
        s->pom[0].la &= 0xffffffffULL;
        s->pom[0].la |= val << 32;
        ppc440_pcix_update_pom(s, 0);
        break;
    case PCIX0_POM0SA:
        s->pom[0].sa = val;
        ppc440_pcix_update_pom(s, 0);
        break;
    case PCIX0_POM0PCIAL:
        s->pom[0].pcia &= 0xffffffff00000000ULL;
        s->pom[0].pcia |= val;
        ppc440_pcix_update_pom(s, 0);
        break;
    case PCIX0_POM0PCIAH:
        s->pom[0].pcia &= 0xffffffffULL;
        s->pom[0].pcia |= val << 32;
        ppc440_pcix_update_pom(s, 0);
        break;
    case PCIX0_POM1LAL:
        s->pom[1].la &= 0xffffffff00000000ULL;
        s->pom[1].la |= val;
        ppc440_pcix_update_pom(s, 1);
        break;
    case PCIX0_POM1LAH:
        s->pom[1].la &= 0xffffffffULL;
        s->pom[1].la |= val << 32;
        ppc440_pcix_update_pom(s, 1);
        break;
    case PCIX0_POM1SA:
        s->pom[1].sa = val;
        ppc440_pcix_update_pom(s, 1);
        break;
    case PCIX0_POM1PCIAL:
        s->pom[1].pcia &= 0xffffffff00000000ULL;
        s->pom[1].pcia |= val;
        ppc440_pcix_update_pom(s, 1);
        break;
    case PCIX0_POM1PCIAH:
        s->pom[1].pcia &= 0xffffffffULL;
        s->pom[1].pcia |= val << 32;
        ppc440_pcix_update_pom(s, 1);
        break;
    case PCIX0_POM2SA:
        s->pom[2].sa = val;
        break;

    case PCIX0_PIM0SAL:
        s->pim[0].sa &= 0xffffffff00000000ULL;
        s->pim[0].sa |= val;
        ppc440_pcix_update_pim(s, 0);
        break;
    case PCIX0_PIM0LAL:
        s->pim[0].la &= 0xffffffff00000000ULL;
        s->pim[0].la |= val;
        ppc440_pcix_update_pim(s, 0);
        break;
    case PCIX0_PIM0LAH:
        s->pim[0].la &= 0xffffffffULL;
        s->pim[0].la |= val << 32;
        ppc440_pcix_update_pim(s, 0);
        break;
    case PCIX0_PIM1SA:
        s->pim[1].sa = val;
        ppc440_pcix_update_pim(s, 1);
        break;
    case PCIX0_PIM1LAL:
        s->pim[1].la &= 0xffffffff00000000ULL;
        s->pim[1].la |= val;
        ppc440_pcix_update_pim(s, 1);
        break;
    case PCIX0_PIM1LAH:
        s->pim[1].la &= 0xffffffffULL;
        s->pim[1].la |= val << 32;
        ppc440_pcix_update_pim(s, 1);
        break;
    case PCIX0_PIM2SAL:
        s->pim[2].sa &= 0xffffffff00000000ULL;
        s->pim[2].sa |= val;
        ppc440_pcix_update_pim(s, 2);
        break;
    case PCIX0_PIM2LAL:
        s->pim[2].la &= 0xffffffff00000000ULL;
        s->pim[2].la |= val;
        ppc440_pcix_update_pim(s, 2);
        break;
    case PCIX0_PIM2LAH:
        s->pim[2].la &= 0xffffffffULL;
        s->pim[2].la |= val << 32;
        ppc440_pcix_update_pim(s, 2);
        break;

    case PCIX0_STS:
        s->sts = val;
        break;

    case PCIX0_PIM0SAH:
        s->pim[0].sa &= 0xffffffffULL;
        s->pim[0].sa |= val << 32;
        ppc440_pcix_update_pim(s, 0);
        break;
    case PCIX0_PIM2SAH:
        s->pim[2].sa &= 0xffffffffULL;
        s->pim[2].sa |= val << 32;
        ppc440_pcix_update_pim(s, 2);
        break;

    default:
        qemu_log_mask(LOG_UNIMP,
                      "%s: unhandled PCI internal register 0x%"HWADDR_PRIx"\n",
                      __func__, addr);
        break;
    }
}

static uint64_t ppc440_pcix_reg_read4(void *opaque, hwaddr addr,
                                     unsigned size)
{
    struct PPC440PCIXState *s = opaque;
    uint32_t val;

    switch (addr) {
    case PCI_VENDOR_ID ... PCI_MAX_LAT:
        val = ldl_le_p(s->dev->config + addr);
        break;

    case PCIX0_POM0LAL:
        val = s->pom[0].la;
        break;
    case PCIX0_POM0LAH:
        val = s->pom[0].la >> 32;
        break;
    case PCIX0_POM0SA:
        val = s->pom[0].sa;
        break;
    case PCIX0_POM0PCIAL:
        val = s->pom[0].pcia;
        break;
    case PCIX0_POM0PCIAH:
        val = s->pom[0].pcia >> 32;
        break;
    case PCIX0_POM1LAL:
        val = s->pom[1].la;
        break;
    case PCIX0_POM1LAH:
        val = s->pom[1].la >> 32;
        break;
    case PCIX0_POM1SA:
        val = s->pom[1].sa;
        break;
    case PCIX0_POM1PCIAL:
        val = s->pom[1].pcia;
        break;
    case PCIX0_POM1PCIAH:
        val = s->pom[1].pcia >> 32;
        break;
    case PCIX0_POM2SA:
        val = s->pom[2].sa;
        break;

    case PCIX0_PIM0SAL:
        val = s->pim[0].sa;
        break;
    case PCIX0_PIM0LAL:
        val = s->pim[0].la;
        break;
    case PCIX0_PIM0LAH:
        val = s->pim[0].la >> 32;
        break;
    case PCIX0_PIM1SA:
        val = s->pim[1].sa;
        break;
    case PCIX0_PIM1LAL:
        val = s->pim[1].la;
        break;
    case PCIX0_PIM1LAH:
        val = s->pim[1].la >> 32;
        break;
    case PCIX0_PIM2SAL:
        val = s->pim[2].sa;
        break;
    case PCIX0_PIM2LAL:
        val = s->pim[2].la;
        break;
    case PCIX0_PIM2LAH:
        val = s->pim[2].la >> 32;
        break;

    case PCIX0_STS:
        val = s->sts;
        break;

    case PCIX0_PIM0SAH:
        val = s->pim[0].sa  >> 32;
        break;
    case PCIX0_PIM2SAH:
        val = s->pim[2].sa  >> 32;
        break;

    default:
        qemu_log_mask(LOG_UNIMP,
                      "%s: invalid PCI internal register 0x%" HWADDR_PRIx "\n",
                      __func__, addr);
        val = 0;
    }

    trace_ppc440_pcix_reg_read(addr, val);
    return val;
}

static const MemoryRegionOps pci_reg_ops = {
    .read = ppc440_pcix_reg_read4,
    .write = ppc440_pcix_reg_write4,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void ppc440_pcix_reset(DeviceState *dev)
{
    struct PPC440PCIXState *s = PPC440_PCIX_HOST_BRIDGE(dev);
    int i;

    for (i = 0; i < PPC440_PCIX_NR_POMS; i++) {
        ppc440_pcix_clear_region(get_system_memory(), &s->pom[i].mr);
    }
    for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) {
        ppc440_pcix_clear_region(&s->bm, &s->pim[i].mr);
    }
    memset(s->pom, 0, sizeof(s->pom));
    memset(s->pim, 0, sizeof(s->pim));
    for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) {
        s->pim[i].sa = 0xffffffff00000000ULL;
    }
    s->sts = 0;
}

/* All pins from each slot are tied to a single board IRQ.
 * This may need further refactoring for other boards. */
static int ppc440_pcix_map_irq(PCIDevice *pci_dev, int irq_num)
{
    trace_ppc440_pcix_map_irq(pci_dev->devfn, irq_num, 0);
    return 0;
}

static void ppc440_pcix_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pci_irq = opaque;

    trace_ppc440_pcix_set_irq(irq_num);
    if (irq_num < 0) {
        error_report("%s: PCI irq %d", __func__, irq_num);
        return;
    }
    qemu_set_irq(*pci_irq, level);
}

static AddressSpace *ppc440_pcix_set_iommu(PCIBus *b, void *opaque, int devfn)
{
    PPC440PCIXState *s = opaque;

    return &s->bm_as;
}

/* The default pci_host_data_{read,write} functions in pci/pci_host.c
 * deny access to registers without bit 31 set but our clients want
 * this to work so we have to override these here */
static void pci_host_data_write(void *opaque, hwaddr addr,
                                uint64_t val, unsigned len)
{
    PCIHostState *s = opaque;
    pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
}

static uint64_t pci_host_data_read(void *opaque,
                                   hwaddr addr, unsigned len)
{
    PCIHostState *s = opaque;
    uint32_t val;
    val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
    return val;
}

const MemoryRegionOps ppc440_pcix_host_data_ops = {
    .read = pci_host_data_read,
    .write = pci_host_data_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
};

static void ppc440_pcix_realize(DeviceState *dev, Error **errp)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    PPC440PCIXState *s;
    PCIHostState *h;

    h = PCI_HOST_BRIDGE(dev);
    s = PPC440_PCIX_HOST_BRIDGE(dev);

    sysbus_init_irq(sbd, &s->irq);
    memory_region_init(&s->busmem, OBJECT(dev), "pci bus memory", UINT64_MAX);
    h->bus = pci_register_root_bus(dev, NULL, ppc440_pcix_set_irq,
                         ppc440_pcix_map_irq, &s->irq, &s->busmem,
                         get_system_io(), PCI_DEVFN(0, 0), 1, TYPE_PCI_BUS);

    s->dev = pci_create_simple(h->bus, PCI_DEVFN(0, 0), "ppc4xx-host-bridge");

    memory_region_init(&s->bm, OBJECT(s), "bm-ppc440-pcix", UINT64_MAX);
    memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
    address_space_init(&s->bm_as, &s->bm, "pci-bm");
    pci_setup_iommu(h->bus, ppc440_pcix_set_iommu, s);

    memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
    memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops,
                          h, "pci-conf-idx", 4);
    memory_region_init_io(&h->data_mem, OBJECT(s), &ppc440_pcix_host_data_ops,
                          h, "pci-conf-data", 4);
    memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
                          "pci.reg", PPC440_REG_SIZE);
    memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
    memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
    memory_region_add_subregion(&s->container, PPC440_REG_BASE, &s->iomem);
    sysbus_init_mmio(sbd, &s->container);
}

static void ppc440_pcix_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = ppc440_pcix_realize;
    dc->reset = ppc440_pcix_reset;
}

static const TypeInfo ppc440_pcix_info = {
    .name          = TYPE_PPC440_PCIX_HOST_BRIDGE,
    .parent        = TYPE_PCI_HOST_BRIDGE,
    .instance_size = sizeof(PPC440PCIXState),
    .class_init    = ppc440_pcix_class_init,
};

static void ppc440_pcix_register_types(void)
{
    type_register_static(&ppc440_pcix_info);
}

type_init(ppc440_pcix_register_types)
Commit	Line	Data
7ccc89b5 BZ	1	/*
	2	* Emulation of the ibm,plb-pcix PCI controller
	3	* This is found in some 440 SoCs e.g. the 460EX.
	4	*
	5	* Copyright (c) 2016-2018 BALATON Zoltan
	6	*
	7	* Derived from ppc4xx_pci.c and pci-host/ppce500.c
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License, version 2, as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#include "qemu/osdep.h"
	23	#include "qemu/error-report.h"
21a5a442	24	#include "qemu/log.h"
0b8fa32f	25	#include "qemu/module.h"
64552b6b	26	#include "hw/irq.h"
7ccc89b5 BZ	27	#include "hw/ppc/ppc.h"
	28	#include "hw/ppc/ppc4xx.h"
	29	#include "hw/pci/pci.h"
	30	#include "hw/pci/pci_host.h"
	31	#include "exec/address-spaces.h"
	32	#include "trace.h"
db1015e9	33	#include "qom/object.h"
7ccc89b5 BZ	34
	35	struct PLBOutMap {
	36	uint64_t la;
	37	uint64_t pcia;
	38	uint32_t sa;
	39	MemoryRegion mr;
	40	};
	41
	42	struct PLBInMap {
	43	uint64_t sa;
	44	uint64_t la;
	45	MemoryRegion mr;
	46	};
	47
	48	#define TYPE_PPC440_PCIX_HOST_BRIDGE "ppc440-pcix-host"
db1015e9	49	typedef struct PPC440PCIXState PPC440PCIXState;
8110fa1d EH	50	DECLARE_INSTANCE_CHECKER(PPC440PCIXState, PPC440_PCIX_HOST_BRIDGE,
8110fa1d EH	51	TYPE_PPC440_PCIX_HOST_BRIDGE)
7ccc89b5 BZ	52
	53	#define PPC440_PCIX_NR_POMS 3
	54	#define PPC440_PCIX_NR_PIMS 3
	55
db1015e9	56	struct PPC440PCIXState {
7ccc89b5 BZ	57	PCIHostState parent_obj;
	58
	59	PCIDevice *dev;
	60	struct PLBOutMap pom[PPC440_PCIX_NR_POMS];
	61	struct PLBInMap pim[PPC440_PCIX_NR_PIMS];
	62	uint32_t sts;
6484ab3d	63	qemu_irq irq;
7ccc89b5 BZ	64	AddressSpace bm_as;
	65	MemoryRegion bm;
	66
	67	MemoryRegion container;
	68	MemoryRegion iomem;
	69	MemoryRegion busmem;
db1015e9	70	};
7ccc89b5 BZ	71
	72	#define PPC440_REG_BASE 0x80000
	73	#define PPC440_REG_SIZE 0xff
	74
	75	#define PCIC0_CFGADDR 0x0
	76	#define PCIC0_CFGDATA 0x4
	77
	78	#define PCIX0_POM0LAL 0x68
	79	#define PCIX0_POM0LAH 0x6c
	80	#define PCIX0_POM0SA 0x70
	81	#define PCIX0_POM0PCIAL 0x74
	82	#define PCIX0_POM0PCIAH 0x78
	83	#define PCIX0_POM1LAL 0x7c
	84	#define PCIX0_POM1LAH 0x80
	85	#define PCIX0_POM1SA 0x84
	86	#define PCIX0_POM1PCIAL 0x88
	87	#define PCIX0_POM1PCIAH 0x8c
	88	#define PCIX0_POM2SA 0x90
	89
	90	#define PCIX0_PIM0SAL 0x98
	91	#define PCIX0_PIM0LAL 0x9c
	92	#define PCIX0_PIM0LAH 0xa0
	93	#define PCIX0_PIM1SA 0xa4
	94	#define PCIX0_PIM1LAL 0xa8
	95	#define PCIX0_PIM1LAH 0xac
	96	#define PCIX0_PIM2SAL 0xb0
	97	#define PCIX0_PIM2LAL 0xb4
	98	#define PCIX0_PIM2LAH 0xb8
	99	#define PCIX0_PIM0SAH 0xf8
	100	#define PCIX0_PIM2SAH 0xfc
	101
	102	#define PCIX0_STS 0xe0
	103
	104	#define PCI_ALL_SIZE (PPC440_REG_BASE + PPC440_REG_SIZE)
	105
	106	static void ppc440_pcix_clear_region(MemoryRegion *parent,
	107	MemoryRegion *mem)
	108	{
	109	if (memory_region_is_mapped(mem)) {
	110	memory_region_del_subregion(parent, mem);
	111	object_unparent(OBJECT(mem));
	112	}
	113	}
	114
	115	/* DMA mapping */
	116	static void ppc440_pcix_update_pim(PPC440PCIXState *s, int idx)
	117	{
	118	MemoryRegion *mem = &s->pim[idx].mr;
	119	char *name;
	120	uint64_t size;
	121
	122	/* Before we modify anything, unmap and destroy the region */
	123	ppc440_pcix_clear_region(&s->bm, mem);
	124
	125	if (!(s->pim[idx].sa & 1)) {
	126	/* Not enabled, nothing to do */
	127	return;
	128	}
	129
	130	name = g_strdup_printf("PCI Inbound Window %d", idx);
	131	size = ~(s->pim[idx].sa & ~7ULL) + 1;
	132	memory_region_init_alias(mem, OBJECT(s), name, get_system_memory(),
	133	s->pim[idx].la, size);
	134	memory_region_add_subregion_overlap(&s->bm, 0, mem, -1);
135	g_free(name);
136
137	trace_ppc440_pcix_update_pim(idx, size, s->pim[idx].la);
138	}
139
140	/* BAR mapping */
141	static void ppc440_pcix_update_pom(PPC440PCIXState *s, int idx)
142	{
143	MemoryRegion *mem = &s->pom[idx].mr;
144	MemoryRegion *address_space_mem = get_system_memory();
145	char *name;
146	uint32_t size;
147
148	/* Before we modify anything, unmap and destroy the region */
149	ppc440_pcix_clear_region(address_space_mem, mem);
150
151	if (!(s->pom[idx].sa & 1)) {
152	/* Not enabled, nothing to do */
153	return;
154	}
155
156	name = g_strdup_printf("PCI Outbound Window %d", idx);
157	size = ~(s->pom[idx].sa & 0xfffffffe) + 1;
158	if (!size) {
159	size = 0xffffffff;
160	}
161	memory_region_init_alias(mem, OBJECT(s), name, &s->busmem,
162	s->pom[idx].pcia, size);
163	memory_region_add_subregion(address_space_mem, s->pom[idx].la, mem);
164	g_free(name);
165
166	trace_ppc440_pcix_update_pom(idx, size, s->pom[idx].la, s->pom[idx].pcia);
167	}
168
169	static void ppc440_pcix_reg_write4(void *opaque, hwaddr addr,
170	uint64_t val, unsigned size)
171	{
172	struct PPC440PCIXState *s = opaque;
173
174	trace_ppc440_pcix_reg_read(addr, val);
175	switch (addr) {
176	case PCI_VENDOR_ID ... PCI_MAX_LAT:
177	stl_le_p(s->dev->config + addr, val);
178	break;
179
180	case PCIX0_POM0LAL:
181	s->pom[0].la &= 0xffffffff00000000ULL;
182	s->pom[0].la \|= val;
183	ppc440_pcix_update_pom(s, 0);
184	break;
185	case PCIX0_POM0LAH:
186	s->pom[0].la &= 0xffffffffULL;
187	s->pom[0].la \|= val << 32;
188	ppc440_pcix_update_pom(s, 0);
189	break;
190	case PCIX0_POM0SA:
191	s->pom[0].sa = val;
192	ppc440_pcix_update_pom(s, 0);
193	break;
194	case PCIX0_POM0PCIAL:
195	s->pom[0].pcia &= 0xffffffff00000000ULL;
196	s->pom[0].pcia \|= val;
197	ppc440_pcix_update_pom(s, 0);
198	break;
199	case PCIX0_POM0PCIAH:
200	s->pom[0].pcia &= 0xffffffffULL;
201	s->pom[0].pcia \|= val << 32;
202	ppc440_pcix_update_pom(s, 0);
203	break;
204	case PCIX0_POM1LAL:
205	s->pom[1].la &= 0xffffffff00000000ULL;
206	s->pom[1].la \|= val;
207	ppc440_pcix_update_pom(s, 1);
208	break;
209	case PCIX0_POM1LAH:
210	s->pom[1].la &= 0xffffffffULL;
211	s->pom[1].la \|= val << 32;
212	ppc440_pcix_update_pom(s, 1);
213	break;
214	case PCIX0_POM1SA:
215	s->pom[1].sa = val;
216	ppc440_pcix_update_pom(s, 1);
217	break;
218	case PCIX0_POM1PCIAL:
219	s->pom[1].pcia &= 0xffffffff00000000ULL;
220	s->pom[1].pcia \|= val;
221	ppc440_pcix_update_pom(s, 1);
222	break;
223	case PCIX0_POM1PCIAH:
224	s->pom[1].pcia &= 0xffffffffULL;
225	s->pom[1].pcia \|= val << 32;
226	ppc440_pcix_update_pom(s, 1);
227	break;
228	case PCIX0_POM2SA:
229	s->pom[2].sa = val;
230	break;
231
232	case PCIX0_PIM0SAL:
233	s->pim[0].sa &= 0xffffffff00000000ULL;
234	s->pim[0].sa \|= val;
235	ppc440_pcix_update_pim(s, 0);
236	break;
237	case PCIX0_PIM0LAL:
238	s->pim[0].la &= 0xffffffff00000000ULL;
239	s->pim[0].la \|= val;
240	ppc440_pcix_update_pim(s, 0);
241	break;
242	case PCIX0_PIM0LAH:
243	s->pim[0].la &= 0xffffffffULL;
244	s->pim[0].la \|= val << 32;
245	ppc440_pcix_update_pim(s, 0);
246	break;
247	case PCIX0_PIM1SA:
248	s->pim[1].sa = val;
249	ppc440_pcix_update_pim(s, 1);
250	break;
251	case PCIX0_PIM1LAL:
252	s->pim[1].la &= 0xffffffff00000000ULL;
253	s->pim[1].la \|= val;
254	ppc440_pcix_update_pim(s, 1);
255	break;
256	case PCIX0_PIM1LAH:
257	s->pim[1].la &= 0xffffffffULL;
258	s->pim[1].la \|= val << 32;
259	ppc440_pcix_update_pim(s, 1);
260	break;
261	case PCIX0_PIM2SAL:
262	s->pim[2].sa &= 0xffffffff00000000ULL;
68143189	263	s->pim[2].sa \|= val;
7ccc89b5 BZ	264	ppc440_pcix_update_pim(s, 2);
	265	break;
	266	case PCIX0_PIM2LAL:
	267	s->pim[2].la &= 0xffffffff00000000ULL;
	268	s->pim[2].la \|= val;
	269	ppc440_pcix_update_pim(s, 2);
	270	break;
	271	case PCIX0_PIM2LAH:
	272	s->pim[2].la &= 0xffffffffULL;
	273	s->pim[2].la \|= val << 32;
	274	ppc440_pcix_update_pim(s, 2);
	275	break;
	276
	277	case PCIX0_STS:
	278	s->sts = val;
	279	break;
	280
	281	case PCIX0_PIM0SAH:
	282	s->pim[0].sa &= 0xffffffffULL;
	283	s->pim[0].sa \|= val << 32;
	284	ppc440_pcix_update_pim(s, 0);
	285	break;
	286	case PCIX0_PIM2SAH:
	287	s->pim[2].sa &= 0xffffffffULL;
	288	s->pim[2].sa \|= val << 32;
	289	ppc440_pcix_update_pim(s, 2);
	290	break;
	291
	292	default:
21a5a442 BZ	293	qemu_log_mask(LOG_UNIMP,
	294	"%s: unhandled PCI internal register 0x%"HWADDR_PRIx"\n",
	295	__func__, addr);
7ccc89b5 BZ	296	break;
	297	}
	298	}
	299
	300	static uint64_t ppc440_pcix_reg_read4(void *opaque, hwaddr addr,
	301	unsigned size)
	302	{
	303	struct PPC440PCIXState *s = opaque;
	304	uint32_t val;
	305
	306	switch (addr) {
	307	case PCI_VENDOR_ID ... PCI_MAX_LAT:
	308	val = ldl_le_p(s->dev->config + addr);
	309	break;
	310
	311	case PCIX0_POM0LAL:
	312	val = s->pom[0].la;
	313	break;
	314	case PCIX0_POM0LAH:
	315	val = s->pom[0].la >> 32;
	316	break;
	317	case PCIX0_POM0SA:
	318	val = s->pom[0].sa;
	319	break;
	320	case PCIX0_POM0PCIAL:
	321	val = s->pom[0].pcia;
	322	break;
	323	case PCIX0_POM0PCIAH:
	324	val = s->pom[0].pcia >> 32;
	325	break;
	326	case PCIX0_POM1LAL:
	327	val = s->pom[1].la;
	328	break;
	329	case PCIX0_POM1LAH:
	330	val = s->pom[1].la >> 32;
	331	break;
	332	case PCIX0_POM1SA:
	333	val = s->pom[1].sa;
	334	break;
	335	case PCIX0_POM1PCIAL:
	336	val = s->pom[1].pcia;
	337	break;
	338	case PCIX0_POM1PCIAH:
	339	val = s->pom[1].pcia >> 32;
	340	break;
	341	case PCIX0_POM2SA:
	342	val = s->pom[2].sa;
	343	break;
	344
	345	case PCIX0_PIM0SAL:
	346	val = s->pim[0].sa;
	347	break;
	348	case PCIX0_PIM0LAL:
	349	val = s->pim[0].la;
	350	break;
	351	case PCIX0_PIM0LAH:
	352	val = s->pim[0].la >> 32;
	353	break;
	354	case PCIX0_PIM1SA:
	355	val = s->pim[1].sa;
	356	break;
	357	case PCIX0_PIM1LAL:
	358	val = s->pim[1].la;
	359	break;
360	case PCIX0_PIM1LAH:
361	val = s->pim[1].la >> 32;
362	break;
363	case PCIX0_PIM2SAL:
364	val = s->pim[2].sa;
365	break;
366	case PCIX0_PIM2LAL:
367	val = s->pim[2].la;
368	break;
369	case PCIX0_PIM2LAH:
370	val = s->pim[2].la >> 32;
371	break;
372
373	case PCIX0_STS:
374	val = s->sts;
375	break;
376
377	case PCIX0_PIM0SAH:
378	val = s->pim[0].sa >> 32;
379	break;
380	case PCIX0_PIM2SAH:
381	val = s->pim[2].sa >> 32;
382	break;
383
384	default:
21a5a442 BZ	385	qemu_log_mask(LOG_UNIMP,
	386	"%s: invalid PCI internal register 0x%" HWADDR_PRIx "\n",
	387	__func__, addr);
7ccc89b5 BZ	388	val = 0;
	389	}
	390
	391	trace_ppc440_pcix_reg_read(addr, val);
	392	return val;
	393	}
	394
	395	static const MemoryRegionOps pci_reg_ops = {
	396	.read = ppc440_pcix_reg_read4,
	397	.write = ppc440_pcix_reg_write4,
	398	.endianness = DEVICE_LITTLE_ENDIAN,
	399	};
	400
	401	static void ppc440_pcix_reset(DeviceState *dev)
	402	{
	403	struct PPC440PCIXState *s = PPC440_PCIX_HOST_BRIDGE(dev);
	404	int i;
	405
	406	for (i = 0; i < PPC440_PCIX_NR_POMS; i++) {
	407	ppc440_pcix_clear_region(get_system_memory(), &s->pom[i].mr);
	408	}
	409	for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) {
	410	ppc440_pcix_clear_region(&s->bm, &s->pim[i].mr);
	411	}
	412	memset(s->pom, 0, sizeof(s->pom));
	413	memset(s->pim, 0, sizeof(s->pim));
	414	for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) {
	415	s->pim[i].sa = 0xffffffff00000000ULL;
	416	}
	417	s->sts = 0;
	418	}
	419
	420	/* All pins from each slot are tied to a single board IRQ.
	421	* This may need further refactoring for other boards. */
	422	static int ppc440_pcix_map_irq(PCIDevice *pci_dev, int irq_num)
	423	{
6484ab3d BZ	424	trace_ppc440_pcix_map_irq(pci_dev->devfn, irq_num, 0);
6484ab3d BZ	425	return 0;
7ccc89b5 BZ	426	}
	427
	428	static void ppc440_pcix_set_irq(void *opaque, int irq_num, int level)
	429	{
6484ab3d	430	qemu_irq *pci_irq = opaque;
7ccc89b5 BZ	431
	432	trace_ppc440_pcix_set_irq(irq_num);
	433	if (irq_num < 0) {
	434	error_report("%s: PCI irq %d", __func__, irq_num);
	435	return;
	436	}
6484ab3d	437	qemu_set_irq(*pci_irq, level);
7ccc89b5 BZ	438	}
	439
	440	static AddressSpace ppc440_pcix_set_iommu(PCIBus b, void *opaque, int devfn)
	441	{
	442	PPC440PCIXState *s = opaque;
	443
	444	return &s->bm_as;
	445	}
	446
	447	/* The default pci_host_data_{read,write} functions in pci/pci_host.c
	448	* deny access to registers without bit 31 set but our clients want
	449	* this to work so we have to override these here */
	450	static void pci_host_data_write(void *opaque, hwaddr addr,
	451	uint64_t val, unsigned len)
	452	{
	453	PCIHostState *s = opaque;
	454	pci_data_write(s->bus, s->config_reg \| (addr & 3), val, len);
	455	}
	456
	457	static uint64_t pci_host_data_read(void *opaque,
	458	hwaddr addr, unsigned len)
	459	{
	460	PCIHostState *s = opaque;
	461	uint32_t val;
	462	val = pci_data_read(s->bus, s->config_reg \| (addr & 3), len);
	463	return val;
	464	}
	465
	466	const MemoryRegionOps ppc440_pcix_host_data_ops = {
	467	.read = pci_host_data_read,
	468	.write = pci_host_data_write,
	469	.endianness = DEVICE_LITTLE_ENDIAN,
	470	};
	471
7b0f4ec9	472	static void ppc440_pcix_realize(DeviceState dev, Error *errp)
7ccc89b5	473	{
7b0f4ec9	474	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
7ccc89b5 BZ	475	PPC440PCIXState *s;
7ccc89b5 BZ	476	PCIHostState *h;
7ccc89b5 BZ	477
	478	h = PCI_HOST_BRIDGE(dev);
	479	s = PPC440_PCIX_HOST_BRIDGE(dev);
	480
7b0f4ec9	481	sysbus_init_irq(sbd, &s->irq);
7ccc89b5	482	memory_region_init(&s->busmem, OBJECT(dev), "pci bus memory", UINT64_MAX);
7b0f4ec9	483	h->bus = pci_register_root_bus(dev, NULL, ppc440_pcix_set_irq,
6484ab3d BZ	484	ppc440_pcix_map_irq, &s->irq, &s->busmem,
6484ab3d BZ	485	get_system_io(), PCI_DEVFN(0, 0), 1, TYPE_PCI_BUS);
7ccc89b5 BZ	486
	487	s->dev = pci_create_simple(h->bus, PCI_DEVFN(0, 0), "ppc4xx-host-bridge");
	488
	489	memory_region_init(&s->bm, OBJECT(s), "bm-ppc440-pcix", UINT64_MAX);
	490	memory_region_add_subregion(&s->bm, 0x0, &s->busmem);
	491	address_space_init(&s->bm_as, &s->bm, "pci-bm");
	492	pci_setup_iommu(h->bus, ppc440_pcix_set_iommu, s);
	493
	494	memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
	495	memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops,
	496	h, "pci-conf-idx", 4);
	497	memory_region_init_io(&h->data_mem, OBJECT(s), &ppc440_pcix_host_data_ops,
	498	h, "pci-conf-data", 4);
	499	memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
	500	"pci.reg", PPC440_REG_SIZE);
	501	memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
	502	memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
	503	memory_region_add_subregion(&s->container, PPC440_REG_BASE, &s->iomem);
7b0f4ec9	504	sysbus_init_mmio(sbd, &s->container);
7ccc89b5 BZ	505	}
	506
	507	static void ppc440_pcix_class_init(ObjectClass klass, void data)
	508	{
7ccc89b5 BZ	509	DeviceClass *dc = DEVICE_CLASS(klass);
7ccc89b5 BZ	510
7b0f4ec9	511	dc->realize = ppc440_pcix_realize;
7ccc89b5 BZ	512	dc->reset = ppc440_pcix_reset;
	513	}
	514
	515	static const TypeInfo ppc440_pcix_info = {
	516	.name = TYPE_PPC440_PCIX_HOST_BRIDGE,
	517	.parent = TYPE_PCI_HOST_BRIDGE,
	518	.instance_size = sizeof(PPC440PCIXState),
	519	.class_init = ppc440_pcix_class_init,
	520	};
	521
	522	static void ppc440_pcix_register_types(void)
	523	{
	524	type_register_static(&ppc440_pcix_info);
	525	}
	526
	527	type_init(ppc440_pcix_register_types)