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Commit | Line | Data |
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9b8bfe21 | 1 | #include "qemu/osdep.h" |
c5d4dac8 GH |
2 | #include "hw/hw.h" |
3 | #include "hw/pci/pci.h" | |
4 | #include "ui/console.h" | |
5 | #include "vga_int.h" | |
6 | #include "hw/virtio/virtio-pci.h" | |
d0f0c865 | 7 | #include "qapi/error.h" |
c5d4dac8 GH |
8 | |
9 | /* | |
10 | * virtio-vga: This extends VirtioPCIProxy. | |
11 | */ | |
12 | #define TYPE_VIRTIO_VGA "virtio-vga" | |
13 | #define VIRTIO_VGA(obj) \ | |
14 | OBJECT_CHECK(VirtIOVGA, (obj), TYPE_VIRTIO_VGA) | |
15 | ||
16 | typedef struct VirtIOVGA { | |
17 | VirtIOPCIProxy parent_obj; | |
18 | VirtIOGPU vdev; | |
19 | VGACommonState vga; | |
20 | MemoryRegion vga_mrs[3]; | |
21 | } VirtIOVGA; | |
22 | ||
23 | static void virtio_vga_invalidate_display(void *opaque) | |
24 | { | |
25 | VirtIOVGA *vvga = opaque; | |
26 | ||
27 | if (vvga->vdev.enable) { | |
28 | virtio_gpu_ops.invalidate(&vvga->vdev); | |
29 | } else { | |
30 | vvga->vga.hw_ops->invalidate(&vvga->vga); | |
31 | } | |
32 | } | |
33 | ||
34 | static void virtio_vga_update_display(void *opaque) | |
35 | { | |
36 | VirtIOVGA *vvga = opaque; | |
37 | ||
38 | if (vvga->vdev.enable) { | |
39 | virtio_gpu_ops.gfx_update(&vvga->vdev); | |
40 | } else { | |
41 | vvga->vga.hw_ops->gfx_update(&vvga->vga); | |
42 | } | |
43 | } | |
44 | ||
45 | static void virtio_vga_text_update(void *opaque, console_ch_t *chardata) | |
46 | { | |
47 | VirtIOVGA *vvga = opaque; | |
48 | ||
49 | if (vvga->vdev.enable) { | |
50 | if (virtio_gpu_ops.text_update) { | |
51 | virtio_gpu_ops.text_update(&vvga->vdev, chardata); | |
52 | } | |
53 | } else { | |
54 | if (vvga->vga.hw_ops->text_update) { | |
55 | vvga->vga.hw_ops->text_update(&vvga->vga, chardata); | |
56 | } | |
57 | } | |
58 | } | |
59 | ||
60 | static int virtio_vga_ui_info(void *opaque, uint32_t idx, QemuUIInfo *info) | |
61 | { | |
62 | VirtIOVGA *vvga = opaque; | |
63 | ||
64 | if (virtio_gpu_ops.ui_info) { | |
65 | return virtio_gpu_ops.ui_info(&vvga->vdev, idx, info); | |
66 | } | |
67 | return -1; | |
68 | } | |
69 | ||
321c9adb GH |
70 | static void virtio_vga_gl_block(void *opaque, bool block) |
71 | { | |
72 | VirtIOVGA *vvga = opaque; | |
73 | ||
74 | if (virtio_gpu_ops.gl_block) { | |
75 | virtio_gpu_ops.gl_block(&vvga->vdev, block); | |
76 | } | |
77 | } | |
78 | ||
c5d4dac8 GH |
79 | static const GraphicHwOps virtio_vga_ops = { |
80 | .invalidate = virtio_vga_invalidate_display, | |
81 | .gfx_update = virtio_vga_update_display, | |
82 | .text_update = virtio_vga_text_update, | |
83 | .ui_info = virtio_vga_ui_info, | |
321c9adb | 84 | .gl_block = virtio_vga_gl_block, |
c5d4dac8 GH |
85 | }; |
86 | ||
0c244e50 GH |
87 | static const VMStateDescription vmstate_virtio_vga = { |
88 | .name = "virtio-vga", | |
89 | .version_id = 2, | |
90 | .minimum_version_id = 2, | |
91 | .fields = (VMStateField[]) { | |
92 | /* no pci stuff here, saving the virtio device will handle that */ | |
93 | VMSTATE_STRUCT(vga, VirtIOVGA, 0, vmstate_vga_common, VGACommonState), | |
94 | VMSTATE_END_OF_LIST() | |
95 | } | |
96 | }; | |
97 | ||
c5d4dac8 GH |
98 | /* VGA device wrapper around PCI device around virtio GPU */ |
99 | static void virtio_vga_realize(VirtIOPCIProxy *vpci_dev, Error **errp) | |
100 | { | |
101 | VirtIOVGA *vvga = VIRTIO_VGA(vpci_dev); | |
102 | VirtIOGPU *g = &vvga->vdev; | |
103 | VGACommonState *vga = &vvga->vga; | |
d0f0c865 | 104 | Error *err = NULL; |
c5d4dac8 | 105 | uint32_t offset; |
e1888295 | 106 | int i; |
c5d4dac8 GH |
107 | |
108 | /* init vga compat bits */ | |
109 | vga->vram_size_mb = 8; | |
110 | vga_common_init(vga, OBJECT(vpci_dev), false); | |
111 | vga_init(vga, OBJECT(vpci_dev), pci_address_space(&vpci_dev->pci_dev), | |
112 | pci_address_space_io(&vpci_dev->pci_dev), true); | |
113 | pci_register_bar(&vpci_dev->pci_dev, 0, | |
114 | PCI_BASE_ADDRESS_MEM_PREFETCH, &vga->vram); | |
115 | ||
116 | /* | |
117 | * Configure virtio bar and regions | |
118 | * | |
119 | * We use bar #2 for the mmio regions, to be compatible with stdvga. | |
120 | * virtio regions are moved to the end of bar #2, to make room for | |
121 | * the stdvga mmio registers at the start of bar #2. | |
122 | */ | |
7a25126d CF |
123 | vpci_dev->modern_mem_bar_idx = 2; |
124 | vpci_dev->msix_bar_idx = 4; | |
c2843e93 GH |
125 | |
126 | if (!(vpci_dev->flags & VIRTIO_PCI_FLAG_PAGE_PER_VQ)) { | |
127 | /* | |
128 | * with page-per-vq=off there is no padding space we can use | |
129 | * for the stdvga registers. Make the common and isr regions | |
130 | * smaller then. | |
131 | */ | |
132 | vpci_dev->common.size /= 2; | |
133 | vpci_dev->isr.size /= 2; | |
134 | } | |
135 | ||
c5d4dac8 GH |
136 | offset = memory_region_size(&vpci_dev->modern_bar); |
137 | offset -= vpci_dev->notify.size; | |
138 | vpci_dev->notify.offset = offset; | |
139 | offset -= vpci_dev->device.size; | |
140 | vpci_dev->device.offset = offset; | |
141 | offset -= vpci_dev->isr.size; | |
142 | vpci_dev->isr.offset = offset; | |
143 | offset -= vpci_dev->common.size; | |
144 | vpci_dev->common.offset = offset; | |
145 | ||
146 | /* init virtio bits */ | |
147 | qdev_set_parent_bus(DEVICE(g), BUS(&vpci_dev->bus)); | |
9a4c0e22 | 148 | virtio_pci_force_virtio_1(vpci_dev); |
d0f0c865 MAL |
149 | object_property_set_bool(OBJECT(g), true, "realized", &err); |
150 | if (err) { | |
151 | error_propagate(errp, err); | |
152 | return; | |
153 | } | |
c5d4dac8 GH |
154 | |
155 | /* add stdvga mmio regions */ | |
156 | pci_std_vga_mmio_region_init(vga, &vpci_dev->modern_bar, | |
157 | vvga->vga_mrs, true); | |
158 | ||
159 | vga->con = g->scanout[0].con; | |
160 | graphic_console_set_hwops(vga->con, &virtio_vga_ops, vvga); | |
e1888295 GH |
161 | |
162 | for (i = 0; i < g->conf.max_outputs; i++) { | |
163 | object_property_set_link(OBJECT(g->scanout[i].con), | |
164 | OBJECT(vpci_dev), | |
165 | "device", errp); | |
166 | } | |
c5d4dac8 GH |
167 | } |
168 | ||
169 | static void virtio_vga_reset(DeviceState *dev) | |
170 | { | |
171 | VirtIOVGA *vvga = VIRTIO_VGA(dev); | |
172 | vvga->vdev.enable = 0; | |
173 | ||
174 | vga_dirty_log_start(&vvga->vga); | |
175 | } | |
176 | ||
177 | static Property virtio_vga_properties[] = { | |
c5d4dac8 GH |
178 | DEFINE_VIRTIO_GPU_PCI_PROPERTIES(VirtIOPCIProxy), |
179 | DEFINE_PROP_END_OF_LIST(), | |
180 | }; | |
181 | ||
182 | static void virtio_vga_class_init(ObjectClass *klass, void *data) | |
183 | { | |
184 | DeviceClass *dc = DEVICE_CLASS(klass); | |
185 | VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass); | |
186 | PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); | |
187 | ||
188 | set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); | |
189 | dc->props = virtio_vga_properties; | |
190 | dc->reset = virtio_vga_reset; | |
0c244e50 | 191 | dc->vmsd = &vmstate_virtio_vga; |
c5d4dac8 GH |
192 | dc->hotpluggable = false; |
193 | ||
194 | k->realize = virtio_vga_realize; | |
195 | pcidev_k->romfile = "vgabios-virtio.bin"; | |
196 | pcidev_k->class_id = PCI_CLASS_DISPLAY_VGA; | |
197 | } | |
198 | ||
199 | static void virtio_vga_inst_initfn(Object *obj) | |
200 | { | |
201 | VirtIOVGA *dev = VIRTIO_VGA(obj); | |
b3409a31 GH |
202 | |
203 | virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev), | |
204 | TYPE_VIRTIO_GPU); | |
c5d4dac8 GH |
205 | } |
206 | ||
207 | static TypeInfo virtio_vga_info = { | |
208 | .name = TYPE_VIRTIO_VGA, | |
209 | .parent = TYPE_VIRTIO_PCI, | |
210 | .instance_size = sizeof(struct VirtIOVGA), | |
211 | .instance_init = virtio_vga_inst_initfn, | |
212 | .class_init = virtio_vga_class_init, | |
213 | }; | |
214 | ||
215 | static void virtio_vga_register_types(void) | |
216 | { | |
217 | type_register_static(&virtio_vga_info); | |
218 | } | |
219 | ||
220 | type_init(virtio_vga_register_types) |