[qemu.git] / hw / ssi / omap_spi.c

/*
 * TI OMAP processor's Multichannel SPI emulation.
 *
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Original code for OMAP2 by Andrzej Zaborowski <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) any later version of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/hw.h"
#include "hw/arm/omap.h"

/* Multichannel SPI */
struct omap_mcspi_s {
    MemoryRegion iomem;
    qemu_irq irq;
    int chnum;

    uint32_t sysconfig;
    uint32_t systest;
    uint32_t irqst;
    uint32_t irqen;
    uint32_t wken;
    uint32_t control;

    struct omap_mcspi_ch_s {
        qemu_irq txdrq;
        qemu_irq rxdrq;
        uint32_t (*txrx)(void *opaque, uint32_t, int);
        void *opaque;

        uint32_t tx;
        uint32_t rx;

        uint32_t config;
        uint32_t status;
        uint32_t control;
    } ch[4];
};

static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
{
    qemu_set_irq(s->irq, s->irqst & s->irqen);
}

static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
{
    qemu_set_irq(ch->txdrq,
                    (ch->control & 1) &&		/* EN */
                    (ch->config & (1 << 14)) &&		/* DMAW */
                    (ch->status & (1 << 1)) &&		/* TXS */
                    ((ch->config >> 12) & 3) != 1);	/* TRM */
    qemu_set_irq(ch->rxdrq,
                    (ch->control & 1) &&		/* EN */
                    (ch->config & (1 << 15)) &&		/* DMAW */
                    (ch->status & (1 << 0)) &&		/* RXS */
                    ((ch->config >> 12) & 3) != 2);	/* TRM */
}

static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
{
    struct omap_mcspi_ch_s *ch = s->ch + chnum;

    if (!(ch->control & 1))				/* EN */
        return;
    if ((ch->status & (1 << 0)) &&			/* RXS */
                    ((ch->config >> 12) & 3) != 2 &&	/* TRM */
                    !(ch->config & (1 << 19)))		/* TURBO */
        goto intr_update;
    if ((ch->status & (1 << 1)) &&			/* TXS */
                    ((ch->config >> 12) & 3) != 1)	/* TRM */
        goto intr_update;

    if (!(s->control & 1) ||				/* SINGLE */
                    (ch->config & (1 << 20))) {		/* FORCE */
        if (ch->txrx)
            ch->rx = ch->txrx(ch->opaque, ch->tx,	/* WL */
                            1 + (0x1f & (ch->config >> 7)));
    }

    ch->tx = 0;
    ch->status |= 1 << 2;				/* EOT */
    ch->status |= 1 << 1;				/* TXS */
    if (((ch->config >> 12) & 3) != 2)			/* TRM */
        ch->status |= 1 << 0;				/* RXS */

intr_update:
    if ((ch->status & (1 << 0)) &&			/* RXS */
                    ((ch->config >> 12) & 3) != 2 &&	/* TRM */
                    !(ch->config & (1 << 19)))		/* TURBO */
        s->irqst |= 1 << (2 + 4 * chnum);		/* RX_FULL */
    if ((ch->status & (1 << 1)) &&			/* TXS */
                    ((ch->config >> 12) & 3) != 1)	/* TRM */
        s->irqst |= 1 << (0 + 4 * chnum);		/* TX_EMPTY */
    omap_mcspi_interrupt_update(s);
    omap_mcspi_dmarequest_update(ch);
}

void omap_mcspi_reset(struct omap_mcspi_s *s)
{
    int ch;

    s->sysconfig = 0;
    s->systest = 0;
    s->irqst = 0;
    s->irqen = 0;
    s->wken = 0;
    s->control = 4;

    for (ch = 0; ch < 4; ch ++) {
        s->ch[ch].config = 0x060000;
        s->ch[ch].status = 2;				/* TXS */
        s->ch[ch].control = 0;

        omap_mcspi_dmarequest_update(s->ch + ch);
    }

    omap_mcspi_interrupt_update(s);
}

static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
                                unsigned size)
{
    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
    int ch = 0;
    uint32_t ret;

    if (size != 4) {
        return omap_badwidth_read32(opaque, addr);
    }

    switch (addr) {
    case 0x00:	/* MCSPI_REVISION */
        return 0x91;

    case 0x10:	/* MCSPI_SYSCONFIG */
        return s->sysconfig;

    case 0x14:	/* MCSPI_SYSSTATUS */
        return 1;					/* RESETDONE */

    case 0x18:	/* MCSPI_IRQSTATUS */
        return s->irqst;

    case 0x1c:	/* MCSPI_IRQENABLE */
        return s->irqen;

    case 0x20:	/* MCSPI_WAKEUPENABLE */
        return s->wken;

    case 0x24:	/* MCSPI_SYST */
        return s->systest;

    case 0x28:	/* MCSPI_MODULCTRL */
        return s->control;

    case 0x68: ch ++;
        /* fall through */
    case 0x54: ch ++;
        /* fall through */
    case 0x40: ch ++;
        /* fall through */
    case 0x2c:	/* MCSPI_CHCONF */
        return s->ch[ch].config;

    case 0x6c: ch ++;
        /* fall through */
    case 0x58: ch ++;
        /* fall through */
    case 0x44: ch ++;
        /* fall through */
    case 0x30:	/* MCSPI_CHSTAT */
        return s->ch[ch].status;

    case 0x70: ch ++;
        /* fall through */
    case 0x5c: ch ++;
        /* fall through */
    case 0x48: ch ++;
        /* fall through */
    case 0x34:	/* MCSPI_CHCTRL */
        return s->ch[ch].control;

    case 0x74: ch ++;
        /* fall through */
    case 0x60: ch ++;
        /* fall through */
    case 0x4c: ch ++;
        /* fall through */
    case 0x38:	/* MCSPI_TX */
        return s->ch[ch].tx;

    case 0x78: ch ++;
        /* fall through */
    case 0x64: ch ++;
        /* fall through */
    case 0x50: ch ++;
        /* fall through */
    case 0x3c:	/* MCSPI_RX */
        s->ch[ch].status &= ~(1 << 0);			/* RXS */
        ret = s->ch[ch].rx;
        omap_mcspi_transfer_run(s, ch);
        return ret;
    }

    OMAP_BAD_REG(addr);
    return 0;
}

static void omap_mcspi_write(void *opaque, hwaddr addr,
                             uint64_t value, unsigned size)
{
    struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
    int ch = 0;

    if (size != 4) {
        omap_badwidth_write32(opaque, addr, value);
        return;
    }

    switch (addr) {
    case 0x00:	/* MCSPI_REVISION */
    case 0x14:	/* MCSPI_SYSSTATUS */
    case 0x30:	/* MCSPI_CHSTAT0 */
    case 0x3c:	/* MCSPI_RX0 */
    case 0x44:	/* MCSPI_CHSTAT1 */
    case 0x50:	/* MCSPI_RX1 */
    case 0x58:	/* MCSPI_CHSTAT2 */
    case 0x64:	/* MCSPI_RX2 */
    case 0x6c:	/* MCSPI_CHSTAT3 */
    case 0x78:	/* MCSPI_RX3 */
        OMAP_RO_REG(addr);
        return;

    case 0x10:	/* MCSPI_SYSCONFIG */
        if (value & (1 << 1))				/* SOFTRESET */
            omap_mcspi_reset(s);
        s->sysconfig = value & 0x31d;
        break;

    case 0x18:	/* MCSPI_IRQSTATUS */
        if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
            s->irqst &= ~value;
            omap_mcspi_interrupt_update(s);
        }
        break;

    case 0x1c:	/* MCSPI_IRQENABLE */
        s->irqen = value & 0x1777f;
        omap_mcspi_interrupt_update(s);
        break;

    case 0x20:	/* MCSPI_WAKEUPENABLE */
        s->wken = value & 1;
        break;

    case 0x24:	/* MCSPI_SYST */
        if (s->control & (1 << 3))			/* SYSTEM_TEST */
            if (value & (1 << 11)) {			/* SSB */
                s->irqst |= 0x1777f;
                omap_mcspi_interrupt_update(s);
            }
        s->systest = value & 0xfff;
        break;

    case 0x28:	/* MCSPI_MODULCTRL */
        if (value & (1 << 3))				/* SYSTEM_TEST */
            if (s->systest & (1 << 11)) {		/* SSB */
                s->irqst |= 0x1777f;
                omap_mcspi_interrupt_update(s);
            }
        s->control = value & 0xf;
        break;

    case 0x68: ch ++;
        /* fall through */
    case 0x54: ch ++;
        /* fall through */
    case 0x40: ch ++;
        /* fall through */
    case 0x2c:	/* MCSPI_CHCONF */
        if ((value ^ s->ch[ch].config) & (3 << 14))	/* DMAR | DMAW */
            omap_mcspi_dmarequest_update(s->ch + ch);
        if (((value >> 12) & 3) == 3) { /* TRM */
            qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid TRM value (3)\n",
                          __func__);
        }
        if (((value >> 7) & 0x1f) < 3) { /* WL */
            qemu_log_mask(LOG_GUEST_ERROR,
                          "%s: invalid WL value (%" PRIx64 ")\n",
                          __func__, (value >> 7) & 0x1f);
        }
        s->ch[ch].config = value & 0x7fffff;
        break;

    case 0x70: ch ++;
        /* fall through */
    case 0x5c: ch ++;
        /* fall through */
    case 0x48: ch ++;
        /* fall through */
    case 0x34:	/* MCSPI_CHCTRL */
        if (value & ~s->ch[ch].control & 1) {		/* EN */
            s->ch[ch].control |= 1;
            omap_mcspi_transfer_run(s, ch);
        } else
            s->ch[ch].control = value & 1;
        break;

    case 0x74: ch ++;
        /* fall through */
    case 0x60: ch ++;
        /* fall through */
    case 0x4c: ch ++;
        /* fall through */
    case 0x38:	/* MCSPI_TX */
        s->ch[ch].tx = value;
        s->ch[ch].status &= ~(1 << 1);			/* TXS */
        omap_mcspi_transfer_run(s, ch);
        break;

    default:
        OMAP_BAD_REG(addr);
        return;
    }
}

static const MemoryRegionOps omap_mcspi_ops = {
    .read = omap_mcspi_read,
    .write = omap_mcspi_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
                qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
{
    struct omap_mcspi_s *s = g_new0(struct omap_mcspi_s, 1);
    struct omap_mcspi_ch_s *ch = s->ch;

    s->irq = irq;
    s->chnum = chnum;
    while (chnum --) {
        ch->txdrq = *drq ++;
        ch->rxdrq = *drq ++;
        ch ++;
    }
    omap_mcspi_reset(s);

    memory_region_init_io(&s->iomem, NULL, &omap_mcspi_ops, s, "omap.mcspi",
                          omap_l4_region_size(ta, 0));
    omap_l4_attach(ta, 0, &s->iomem);

    return s;
}

void omap_mcspi_attach(struct omap_mcspi_s *s,
                uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
                int chipselect)
{
    if (chipselect < 0 || chipselect >= s->chnum)
        hw_error("%s: Bad chipselect %i\n", __func__, chipselect);

    s->ch[chipselect].txrx = txrx;
    s->ch[chipselect].opaque = opaque;
}
Commit	Line	Data
2d08cc7c	1	/*
	2	* TI OMAP processor's Multichannel SPI emulation.
	3	*
	4	* Copyright (C) 2007-2009 Nokia Corporation
	5	*
	6	* Original code for OMAP2 by Andrzej Zaborowski <[email protected]>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 or
	11	* (at your option) any later version of the License.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License along
	19	* with this program; if not, write to the Free Software Foundation, Inc.,
	20	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	21	*/
17b7f2db	22	#include "qemu/osdep.h"
31a1246d	23	#include "qemu/log.h"
83c9f4ca	24	#include "hw/hw.h"
0d09e41a	25	#include "hw/arm/omap.h"
2d08cc7c	26
	27	/* Multichannel SPI */
	28	struct omap_mcspi_s {
1a072690	29	MemoryRegion iomem;
2d08cc7c	30	qemu_irq irq;
	31	int chnum;
	32
	33	uint32_t sysconfig;
	34	uint32_t systest;
	35	uint32_t irqst;
	36	uint32_t irqen;
	37	uint32_t wken;
	38	uint32_t control;
	39
	40	struct omap_mcspi_ch_s {
	41	qemu_irq txdrq;
	42	qemu_irq rxdrq;
	43	uint32_t (txrx)(void opaque, uint32_t, int);
	44	void *opaque;
	45
	46	uint32_t tx;
	47	uint32_t rx;
	48
	49	uint32_t config;
	50	uint32_t status;
	51	uint32_t control;
	52	} ch[4];
	53	};
	54
	55	static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
	56	{
	57	qemu_set_irq(s->irq, s->irqst & s->irqen);
	58	}
	59
	60	static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
	61	{
	62	qemu_set_irq(ch->txdrq,
	63	(ch->control & 1) && /* EN */
	64	(ch->config & (1 << 14)) && /* DMAW */
	65	(ch->status & (1 << 1)) && /* TXS */
	66	((ch->config >> 12) & 3) != 1); /* TRM */
	67	qemu_set_irq(ch->rxdrq,
	68	(ch->control & 1) && /* EN */
	69	(ch->config & (1 << 15)) && /* DMAW */
	70	(ch->status & (1 << 0)) && /* RXS */
	71	((ch->config >> 12) & 3) != 2); /* TRM */
	72	}
	73
	74	static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
	75	{
	76	struct omap_mcspi_ch_s *ch = s->ch + chnum;
	77
	78	if (!(ch->control & 1)) /* EN */
	79	return;
	80	if ((ch->status & (1 << 0)) && /* RXS */
	81	((ch->config >> 12) & 3) != 2 && /* TRM */
	82	!(ch->config & (1 << 19))) /* TURBO */
	83	goto intr_update;
	84	if ((ch->status & (1 << 1)) && /* TXS */
	85	((ch->config >> 12) & 3) != 1) /* TRM */
	86	goto intr_update;
	87
	88	if (!(s->control & 1) \|\| /* SINGLE */
	89	(ch->config & (1 << 20))) { /* FORCE */
	90	if (ch->txrx)
	91	ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
	92	1 + (0x1f & (ch->config >> 7)));
	93	}
94
95	ch->tx = 0;
96	ch->status \|= 1 << 2; /* EOT */
97	ch->status \|= 1 << 1; /* TXS */
98	if (((ch->config >> 12) & 3) != 2) /* TRM */
99	ch->status \|= 1 << 0; /* RXS */
100
101	intr_update:
102	if ((ch->status & (1 << 0)) && /* RXS */
103	((ch->config >> 12) & 3) != 2 && /* TRM */
104	!(ch->config & (1 << 19))) /* TURBO */
105	s->irqst \|= 1 << (2 + 4 * chnum); /* RX_FULL */
106	if ((ch->status & (1 << 1)) && /* TXS */
107	((ch->config >> 12) & 3) != 1) /* TRM */
108	s->irqst \|= 1 << (0 + 4 * chnum); /* TX_EMPTY */
109	omap_mcspi_interrupt_update(s);
110	omap_mcspi_dmarequest_update(ch);
111	}
112
113	void omap_mcspi_reset(struct omap_mcspi_s *s)
114	{
115	int ch;
116
117	s->sysconfig = 0;
118	s->systest = 0;
119	s->irqst = 0;
120	s->irqen = 0;
121	s->wken = 0;
122	s->control = 4;
123
124	for (ch = 0; ch < 4; ch ++) {
125	s->ch[ch].config = 0x060000;
126	s->ch[ch].status = 2; /* TXS */
127	s->ch[ch].control = 0;
128
129	omap_mcspi_dmarequest_update(s->ch + ch);
130	}
131
132	omap_mcspi_interrupt_update(s);
133	}
134
a8170e5e	135	static uint64_t omap_mcspi_read(void *opaque, hwaddr addr,
1a072690	136	unsigned size)
2d08cc7c	137	{
	138	struct omap_mcspi_s s = (struct omap_mcspi_s ) opaque;
	139	int ch = 0;
	140	uint32_t ret;
	141
1a072690 BC	142	if (size != 4) {
	143	return omap_badwidth_read32(opaque, addr);
	144	}
	145
2d08cc7c	146	switch (addr) {
	147	case 0x00: /* MCSPI_REVISION */
	148	return 0x91;
	149
	150	case 0x10: /* MCSPI_SYSCONFIG */
	151	return s->sysconfig;
	152
	153	case 0x14: /* MCSPI_SYSSTATUS */
	154	return 1; /* RESETDONE */
	155
	156	case 0x18: /* MCSPI_IRQSTATUS */
	157	return s->irqst;
	158
	159	case 0x1c: /* MCSPI_IRQENABLE */
	160	return s->irqen;
	161
	162	case 0x20: /* MCSPI_WAKEUPENABLE */
	163	return s->wken;
	164
	165	case 0x24: /* MCSPI_SYST */
	166	return s->systest;
	167
	168	case 0x28: /* MCSPI_MODULCTRL */
	169	return s->control;
	170
	171	case 0x68: ch ++;
be688dfb	172	/* fall through */
2d08cc7c	173	case 0x54: ch ++;
be688dfb	174	/* fall through */
2d08cc7c	175	case 0x40: ch ++;
be688dfb	176	/* fall through */
2d08cc7c	177	case 0x2c: /* MCSPI_CHCONF */
	178	return s->ch[ch].config;
	179
	180	case 0x6c: ch ++;
be688dfb	181	/* fall through */
2d08cc7c	182	case 0x58: ch ++;
be688dfb	183	/* fall through */
2d08cc7c	184	case 0x44: ch ++;
be688dfb	185	/* fall through */
2d08cc7c	186	case 0x30: /* MCSPI_CHSTAT */
	187	return s->ch[ch].status;
	188
	189	case 0x70: ch ++;
be688dfb	190	/* fall through */
2d08cc7c	191	case 0x5c: ch ++;
be688dfb	192	/* fall through */
2d08cc7c	193	case 0x48: ch ++;
be688dfb	194	/* fall through */
2d08cc7c	195	case 0x34: /* MCSPI_CHCTRL */
	196	return s->ch[ch].control;
	197
	198	case 0x74: ch ++;
be688dfb	199	/* fall through */
2d08cc7c	200	case 0x60: ch ++;
be688dfb	201	/* fall through */
2d08cc7c	202	case 0x4c: ch ++;
be688dfb	203	/* fall through */
2d08cc7c	204	case 0x38: /* MCSPI_TX */
	205	return s->ch[ch].tx;
	206
	207	case 0x78: ch ++;
be688dfb	208	/* fall through */
2d08cc7c	209	case 0x64: ch ++;
be688dfb	210	/* fall through */
2d08cc7c	211	case 0x50: ch ++;
be688dfb	212	/* fall through */
2d08cc7c	213	case 0x3c: /* MCSPI_RX */
	214	s->ch[ch].status &= ~(1 << 0); /* RXS */
	215	ret = s->ch[ch].rx;
	216	omap_mcspi_transfer_run(s, ch);
	217	return ret;
	218	}
	219
	220	OMAP_BAD_REG(addr);
	221	return 0;
	222	}
	223
a8170e5e	224	static void omap_mcspi_write(void *opaque, hwaddr addr,
1a072690	225	uint64_t value, unsigned size)
2d08cc7c	226	{
	227	struct omap_mcspi_s s = (struct omap_mcspi_s ) opaque;
	228	int ch = 0;
	229
1a072690	230	if (size != 4) {
77a8257e SW	231	omap_badwidth_write32(opaque, addr, value);
77a8257e SW	232	return;
1a072690 BC	233	}
1a072690 BC	234
2d08cc7c	235	switch (addr) {
	236	case 0x00: /* MCSPI_REVISION */
	237	case 0x14: /* MCSPI_SYSSTATUS */
	238	case 0x30: /* MCSPI_CHSTAT0 */
	239	case 0x3c: /* MCSPI_RX0 */
	240	case 0x44: /* MCSPI_CHSTAT1 */
	241	case 0x50: /* MCSPI_RX1 */
	242	case 0x58: /* MCSPI_CHSTAT2 */
	243	case 0x64: /* MCSPI_RX2 */
	244	case 0x6c: /* MCSPI_CHSTAT3 */
	245	case 0x78: /* MCSPI_RX3 */
	246	OMAP_RO_REG(addr);
	247	return;
	248
	249	case 0x10: /* MCSPI_SYSCONFIG */
	250	if (value & (1 << 1)) /* SOFTRESET */
	251	omap_mcspi_reset(s);
	252	s->sysconfig = value & 0x31d;
	253	break;
	254
	255	case 0x18: /* MCSPI_IRQSTATUS */
	256	if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
	257	s->irqst &= ~value;
	258	omap_mcspi_interrupt_update(s);
	259	}
	260	break;
	261
	262	case 0x1c: /* MCSPI_IRQENABLE */
	263	s->irqen = value & 0x1777f;
	264	omap_mcspi_interrupt_update(s);
	265	break;
	266
	267	case 0x20: /* MCSPI_WAKEUPENABLE */
	268	s->wken = value & 1;
	269	break;
	270
	271	case 0x24: /* MCSPI_SYST */
	272	if (s->control & (1 << 3)) /* SYSTEM_TEST */
	273	if (value & (1 << 11)) { /* SSB */
	274	s->irqst \|= 0x1777f;
	275	omap_mcspi_interrupt_update(s);
	276	}
	277	s->systest = value & 0xfff;
	278	break;
	279
	280	case 0x28: /* MCSPI_MODULCTRL */
	281	if (value & (1 << 3)) /* SYSTEM_TEST */
	282	if (s->systest & (1 << 11)) { /* SSB */
	283	s->irqst \|= 0x1777f;
	284	omap_mcspi_interrupt_update(s);
	285	}
	286	s->control = value & 0xf;
	287	break;
	288
	289	case 0x68: ch ++;
be688dfb	290	/* fall through */
2d08cc7c	291	case 0x54: ch ++;
be688dfb	292	/* fall through */
2d08cc7c	293	case 0x40: ch ++;
be688dfb	294	/* fall through */
2d08cc7c	295	case 0x2c: /* MCSPI_CHCONF */
	296	if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR \| DMAW */
	297	omap_mcspi_dmarequest_update(s->ch + ch);
31a1246d PMD	298	if (((value >> 12) & 3) == 3) { /* TRM */
	299	qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid TRM value (3)\n",
	300	__func__);
	301	}
	302	if (((value >> 7) & 0x1f) < 3) { /* WL */
	303	qemu_log_mask(LOG_GUEST_ERROR,
	304	"%s: invalid WL value (%" PRIx64 ")\n",
	305	__func__, (value >> 7) & 0x1f);
	306	}
2d08cc7c	307	s->ch[ch].config = value & 0x7fffff;
	308	break;
	309
	310	case 0x70: ch ++;
be688dfb	311	/* fall through */
2d08cc7c	312	case 0x5c: ch ++;
be688dfb	313	/* fall through */
2d08cc7c	314	case 0x48: ch ++;
be688dfb	315	/* fall through */
2d08cc7c	316	case 0x34: /* MCSPI_CHCTRL */
	317	if (value & ~s->ch[ch].control & 1) { /* EN */
	318	s->ch[ch].control \|= 1;
	319	omap_mcspi_transfer_run(s, ch);
	320	} else
	321	s->ch[ch].control = value & 1;
	322	break;
	323
	324	case 0x74: ch ++;
be688dfb	325	/* fall through */
2d08cc7c	326	case 0x60: ch ++;
be688dfb	327	/* fall through */
2d08cc7c	328	case 0x4c: ch ++;
be688dfb	329	/* fall through */
2d08cc7c	330	case 0x38: /* MCSPI_TX */
	331	s->ch[ch].tx = value;
	332	s->ch[ch].status &= ~(1 << 1); /* TXS */
	333	omap_mcspi_transfer_run(s, ch);
	334	break;
	335
	336	default:
	337	OMAP_BAD_REG(addr);
	338	return;
	339	}
	340	}
	341
1a072690 BC	342	static const MemoryRegionOps omap_mcspi_ops = {
	343	.read = omap_mcspi_read,
	344	.write = omap_mcspi_write,
	345	.endianness = DEVICE_NATIVE_ENDIAN,
2d08cc7c	346	};
	347
	348	struct omap_mcspi_s omap_mcspi_init(struct omap_target_agent_s ta, int chnum,
	349	qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
	350	{
b45c03f5	351	struct omap_mcspi_s *s = g_new0(struct omap_mcspi_s, 1);
2d08cc7c	352	struct omap_mcspi_ch_s *ch = s->ch;
	353
	354	s->irq = irq;
	355	s->chnum = chnum;
	356	while (chnum --) {
	357	ch->txdrq = *drq ++;
	358	ch->rxdrq = *drq ++;
	359	ch ++;
	360	}
	361	omap_mcspi_reset(s);
	362
2c9b15ca	363	memory_region_init_io(&s->iomem, NULL, &omap_mcspi_ops, s, "omap.mcspi",
1a072690	364	omap_l4_region_size(ta, 0));
f44336c5	365	omap_l4_attach(ta, 0, &s->iomem);
2d08cc7c	366
	367	return s;
	368	}
	369
	370	void omap_mcspi_attach(struct omap_mcspi_s *s,
	371	uint32_t (txrx)(void opaque, uint32_t, int), void *opaque,
	372	int chipselect)
	373	{
	374	if (chipselect < 0 \|\| chipselect >= s->chnum)
a89f364a	375	hw_error("%s: Bad chipselect %i\n", __func__, chipselect);
2d08cc7c	376
	377	s->ch[chipselect].txrx = txrx;
	378	s->ch[chipselect].opaque = opaque;
	379	}