[qemu.git] / hw / riscv / virt.c

/*
 * QEMU RISC-V VirtIO Board
 *
 * Copyright (c) 2017 SiFive, Inc.
 *
 * RISC-V machine with 16550a UART and VirtIO MMIO
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/log.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "hw/hw.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
#include "target/riscv/cpu.h"
#include "hw/riscv/riscv_htif.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_test.h"
#include "hw/riscv/virt.h"
#include "chardev/char.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "exec/address-spaces.h"
#include "elf.h"

#include <libfdt.h>

static const struct MemmapEntry {
    hwaddr base;
    hwaddr size;
} virt_memmap[] = {
    [VIRT_DEBUG] =    {        0x0,      0x100 },
    [VIRT_MROM] =     {     0x1000,    0x11000 },
    [VIRT_TEST] =     {   0x100000,     0x1000 },
    [VIRT_CLINT] =    {  0x2000000,    0x10000 },
    [VIRT_PLIC] =     {  0xc000000,  0x4000000 },
    [VIRT_UART0] =    { 0x10000000,      0x100 },
    [VIRT_VIRTIO] =   { 0x10001000,     0x1000 },
    [VIRT_DRAM] =     { 0x80000000,        0x0 },
};

static uint64_t load_kernel(const char *kernel_filename)
{
    uint64_t kernel_entry, kernel_high;

    if (load_elf(kernel_filename, NULL, NULL,
                 &kernel_entry, NULL, &kernel_high,
                 0, EM_RISCV, 1, 0) < 0) {
        error_report("could not load kernel '%s'", kernel_filename);
        exit(1);
    }
    return kernel_entry;
}

static hwaddr load_initrd(const char *filename, uint64_t mem_size,
                          uint64_t kernel_entry, hwaddr *start)
{
    int size;

    /* We want to put the initrd far enough into RAM that when the
     * kernel is uncompressed it will not clobber the initrd. However
     * on boards without much RAM we must ensure that we still leave
     * enough room for a decent sized initrd, and on boards with large
     * amounts of RAM we must avoid the initrd being so far up in RAM
     * that it is outside lowmem and inaccessible to the kernel.
     * So for boards with less  than 256MB of RAM we put the initrd
     * halfway into RAM, and for boards with 256MB of RAM or more we put
     * the initrd at 128MB.
     */
    *start = kernel_entry + MIN(mem_size / 2, 128 * MiB);

    size = load_ramdisk(filename, *start, mem_size - *start);
    if (size == -1) {
        size = load_image_targphys(filename, *start, mem_size - *start);
        if (size == -1) {
            error_report("could not load ramdisk '%s'", filename);
            exit(1);
        }
    }
    return *start + size;
}

static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
    uint64_t mem_size, const char *cmdline)
{
    void *fdt;
    int cpu;
    uint32_t *cells;
    char *nodename;
    uint32_t plic_phandle, phandle = 1;
    int i;

    fdt = s->fdt = create_device_tree(&s->fdt_size);
    if (!fdt) {
        error_report("create_device_tree() failed");
        exit(1);
    }

    qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
    qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
    qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
    qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);

    qemu_fdt_add_subnode(fdt, "/soc");
    qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
    qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
    qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);

    nodename = g_strdup_printf("/memory@%lx",
        (long)memmap[VIRT_DRAM].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
        mem_size >> 32, mem_size);
    qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
    g_free(nodename);

    qemu_fdt_add_subnode(fdt, "/cpus");
    qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
                          SIFIVE_CLINT_TIMEBASE_FREQ);
    qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
    qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);

    for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
        int cpu_phandle = phandle++;
        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        char *isa = riscv_isa_string(&s->soc.harts[cpu]);
        qemu_fdt_add_subnode(fdt, nodename);
        qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
                              VIRT_CLOCK_FREQ);
        qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
        qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
        qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
        qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
        qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
        qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
        qemu_fdt_add_subnode(fdt, intc);
        qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
        qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
        qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
        qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
        qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
        g_free(isa);
        g_free(intc);
        g_free(nodename);
    }

    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
        nodename =
            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
        g_free(nodename);
    }
    nodename = g_strdup_printf("/soc/clint@%lx",
        (long)memmap[VIRT_CLINT].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[VIRT_CLINT].base,
        0x0, memmap[VIRT_CLINT].size);
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
    g_free(cells);
    g_free(nodename);

    plic_phandle = phandle++;
    cells =  g_new0(uint32_t, s->soc.num_harts * 4);
    for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
        nodename =
            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
        g_free(nodename);
    }
    nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
        (long)memmap[VIRT_PLIC].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
    qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
        cells, s->soc.num_harts * sizeof(uint32_t) * 4);
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[VIRT_PLIC].base,
        0x0, memmap[VIRT_PLIC].size);
    qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
    qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
    qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
    qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
    plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
    g_free(cells);
    g_free(nodename);

    for (i = 0; i < VIRTIO_COUNT; i++) {
        nodename = g_strdup_printf("/virtio_mmio@%lx",
            (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
        qemu_fdt_add_subnode(fdt, nodename);
        qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
        qemu_fdt_setprop_cells(fdt, nodename, "reg",
            0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
            0x0, memmap[VIRT_VIRTIO].size);
        qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
        qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
        g_free(nodename);
    }

    nodename = g_strdup_printf("/test@%lx",
        (long)memmap[VIRT_TEST].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[VIRT_TEST].base,
        0x0, memmap[VIRT_TEST].size);

    nodename = g_strdup_printf("/uart@%lx",
        (long)memmap[VIRT_UART0].base);
    qemu_fdt_add_subnode(fdt, nodename);
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
        0x0, memmap[VIRT_UART0].base,
        0x0, memmap[VIRT_UART0].size);
    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
        qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
        qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ);

    qemu_fdt_add_subnode(fdt, "/chosen");
    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
    if (cmdline) {
        qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
    }
    g_free(nodename);

    return fdt;
}

static void riscv_virt_board_init(MachineState *machine)
{
    const struct MemmapEntry *memmap = virt_memmap;

    RISCVVirtState *s = g_new0(RISCVVirtState, 1);
    MemoryRegion *system_memory = get_system_memory();
    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
    char *plic_hart_config;
    size_t plic_hart_config_len;
    int i;
    void *fdt;

    /* Initialize SOC */
    object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
                            TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
    object_property_set_str(OBJECT(&s->soc), VIRT_CPU, "cpu-type",
                            &error_abort);
    object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
                            &error_abort);
    object_property_set_bool(OBJECT(&s->soc), true, "realized",
                            &error_abort);

    /* register system main memory (actual RAM) */
    memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
                           machine->ram_size, &error_fatal);
    memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
        main_mem);

    /* create device tree */
    fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);

    /* boot rom */
    memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
                           memmap[VIRT_MROM].size, &error_fatal);
    memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
                                mask_rom);

    if (machine->kernel_filename) {
        uint64_t kernel_entry = load_kernel(machine->kernel_filename);

        if (machine->initrd_filename) {
            hwaddr start;
            hwaddr end = load_initrd(machine->initrd_filename,
                                     machine->ram_size, kernel_entry,
                                     &start);
            qemu_fdt_setprop_cell(fdt, "/chosen",
                                  "linux,initrd-start", start);
            qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
                                  end);
        }
    }

    /* reset vector */
    uint32_t reset_vec[8] = {
        0x00000297,                  /* 1:  auipc  t0, %pcrel_hi(dtb) */
        0x02028593,                  /*     addi   a1, t0, %pcrel_lo(1b) */
        0xf1402573,                  /*     csrr   a0, mhartid  */
#if defined(TARGET_RISCV32)
        0x0182a283,                  /*     lw     t0, 24(t0) */
#elif defined(TARGET_RISCV64)
        0x0182b283,                  /*     ld     t0, 24(t0) */
#endif
        0x00028067,                  /*     jr     t0 */
        0x00000000,
        memmap[VIRT_DRAM].base,      /* start: .dword memmap[VIRT_DRAM].base */
        0x00000000,
                                     /* dtb: */
    };

    /* copy in the reset vector in little_endian byte order */
    for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
        reset_vec[i] = cpu_to_le32(reset_vec[i]);
    }
    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
                          memmap[VIRT_MROM].base, &address_space_memory);

    /* copy in the device tree */
    if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
            memmap[VIRT_MROM].size - sizeof(reset_vec)) {
        error_report("not enough space to store device-tree");
        exit(1);
    }
    qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
    rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
                          memmap[VIRT_MROM].base + sizeof(reset_vec),
                          &address_space_memory);

    /* create PLIC hart topology configuration string */
    plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
    plic_hart_config = g_malloc0(plic_hart_config_len);
    for (i = 0; i < smp_cpus; i++) {
        if (i != 0) {
            strncat(plic_hart_config, ",", plic_hart_config_len);
        }
        strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
        plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
    }

    /* MMIO */
    s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
        plic_hart_config,
        VIRT_PLIC_NUM_SOURCES,
        VIRT_PLIC_NUM_PRIORITIES,
        VIRT_PLIC_PRIORITY_BASE,
        VIRT_PLIC_PENDING_BASE,
        VIRT_PLIC_ENABLE_BASE,
        VIRT_PLIC_ENABLE_STRIDE,
        VIRT_PLIC_CONTEXT_BASE,
        VIRT_PLIC_CONTEXT_STRIDE,
        memmap[VIRT_PLIC].size);
    sifive_clint_create(memmap[VIRT_CLINT].base,
        memmap[VIRT_CLINT].size, smp_cpus,
        SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
    sifive_test_create(memmap[VIRT_TEST].base);

    for (i = 0; i < VIRTIO_COUNT; i++) {
        sysbus_create_simple("virtio-mmio",
            memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
            qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
    }

    serial_mm_init(system_memory, memmap[VIRT_UART0].base,
        0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
        serial_hd(0), DEVICE_LITTLE_ENDIAN);

    g_free(plic_hart_config);
}

static void riscv_virt_board_machine_init(MachineClass *mc)
{
    mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
    mc->init = riscv_virt_board_init;
    mc->max_cpus = 8; /* hardcoded limit in BBL */
}

DEFINE_MACHINE("virt", riscv_virt_board_machine_init)
Commit	Line	Data
04331d0b MC	1	/*
	2	* QEMU RISC-V VirtIO Board
	3	*
	4	* Copyright (c) 2017 SiFive, Inc.
	5	*
	6	* RISC-V machine with 16550a UART and VirtIO MMIO
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2 or later, as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include "qemu/osdep.h"
4bf46af7	22	#include "qemu/units.h"
04331d0b MC	23	#include "qemu/log.h"
	24	#include "qemu/error-report.h"
	25	#include "qapi/error.h"
	26	#include "hw/hw.h"
	27	#include "hw/boards.h"
	28	#include "hw/loader.h"
	29	#include "hw/sysbus.h"
	30	#include "hw/char/serial.h"
	31	#include "target/riscv/cpu.h"
	32	#include "hw/riscv/riscv_htif.h"
	33	#include "hw/riscv/riscv_hart.h"
	34	#include "hw/riscv/sifive_plic.h"
	35	#include "hw/riscv/sifive_clint.h"
	36	#include "hw/riscv/sifive_test.h"
	37	#include "hw/riscv/virt.h"
	38	#include "chardev/char.h"
	39	#include "sysemu/arch_init.h"
	40	#include "sysemu/device_tree.h"
	41	#include "exec/address-spaces.h"
	42	#include "elf.h"
	43
5aec3247 MC	44	#include <libfdt.h>
5aec3247 MC	45
04331d0b MC	46	static const struct MemmapEntry {
	47	hwaddr base;
	48	hwaddr size;
	49	} virt_memmap[] = {
	50	[VIRT_DEBUG] = { 0x0, 0x100 },
5aec3247 MC	51	[VIRT_MROM] = { 0x1000, 0x11000 },
5aec3247 MC	52	[VIRT_TEST] = { 0x100000, 0x1000 },
04331d0b MC	53	[VIRT_CLINT] = { 0x2000000, 0x10000 },
	54	[VIRT_PLIC] = { 0xc000000, 0x4000000 },
	55	[VIRT_UART0] = { 0x10000000, 0x100 },
	56	[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
	57	[VIRT_DRAM] = { 0x80000000, 0x0 },
	58	};
	59
04331d0b MC	60	static uint64_t load_kernel(const char *kernel_filename)
	61	{
	62	uint64_t kernel_entry, kernel_high;
	63
b7938980	64	if (load_elf(kernel_filename, NULL, NULL,
04331d0b	65	&kernel_entry, NULL, &kernel_high,
89854803	66	0, EM_RISCV, 1, 0) < 0) {
371b74e2	67	error_report("could not load kernel '%s'", kernel_filename);
04331d0b MC	68	exit(1);
	69	}
	70	return kernel_entry;
	71	}
	72
	73	static hwaddr load_initrd(const char *filename, uint64_t mem_size,
	74	uint64_t kernel_entry, hwaddr *start)
	75	{
	76	int size;
	77
	78	/* We want to put the initrd far enough into RAM that when the
	79	* kernel is uncompressed it will not clobber the initrd. However
	80	* on boards without much RAM we must ensure that we still leave
	81	* enough room for a decent sized initrd, and on boards with large
	82	* amounts of RAM we must avoid the initrd being so far up in RAM
	83	* that it is outside lowmem and inaccessible to the kernel.
	84	* So for boards with less than 256MB of RAM we put the initrd
	85	* halfway into RAM, and for boards with 256MB of RAM or more we put
	86	* the initrd at 128MB.
	87	*/
4bf46af7	88	start = kernel_entry + MIN(mem_size / 2, 128 MiB);
04331d0b MC	89
	90	size = load_ramdisk(filename, start, mem_size - start);
	91	if (size == -1) {
	92	size = load_image_targphys(filename, start, mem_size - start);
	93	if (size == -1) {
371b74e2	94	error_report("could not load ramdisk '%s'", filename);
04331d0b MC	95	exit(1);
	96	}
	97	}
	98	return *start + size;
	99	}
	100
	101	static void create_fdt(RISCVVirtState s, const struct MemmapEntry *memmap,
	102	uint64_t mem_size, const char *cmdline)
	103	{
	104	void *fdt;
	105	int cpu;
	106	uint32_t *cells;
	107	char *nodename;
	108	uint32_t plic_phandle, phandle = 1;
	109	int i;
	110
	111	fdt = s->fdt = create_device_tree(&s->fdt_size);
	112	if (!fdt) {
	113	error_report("create_device_tree() failed");
	114	exit(1);
	115	}
	116
	117	qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
	118	qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
	119	qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
	120	qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
	121
	122	qemu_fdt_add_subnode(fdt, "/soc");
	123	qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
53f54508	124	qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
04331d0b MC	125	qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
	126	qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
	127
	128	nodename = g_strdup_printf("/memory@%lx",
	129	(long)memmap[VIRT_DRAM].base);
	130	qemu_fdt_add_subnode(fdt, nodename);
	131	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	132	memmap[VIRT_DRAM].base >> 32, memmap[VIRT_DRAM].base,
	133	mem_size >> 32, mem_size);
	134	qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
	135	g_free(nodename);
	136
	137	qemu_fdt_add_subnode(fdt, "/cpus");
2a8756ed MC	138	qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
2a8756ed MC	139	SIFIVE_CLINT_TIMEBASE_FREQ);
04331d0b MC	140	qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
	141	qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
	142
	143	for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
	144	int cpu_phandle = phandle++;
	145	nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
	146	char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	147	char *isa = riscv_isa_string(&s->soc.harts[cpu]);
	148	qemu_fdt_add_subnode(fdt, nodename);
2a8756ed MC	149	qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
2a8756ed MC	150	VIRT_CLOCK_FREQ);
04331d0b MC	151	qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
	152	qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
	153	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
	154	qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
	155	qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
	156	qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
	157	qemu_fdt_add_subnode(fdt, intc);
	158	qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
	159	qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
	160	qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
	161	qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
	162	qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
	163	g_free(isa);
	164	g_free(intc);
	165	g_free(nodename);
	166	}
	167
	168	cells = g_new0(uint32_t, s->soc.num_harts * 4);
	169	for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
	170	nodename =
	171	g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	172	uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
	173	cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
	174	cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
	175	cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
	176	cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
	177	g_free(nodename);
	178	}
	179	nodename = g_strdup_printf("/soc/clint@%lx",
	180	(long)memmap[VIRT_CLINT].base);
	181	qemu_fdt_add_subnode(fdt, nodename);
	182	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
	183	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	184	0x0, memmap[VIRT_CLINT].base,
	185	0x0, memmap[VIRT_CLINT].size);
	186	qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
	187	cells, s->soc.num_harts * sizeof(uint32_t) * 4);
	188	g_free(cells);
	189	g_free(nodename);
	190
	191	plic_phandle = phandle++;
	192	cells = g_new0(uint32_t, s->soc.num_harts * 4);
	193	for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
	194	nodename =
	195	g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
	196	uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
	197	cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
	198	cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
	199	cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
	200	cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
	201	g_free(nodename);
	202	}
	203	nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
	204	(long)memmap[VIRT_PLIC].base);
	205	qemu_fdt_add_subnode(fdt, nodename);
	206	qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
	207	qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
	208	qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
	209	qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
	210	cells, s->soc.num_harts * sizeof(uint32_t) * 4);
	211	qemu_fdt_setprop_cells(fdt, nodename, "reg",
	212	0x0, memmap[VIRT_PLIC].base,
	213	0x0, memmap[VIRT_PLIC].size);
	214	qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
215	qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
216	qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
217	qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
218	qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
219	plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
220	g_free(cells);
221	g_free(nodename);
222
223	for (i = 0; i < VIRTIO_COUNT; i++) {
224	nodename = g_strdup_printf("/virtio_mmio@%lx",
225	(long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
226	qemu_fdt_add_subnode(fdt, nodename);
227	qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
228	qemu_fdt_setprop_cells(fdt, nodename, "reg",
229	0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
230	0x0, memmap[VIRT_VIRTIO].size);
231	qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
232	qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i);
233	g_free(nodename);
234	}
235
236	nodename = g_strdup_printf("/test@%lx",
237	(long)memmap[VIRT_TEST].base);
238	qemu_fdt_add_subnode(fdt, nodename);
239	qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,test0");
240	qemu_fdt_setprop_cells(fdt, nodename, "reg",
241	0x0, memmap[VIRT_TEST].base,
242	0x0, memmap[VIRT_TEST].size);
243
244	nodename = g_strdup_printf("/uart@%lx",
245	(long)memmap[VIRT_UART0].base);
246	qemu_fdt_add_subnode(fdt, nodename);
247	qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
248	qemu_fdt_setprop_cells(fdt, nodename, "reg",
249	0x0, memmap[VIRT_UART0].base,
250	0x0, memmap[VIRT_UART0].size);
251	qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
252	qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
253	qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ);
254
255	qemu_fdt_add_subnode(fdt, "/chosen");
256	qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
7c28f4da MC	257	if (cmdline) {
	258	qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
	259	}
04331d0b MC	260	g_free(nodename);
	261
	262	return fdt;
	263	}
	264
	265	static void riscv_virt_board_init(MachineState *machine)
	266	{
	267	const struct MemmapEntry *memmap = virt_memmap;
	268
	269	RISCVVirtState *s = g_new0(RISCVVirtState, 1);
	270	MemoryRegion *system_memory = get_system_memory();
	271	MemoryRegion *main_mem = g_new(MemoryRegion, 1);
5aec3247	272	MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
04331d0b MC	273	char *plic_hart_config;
	274	size_t plic_hart_config_len;
	275	int i;
	276	void *fdt;
	277
	278	/* Initialize SOC */
a993cb15 AF	279	object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
a993cb15 AF	280	TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
04331d0b MC	281	object_property_set_str(OBJECT(&s->soc), VIRT_CPU, "cpu-type",
	282	&error_abort);
	283	object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
	284	&error_abort);
	285	object_property_set_bool(OBJECT(&s->soc), true, "realized",
	286	&error_abort);
	287
	288	/* register system main memory (actual RAM) */
	289	memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
	290	machine->ram_size, &error_fatal);
	291	memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
	292	main_mem);
	293
	294	/* create device tree */
	295	fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
	296
	297	/* boot rom */
5aec3247 MC	298	memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
	299	memmap[VIRT_MROM].size, &error_fatal);
	300	memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
	301	mask_rom);
04331d0b MC	302
	303	if (machine->kernel_filename) {
	304	uint64_t kernel_entry = load_kernel(machine->kernel_filename);
	305
	306	if (machine->initrd_filename) {
	307	hwaddr start;
	308	hwaddr end = load_initrd(machine->initrd_filename,
	309	machine->ram_size, kernel_entry,
	310	&start);
	311	qemu_fdt_setprop_cell(fdt, "/chosen",
	312	"linux,initrd-start", start);
	313	qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
	314	end);
	315	}
	316	}
	317
	318	/* reset vector */
	319	uint32_t reset_vec[8] = {
	320	0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
	321	0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
	322	0xf1402573, /* csrr a0, mhartid */
	323	#if defined(TARGET_RISCV32)
	324	0x0182a283, /* lw t0, 24(t0) */
	325	#elif defined(TARGET_RISCV64)
	326	0x0182b283, /* ld t0, 24(t0) */
	327	#endif
	328	0x00028067, /* jr t0 */
	329	0x00000000,
	330	memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].base */
	331	0x00000000,
	332	/* dtb: */
	333	};
	334
5aec3247 MC	335	/* copy in the reset vector in little_endian byte order */
	336	for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
	337	reset_vec[i] = cpu_to_le32(reset_vec[i]);
	338	}
	339	rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
	340	memmap[VIRT_MROM].base, &address_space_memory);
04331d0b MC	341
04331d0b MC	342	/* copy in the device tree */
5aec3247 MC	343	if (fdt_pack(s->fdt) \|\| fdt_totalsize(s->fdt) >
	344	memmap[VIRT_MROM].size - sizeof(reset_vec)) {
	345	error_report("not enough space to store device-tree");
	346	exit(1);
	347	}
	348	qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
	349	rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
	350	memmap[VIRT_MROM].base + sizeof(reset_vec),
	351	&address_space_memory);
04331d0b MC	352
	353	/* create PLIC hart topology configuration string */
	354	plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus;
	355	plic_hart_config = g_malloc0(plic_hart_config_len);
	356	for (i = 0; i < smp_cpus; i++) {
	357	if (i != 0) {
	358	strncat(plic_hart_config, ",", plic_hart_config_len);
	359	}
	360	strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG, plic_hart_config_len);
	361	plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
	362	}
	363
	364	/* MMIO */
	365	s->plic = sifive_plic_create(memmap[VIRT_PLIC].base,
	366	plic_hart_config,
	367	VIRT_PLIC_NUM_SOURCES,
	368	VIRT_PLIC_NUM_PRIORITIES,
	369	VIRT_PLIC_PRIORITY_BASE,
	370	VIRT_PLIC_PENDING_BASE,
	371	VIRT_PLIC_ENABLE_BASE,
	372	VIRT_PLIC_ENABLE_STRIDE,
	373	VIRT_PLIC_CONTEXT_BASE,
	374	VIRT_PLIC_CONTEXT_STRIDE,
	375	memmap[VIRT_PLIC].size);
	376	sifive_clint_create(memmap[VIRT_CLINT].base,
	377	memmap[VIRT_CLINT].size, smp_cpus,
	378	SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
	379	sifive_test_create(memmap[VIRT_TEST].base);
	380
	381	for (i = 0; i < VIRTIO_COUNT; i++) {
	382	sysbus_create_simple("virtio-mmio",
	383	memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
647a70a1	384	qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
04331d0b MC	385	}
	386
	387	serial_mm_init(system_memory, memmap[VIRT_UART0].base,
647a70a1	388	0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
9bca0edb	389	serial_hd(0), DEVICE_LITTLE_ENDIAN);
b6aa6ced MC	390
b6aa6ced MC	391	g_free(plic_hart_config);
04331d0b MC	392	}
04331d0b MC	393
04331d0b MC	394	static void riscv_virt_board_machine_init(MachineClass *mc)
04331d0b MC	395	{
77ff5bba	396	mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
04331d0b MC	397	mc->init = riscv_virt_board_init;
	398	mc->max_cpus = 8; /* hardcoded limit in BBL */
	399	}
	400
	401	DEFINE_MACHINE("virt", riscv_virt_board_machine_init)