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639e8102 DG |
1 | /* |
2 | * QEMU sPAPR NVRAM emulation | |
3 | * | |
4 | * Copyright (C) 2012 David Gibson, IBM Corporation. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e2af7a4d | 24 | |
0d75590d | 25 | #include "qemu/osdep.h" |
ab3dd749 | 26 | #include "qemu/units.h" |
da34e65c | 27 | #include "qapi/error.h" |
4771d756 PB |
28 | #include "qemu-common.h" |
29 | #include "cpu.h" | |
639e8102 DG |
30 | #include <libfdt.h> |
31 | ||
4be74634 | 32 | #include "sysemu/block-backend.h" |
9c17d615 | 33 | #include "sysemu/device_tree.h" |
639e8102 | 34 | #include "hw/sysbus.h" |
61f20b9d | 35 | #include "hw/nvram/chrp_nvram.h" |
0d09e41a PB |
36 | #include "hw/ppc/spapr.h" |
37 | #include "hw/ppc/spapr_vio.h" | |
639e8102 DG |
38 | |
39 | typedef struct sPAPRNVRAM { | |
40 | VIOsPAPRDevice sdev; | |
41 | uint32_t size; | |
42 | uint8_t *buf; | |
4be74634 | 43 | BlockBackend *blk; |
cf472f48 | 44 | VMChangeStateEntry *vmstate; |
639e8102 DG |
45 | } sPAPRNVRAM; |
46 | ||
fd506b4f DG |
47 | #define TYPE_VIO_SPAPR_NVRAM "spapr-nvram" |
48 | #define VIO_SPAPR_NVRAM(obj) \ | |
49 | OBJECT_CHECK(sPAPRNVRAM, (obj), TYPE_VIO_SPAPR_NVRAM) | |
50 | ||
ab3dd749 PMD |
51 | #define MIN_NVRAM_SIZE (8 * KiB) |
52 | #define DEFAULT_NVRAM_SIZE (64 * KiB) | |
53 | #define MAX_NVRAM_SIZE (1 * MiB) | |
639e8102 | 54 | |
28e02042 | 55 | static void rtas_nvram_fetch(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
639e8102 DG |
56 | uint32_t token, uint32_t nargs, |
57 | target_ulong args, | |
58 | uint32_t nret, target_ulong rets) | |
59 | { | |
60 | sPAPRNVRAM *nvram = spapr->nvram; | |
61 | hwaddr offset, buffer, len; | |
639e8102 DG |
62 | void *membuf; |
63 | ||
64 | if ((nargs != 3) || (nret != 2)) { | |
a64d325d | 65 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
66 | return; |
67 | } | |
68 | ||
69 | if (!nvram) { | |
a64d325d | 70 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
639e8102 DG |
71 | rtas_st(rets, 1, 0); |
72 | return; | |
73 | } | |
74 | ||
75 | offset = rtas_ld(args, 0); | |
76 | buffer = rtas_ld(args, 1); | |
77 | len = rtas_ld(args, 2); | |
78 | ||
79 | if (((offset + len) < offset) | |
80 | || ((offset + len) > nvram->size)) { | |
a64d325d | 81 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
82 | rtas_st(rets, 1, 0); |
83 | return; | |
84 | } | |
85 | ||
f58aa483 | 86 | assert(nvram->buf); |
639e8102 | 87 | |
f58aa483 AK |
88 | membuf = cpu_physical_memory_map(buffer, &len, 1); |
89 | memcpy(membuf, nvram->buf + offset, len); | |
639e8102 DG |
90 | cpu_physical_memory_unmap(membuf, len, 1, len); |
91 | ||
f58aa483 AK |
92 | rtas_st(rets, 0, RTAS_OUT_SUCCESS); |
93 | rtas_st(rets, 1, len); | |
639e8102 DG |
94 | } |
95 | ||
28e02042 | 96 | static void rtas_nvram_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, |
639e8102 DG |
97 | uint32_t token, uint32_t nargs, |
98 | target_ulong args, | |
99 | uint32_t nret, target_ulong rets) | |
100 | { | |
101 | sPAPRNVRAM *nvram = spapr->nvram; | |
102 | hwaddr offset, buffer, len; | |
103 | int alen; | |
104 | void *membuf; | |
105 | ||
106 | if ((nargs != 3) || (nret != 2)) { | |
a64d325d | 107 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
108 | return; |
109 | } | |
110 | ||
111 | if (!nvram) { | |
a64d325d | 112 | rtas_st(rets, 0, RTAS_OUT_HW_ERROR); |
639e8102 DG |
113 | return; |
114 | } | |
115 | ||
116 | offset = rtas_ld(args, 0); | |
117 | buffer = rtas_ld(args, 1); | |
118 | len = rtas_ld(args, 2); | |
119 | ||
120 | if (((offset + len) < offset) | |
121 | || ((offset + len) > nvram->size)) { | |
a64d325d | 122 | rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); |
639e8102 DG |
123 | return; |
124 | } | |
125 | ||
126 | membuf = cpu_physical_memory_map(buffer, &len, 0); | |
f58aa483 AK |
127 | |
128 | alen = len; | |
4be74634 | 129 | if (nvram->blk) { |
8341f00d | 130 | alen = blk_pwrite(nvram->blk, offset, membuf, len, 0); |
639e8102 | 131 | } |
f58aa483 AK |
132 | |
133 | assert(nvram->buf); | |
134 | memcpy(nvram->buf + offset, membuf, len); | |
135 | ||
639e8102 DG |
136 | cpu_physical_memory_unmap(membuf, len, 0, len); |
137 | ||
a64d325d | 138 | rtas_st(rets, 0, (alen < len) ? RTAS_OUT_HW_ERROR : RTAS_OUT_SUCCESS); |
639e8102 DG |
139 | rtas_st(rets, 1, (alen < 0) ? 0 : alen); |
140 | } | |
141 | ||
28b07e73 | 142 | static void spapr_nvram_realize(VIOsPAPRDevice *dev, Error **errp) |
639e8102 | 143 | { |
fd506b4f | 144 | sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev); |
a17c17a2 | 145 | int ret; |
639e8102 | 146 | |
4be74634 | 147 | if (nvram->blk) { |
05249517 PM |
148 | int64_t len = blk_getlength(nvram->blk); |
149 | ||
150 | if (len < 0) { | |
151 | error_setg_errno(errp, -len, | |
152 | "could not get length of backing image"); | |
153 | return; | |
154 | } | |
155 | ||
156 | nvram->size = len; | |
a17c17a2 KW |
157 | |
158 | ret = blk_set_perm(nvram->blk, | |
159 | BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE, | |
160 | BLK_PERM_ALL, errp); | |
161 | if (ret < 0) { | |
162 | return; | |
163 | } | |
639e8102 DG |
164 | } else { |
165 | nvram->size = DEFAULT_NVRAM_SIZE; | |
639e8102 DG |
166 | } |
167 | ||
f58aa483 AK |
168 | nvram->buf = g_malloc0(nvram->size); |
169 | ||
639e8102 | 170 | if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) { |
ab3dd749 PMD |
171 | error_setg(errp, |
172 | "spapr-nvram must be between %" PRId64 | |
173 | " and %" PRId64 " bytes in size", | |
28b07e73 MA |
174 | MIN_NVRAM_SIZE, MAX_NVRAM_SIZE); |
175 | return; | |
639e8102 DG |
176 | } |
177 | ||
f58aa483 AK |
178 | if (nvram->blk) { |
179 | int alen = blk_pread(nvram->blk, 0, nvram->buf, nvram->size); | |
180 | ||
181 | if (alen != nvram->size) { | |
28b07e73 MA |
182 | error_setg(errp, "can't read spapr-nvram contents"); |
183 | return; | |
f58aa483 | 184 | } |
61f20b9d TH |
185 | } else if (nb_prom_envs > 0) { |
186 | /* Create a system partition to pass the -prom-env variables */ | |
187 | chrp_nvram_create_system_partition(nvram->buf, MIN_NVRAM_SIZE / 4); | |
188 | chrp_nvram_create_free_partition(&nvram->buf[MIN_NVRAM_SIZE / 4], | |
189 | nvram->size - MIN_NVRAM_SIZE / 4); | |
f58aa483 AK |
190 | } |
191 | ||
3a3b8502 AK |
192 | spapr_rtas_register(RTAS_NVRAM_FETCH, "nvram-fetch", rtas_nvram_fetch); |
193 | spapr_rtas_register(RTAS_NVRAM_STORE, "nvram-store", rtas_nvram_store); | |
639e8102 DG |
194 | } |
195 | ||
196 | static int spapr_nvram_devnode(VIOsPAPRDevice *dev, void *fdt, int node_off) | |
197 | { | |
fd506b4f | 198 | sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(dev); |
639e8102 DG |
199 | |
200 | return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size); | |
201 | } | |
202 | ||
f58aa483 AK |
203 | static int spapr_nvram_pre_load(void *opaque) |
204 | { | |
205 | sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(opaque); | |
206 | ||
207 | g_free(nvram->buf); | |
208 | nvram->buf = NULL; | |
209 | nvram->size = 0; | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
cf472f48 | 214 | static void postload_update_cb(void *opaque, int running, RunState state) |
215 | { | |
216 | sPAPRNVRAM *nvram = opaque; | |
217 | ||
218 | /* This is called after bdrv_invalidate_cache_all. */ | |
219 | ||
220 | qemu_del_vm_change_state_handler(nvram->vmstate); | |
221 | nvram->vmstate = NULL; | |
222 | ||
223 | blk_pwrite(nvram->blk, 0, nvram->buf, nvram->size, 0); | |
224 | } | |
225 | ||
f58aa483 AK |
226 | static int spapr_nvram_post_load(void *opaque, int version_id) |
227 | { | |
228 | sPAPRNVRAM *nvram = VIO_SPAPR_NVRAM(opaque); | |
229 | ||
230 | if (nvram->blk) { | |
cf472f48 | 231 | nvram->vmstate = qemu_add_vm_change_state_handler(postload_update_cb, |
232 | nvram); | |
f58aa483 AK |
233 | } |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
238 | static const VMStateDescription vmstate_spapr_nvram = { | |
239 | .name = "spapr_nvram", | |
240 | .version_id = 1, | |
241 | .minimum_version_id = 1, | |
242 | .pre_load = spapr_nvram_pre_load, | |
243 | .post_load = spapr_nvram_post_load, | |
244 | .fields = (VMStateField[]) { | |
245 | VMSTATE_UINT32(size, sPAPRNVRAM), | |
59046ec2 | 246 | VMSTATE_VBUFFER_ALLOC_UINT32(buf, sPAPRNVRAM, 1, NULL, size), |
f58aa483 AK |
247 | VMSTATE_END_OF_LIST() |
248 | }, | |
249 | }; | |
250 | ||
639e8102 DG |
251 | static Property spapr_nvram_properties[] = { |
252 | DEFINE_SPAPR_PROPERTIES(sPAPRNVRAM, sdev), | |
4be74634 | 253 | DEFINE_PROP_DRIVE("drive", sPAPRNVRAM, blk), |
639e8102 DG |
254 | DEFINE_PROP_END_OF_LIST(), |
255 | }; | |
256 | ||
257 | static void spapr_nvram_class_init(ObjectClass *klass, void *data) | |
258 | { | |
259 | DeviceClass *dc = DEVICE_CLASS(klass); | |
260 | VIOsPAPRDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass); | |
261 | ||
28b07e73 | 262 | k->realize = spapr_nvram_realize; |
639e8102 DG |
263 | k->devnode = spapr_nvram_devnode; |
264 | k->dt_name = "nvram"; | |
265 | k->dt_type = "nvram"; | |
266 | k->dt_compatible = "qemu,spapr-nvram"; | |
29fdedfe | 267 | set_bit(DEVICE_CATEGORY_MISC, dc->categories); |
639e8102 | 268 | dc->props = spapr_nvram_properties; |
f58aa483 | 269 | dc->vmsd = &vmstate_spapr_nvram; |
280503ee TH |
270 | /* Reason: Internal device only, uses spapr_rtas_register() in realize() */ |
271 | dc->user_creatable = false; | |
639e8102 DG |
272 | } |
273 | ||
274 | static const TypeInfo spapr_nvram_type_info = { | |
fd506b4f | 275 | .name = TYPE_VIO_SPAPR_NVRAM, |
639e8102 DG |
276 | .parent = TYPE_VIO_SPAPR_DEVICE, |
277 | .instance_size = sizeof(sPAPRNVRAM), | |
278 | .class_init = spapr_nvram_class_init, | |
279 | }; | |
280 | ||
281 | static void spapr_nvram_register_types(void) | |
282 | { | |
283 | type_register_static(&spapr_nvram_type_info); | |
284 | } | |
285 | ||
286 | type_init(spapr_nvram_register_types) |