projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 951cd00e JCD |
1 | /* |
| 2 | * i.MX EPIT Timer | |
| 3 | * | |
| 4 | * Copyright (c) 2008 OK Labs | |
| 5 | * Copyright (c) 2011 NICTA Pty Ltd | |
| 6 | * Originally written by Hans Jiang | |
| 7 | * Updated by Peter Chubb | |
| 8 | * Updated by Jean-Christophe Dubois <[email protected]> | |
| 9 | * | |
| 10 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
| 11 | * of this software and associated documentation files (the "Software"), to deal | |
| 12 | * in the Software without restriction, including without limitation the rights | |
| 13 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
| 14 | * copies of the Software, and to permit persons to whom the Software is | |
| 15 | * furnished to do so, subject to the following conditions: | |
| 16 | * | |
| 17 | * The above copyright notice and this permission notice shall be included in | |
| 18 | * all copies or substantial portions of the Software. | |
| 19 | * | |
| 20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 23 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
| 24 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
| 25 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
| 26 | * THE SOFTWARE. | |
| 27 | */ | |
| 28 | ||
| 29 | #ifndef IMX_EPIT_H | |
| 30 | #define IMX_EPIT_H | |
| 31 | ||
| 32 | #include "hw/sysbus.h" | |
| 33 | #include "hw/ptimer.h" | |
| cb54d868 | 34 | #include "hw/misc/imx_ccm.h" |
| db1015e9 | 35 | #include "qom/object.h" |
| 951cd00e JCD |
36 | |
| 37 | /* | |
| 38 | * EPIT: Enhanced periodic interrupt timer | |
| 39 | */ | |
| 40 | ||
| 41 | #define CR_EN (1 << 0) | |
| 42 | #define CR_ENMOD (1 << 1) | |
| 43 | #define CR_OCIEN (1 << 2) | |
| 44 | #define CR_RLD (1 << 3) | |
| 45 | #define CR_PRESCALE_SHIFT (4) | |
| 46 | #define CR_PRESCALE_MASK (0xfff) | |
| 47 | #define CR_SWR (1 << 16) | |
| 48 | #define CR_IOVW (1 << 17) | |
| 49 | #define CR_DBGEN (1 << 18) | |
| 50 | #define CR_WAITEN (1 << 19) | |
| 51 | #define CR_DOZEN (1 << 20) | |
| 52 | #define CR_STOPEN (1 << 21) | |
| 53 | #define CR_CLKSRC_SHIFT (24) | |
| 54 | #define CR_CLKSRC_MASK (0x3 << CR_CLKSRC_SHIFT) | |
| 55 | ||
| 56 | #define EPIT_TIMER_MAX 0XFFFFFFFFUL | |
| 57 | ||
| 58 | #define TYPE_IMX_EPIT "imx.epit" | |
| 8063396b | 59 | OBJECT_DECLARE_SIMPLE_TYPE(IMXEPITState, IMX_EPIT) |
| 951cd00e | 60 | |
| db1015e9 | 61 | struct IMXEPITState { |
| 951cd00e JCD |
62 | /*< private >*/ |
| 63 | SysBusDevice parent_obj; | |
| 64 | ||
| 65 | /*< public >*/ | |
| 66 | ptimer_state *timer_reload; | |
| 67 | ptimer_state *timer_cmp; | |
| cb54d868 JCD |
68 | MemoryRegion iomem; |
| 69 | IMXCCMState *ccm; | |
| 951cd00e JCD |
70 | |
| 71 | uint32_t cr; | |
| 72 | uint32_t sr; | |
| 73 | uint32_t lr; | |
| 74 | uint32_t cmp; | |
| 75 | uint32_t cnt; | |
| 76 | ||
| 77 | uint32_t freq; | |
| 78 | qemu_irq irq; | |
| db1015e9 | 79 | }; |
| 951cd00e JCD |
80 | |
| 81 | #endif /* IMX_EPIT_H */ |