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NIC emulation for qemu arm-softmmu (Paul Brook)
[qemu.git] / target-arm / translate.c
CommitLineData
2c0262af
FB		 1/*
2 * ARM translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
b7bcbe95 5 * Copyright (c) 2005 CodeSourcery, LLC
2c0262af
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <stdarg.h>
22#include <stdlib.h>
23#include <stdio.h>
24#include <string.h>
25#include <inttypes.h>
26
27#include "cpu.h"
28#include "exec-all.h"
29#include "disas.h"
30
b5ff1b31
FB		 31#define ENABLE_ARCH_5J 0
32#define ENABLE_ARCH_6 1
33#define ENABLE_ARCH_6T2 1
34
35#define ARCH(x) if (!ENABLE_ARCH_##x) goto illegal_op;
36
2c0262af
FB		 37/* internal defines */
38typedef struct DisasContext {
0fa85d43 39 target_ulong pc;
2c0262af 40 int is_jmp;
e50e6a20
FB		 41 /* Nonzero if this instruction has been conditionally skipped. */
42 int condjmp;
43 /* The label that will be jumped to when the instruction is skipped. */
44 int condlabel;
2c0262af 45 struct TranslationBlock *tb;
8aaca4c0 46 int singlestep_enabled;
5899f386 47 int thumb;
b5ff1b31
FB		 48#if !defined(CONFIG_USER_ONLY)
49 int user;
50#endif
2c0262af
FB		 51} DisasContext;
52
b5ff1b31
FB		 53#if defined(CONFIG_USER_ONLY)
54#define IS_USER(s) 1
55#else
56#define IS_USER(s) (s->user)
57#endif
58
2c0262af
FB		 59#define DISAS_JUMP_NEXT 4
60
c53be334
FB		 61#ifdef USE_DIRECT_JUMP
62#define TBPARAM(x)
63#else
64#define TBPARAM(x) (long)(x)
65#endif
66
2c0262af
FB		 67/* XXX: move that elsewhere */
68static uint16_t *gen_opc_ptr;
69static uint32_t *gen_opparam_ptr;
70extern FILE *logfile;
71extern int loglevel;
72
73enum {
74#define DEF(s, n, copy_size) INDEX_op_ ## s,
75#include "opc.h"
76#undef DEF
77 NB_OPS,
78};
79
80#include "gen-op.h"
81
e50e6a20 82static GenOpFunc1 *gen_test_cc[14] = {
2c0262af
FB		 83 gen_op_test_eq,
84 gen_op_test_ne,
85 gen_op_test_cs,
86 gen_op_test_cc,
87 gen_op_test_mi,
88 gen_op_test_pl,
89 gen_op_test_vs,
90 gen_op_test_vc,
91 gen_op_test_hi,
92 gen_op_test_ls,
93 gen_op_test_ge,
94 gen_op_test_lt,
95 gen_op_test_gt,
96 gen_op_test_le,
97};
98
99const uint8_t table_logic_cc[16] = {
100 1, /* and */
101 1, /* xor */
102 0, /* sub */
103 0, /* rsb */
104 0, /* add */
105 0, /* adc */
106 0, /* sbc */
107 0, /* rsc */
108 1, /* andl */
109 1, /* xorl */
110 0, /* cmp */
111 0, /* cmn */
112 1, /* orr */
113 1, /* mov */
114 1, /* bic */
115 1, /* mvn */
116};
117
118static GenOpFunc1 *gen_shift_T1_im[4] = {
119 gen_op_shll_T1_im,
120 gen_op_shrl_T1_im,
121 gen_op_sarl_T1_im,
122 gen_op_rorl_T1_im,
123};
124
1e8d4eec
FB		 125static GenOpFunc *gen_shift_T1_0[4] = {
126 NULL,
127 gen_op_shrl_T1_0,
128 gen_op_sarl_T1_0,
129 gen_op_rrxl_T1,
130};
131
2c0262af
FB		 132static GenOpFunc1 *gen_shift_T2_im[4] = {
133 gen_op_shll_T2_im,
134 gen_op_shrl_T2_im,
135 gen_op_sarl_T2_im,
136 gen_op_rorl_T2_im,
137};
138
1e8d4eec
FB		 139static GenOpFunc *gen_shift_T2_0[4] = {
140 NULL,
141 gen_op_shrl_T2_0,
142 gen_op_sarl_T2_0,
143 gen_op_rrxl_T2,
144};
145
2c0262af
FB		 146static GenOpFunc1 *gen_shift_T1_im_cc[4] = {
147 gen_op_shll_T1_im_cc,
148 gen_op_shrl_T1_im_cc,
149 gen_op_sarl_T1_im_cc,
150 gen_op_rorl_T1_im_cc,
151};
152
1e8d4eec
FB		 153static GenOpFunc *gen_shift_T1_0_cc[4] = {
154 NULL,
155 gen_op_shrl_T1_0_cc,
156 gen_op_sarl_T1_0_cc,
157 gen_op_rrxl_T1_cc,
158};
159
2c0262af
FB		 160static GenOpFunc *gen_shift_T1_T0[4] = {
161 gen_op_shll_T1_T0,
162 gen_op_shrl_T1_T0,
163 gen_op_sarl_T1_T0,
164 gen_op_rorl_T1_T0,
165};
166
167static GenOpFunc *gen_shift_T1_T0_cc[4] = {
168 gen_op_shll_T1_T0_cc,
169 gen_op_shrl_T1_T0_cc,
170 gen_op_sarl_T1_T0_cc,
171 gen_op_rorl_T1_T0_cc,
172};
173
174static GenOpFunc *gen_op_movl_TN_reg[3][16] = {
175 {
176 gen_op_movl_T0_r0,
177 gen_op_movl_T0_r1,
178 gen_op_movl_T0_r2,
179 gen_op_movl_T0_r3,
180 gen_op_movl_T0_r4,
181 gen_op_movl_T0_r5,
182 gen_op_movl_T0_r6,
183 gen_op_movl_T0_r7,
184 gen_op_movl_T0_r8,
185 gen_op_movl_T0_r9,
186 gen_op_movl_T0_r10,
187 gen_op_movl_T0_r11,
188 gen_op_movl_T0_r12,
189 gen_op_movl_T0_r13,
190 gen_op_movl_T0_r14,
191 gen_op_movl_T0_r15,
192 },
193 {
194 gen_op_movl_T1_r0,
195 gen_op_movl_T1_r1,
196 gen_op_movl_T1_r2,
197 gen_op_movl_T1_r3,
198 gen_op_movl_T1_r4,
199 gen_op_movl_T1_r5,
200 gen_op_movl_T1_r6,
201 gen_op_movl_T1_r7,
202 gen_op_movl_T1_r8,
203 gen_op_movl_T1_r9,
204 gen_op_movl_T1_r10,
205 gen_op_movl_T1_r11,
206 gen_op_movl_T1_r12,
207 gen_op_movl_T1_r13,
208 gen_op_movl_T1_r14,
209 gen_op_movl_T1_r15,
210 },
211 {
212 gen_op_movl_T2_r0,
213 gen_op_movl_T2_r1,
214 gen_op_movl_T2_r2,
215 gen_op_movl_T2_r3,
216 gen_op_movl_T2_r4,
217 gen_op_movl_T2_r5,
218 gen_op_movl_T2_r6,
219 gen_op_movl_T2_r7,
220 gen_op_movl_T2_r8,
221 gen_op_movl_T2_r9,
222 gen_op_movl_T2_r10,
223 gen_op_movl_T2_r11,
224 gen_op_movl_T2_r12,
225 gen_op_movl_T2_r13,
226 gen_op_movl_T2_r14,
227 gen_op_movl_T2_r15,
228 },
229};
230
231static GenOpFunc *gen_op_movl_reg_TN[2][16] = {
232 {
233 gen_op_movl_r0_T0,
234 gen_op_movl_r1_T0,
235 gen_op_movl_r2_T0,
236 gen_op_movl_r3_T0,
237 gen_op_movl_r4_T0,
238 gen_op_movl_r5_T0,
239 gen_op_movl_r6_T0,
240 gen_op_movl_r7_T0,
241 gen_op_movl_r8_T0,
242 gen_op_movl_r9_T0,
243 gen_op_movl_r10_T0,
244 gen_op_movl_r11_T0,
245 gen_op_movl_r12_T0,
246 gen_op_movl_r13_T0,
247 gen_op_movl_r14_T0,
248 gen_op_movl_r15_T0,
249 },
250 {
251 gen_op_movl_r0_T1,
252 gen_op_movl_r1_T1,
253 gen_op_movl_r2_T1,
254 gen_op_movl_r3_T1,
255 gen_op_movl_r4_T1,
256 gen_op_movl_r5_T1,
257 gen_op_movl_r6_T1,
258 gen_op_movl_r7_T1,
259 gen_op_movl_r8_T1,
260 gen_op_movl_r9_T1,
261 gen_op_movl_r10_T1,
262 gen_op_movl_r11_T1,
263 gen_op_movl_r12_T1,
264 gen_op_movl_r13_T1,
265 gen_op_movl_r14_T1,
266 gen_op_movl_r15_T1,
267 },
268};
269
270static GenOpFunc1 *gen_op_movl_TN_im[3] = {
271 gen_op_movl_T0_im,
272 gen_op_movl_T1_im,
273 gen_op_movl_T2_im,
274};
275
99c475ab
FB		 276static GenOpFunc1 *gen_shift_T0_im_thumb[3] = {
277 gen_op_shll_T0_im_thumb,
278 gen_op_shrl_T0_im_thumb,
279 gen_op_sarl_T0_im_thumb,
280};
281
282static inline void gen_bx(DisasContext *s)
283{
284 s->is_jmp = DISAS_UPDATE;
285 gen_op_bx_T0();
286}
287
b5ff1b31
FB		 288
289#if defined(CONFIG_USER_ONLY)
290#define gen_ldst(name, s) gen_op_##name##_raw()
291#else
292#define gen_ldst(name, s) do { \
293 if (IS_USER(s)) \
294 gen_op_##name##_user(); \
295 else \
296 gen_op_##name##_kernel(); \
297 } while (0)
298#endif
299
2c0262af
FB		 300static inline void gen_movl_TN_reg(DisasContext *s, int reg, int t)
301{
302 int val;
303
304 if (reg == 15) {
5899f386
FB		 305 /* normaly, since we updated PC, we need only to add one insn */
306 if (s->thumb)
307 val = (long)s->pc + 2;
308 else
309 val = (long)s->pc + 4;
2c0262af
FB		 310 gen_op_movl_TN_im[t](val);
311 } else {
312 gen_op_movl_TN_reg[t][reg]();
313 }
314}
315
316static inline void gen_movl_T0_reg(DisasContext *s, int reg)
317{
318 gen_movl_TN_reg(s, reg, 0);
319}
320
321static inline void gen_movl_T1_reg(DisasContext *s, int reg)
322{
323 gen_movl_TN_reg(s, reg, 1);
324}
325
326static inline void gen_movl_T2_reg(DisasContext *s, int reg)
327{
328 gen_movl_TN_reg(s, reg, 2);
329}
330
331static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t)
332{
333 gen_op_movl_reg_TN[t][reg]();
334 if (reg == 15) {
335 s->is_jmp = DISAS_JUMP;
336 }
337}
338
339static inline void gen_movl_reg_T0(DisasContext *s, int reg)
340{
341 gen_movl_reg_TN(s, reg, 0);
342}
343
344static inline void gen_movl_reg_T1(DisasContext *s, int reg)
345{
346 gen_movl_reg_TN(s, reg, 1);
347}
348
b5ff1b31
FB		 349/* Force a TB lookup after an instruction that changes the CPU state. */
350static inline void gen_lookup_tb(DisasContext *s)
351{
352 gen_op_movl_T0_im(s->pc);
353 gen_movl_reg_T0(s, 15);
354 s->is_jmp = DISAS_UPDATE;
355}
356
2c0262af
FB		 357static inline void gen_add_data_offset(DisasContext *s, unsigned int insn)
358{
1e8d4eec 359 int val, rm, shift, shiftop;
2c0262af
FB		 360
361 if (!(insn & (1 << 25))) {
362 /* immediate */
363 val = insn & 0xfff;
364 if (!(insn & (1 << 23)))
365 val = -val;
537730b9
FB		 366 if (val != 0)
367 gen_op_addl_T1_im(val);
2c0262af
FB		 368 } else {
369 /* shift/register */
370 rm = (insn) & 0xf;
371 shift = (insn >> 7) & 0x1f;
372 gen_movl_T2_reg(s, rm);
1e8d4eec 373 shiftop = (insn >> 5) & 3;
2c0262af 374 if (shift != 0) {
1e8d4eec
FB		 375 gen_shift_T2_im[shiftop](shift);
376 } else if (shiftop != 0) {
377 gen_shift_T2_0[shiftop]();
2c0262af
FB		 378 }
379 if (!(insn & (1 << 23)))
380 gen_op_subl_T1_T2();
381 else
382 gen_op_addl_T1_T2();
383 }
384}
385
386static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn)
387{
388 int val, rm;
389
390 if (insn & (1 << 22)) {
391 /* immediate */
392 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
393 if (!(insn & (1 << 23)))
394 val = -val;
537730b9
FB		 395 if (val != 0)
396 gen_op_addl_T1_im(val);
2c0262af
FB		 397 } else {
398 /* register */
399 rm = (insn) & 0xf;
400 gen_movl_T2_reg(s, rm);
401 if (!(insn & (1 << 23)))
402 gen_op_subl_T1_T2();
403 else
404 gen_op_addl_T1_T2();
405 }
406}
407
b7bcbe95
FB		 408#define VFP_OP(name) \
409static inline void gen_vfp_##name(int dp) \
410{ \
411 if (dp) \
412 gen_op_vfp_##name##d(); \
413 else \
414 gen_op_vfp_##name##s(); \
415}
416
417VFP_OP(add)
418VFP_OP(sub)
419VFP_OP(mul)
420VFP_OP(div)
421VFP_OP(neg)
422VFP_OP(abs)
423VFP_OP(sqrt)
424VFP_OP(cmp)
425VFP_OP(cmpe)
426VFP_OP(F1_ld0)
427VFP_OP(uito)
428VFP_OP(sito)
429VFP_OP(toui)
430VFP_OP(touiz)
431VFP_OP(tosi)
432VFP_OP(tosiz)
b7bcbe95
FB		 433
434#undef VFP_OP
435
b5ff1b31
FB		 436static inline void gen_vfp_ld(DisasContext *s, int dp)
437{
438 if (dp)
439 gen_ldst(vfp_ldd, s);
440 else
441 gen_ldst(vfp_lds, s);
442}
443
444static inline void gen_vfp_st(DisasContext *s, int dp)
445{
446 if (dp)
447 gen_ldst(vfp_std, s);
448 else
449 gen_ldst(vfp_sts, s);
450}
451
8e96005d
FB		 452static inline long
453vfp_reg_offset (int dp, int reg)
454{
455 if (dp)
456 return offsetof(CPUARMState, vfp.regs[reg]);
457 else if (reg & 1) {
458 return offsetof(CPUARMState, vfp.regs[reg >> 1])
459 + offsetof(CPU_DoubleU, l.upper);
460 } else {
461 return offsetof(CPUARMState, vfp.regs[reg >> 1])
462 + offsetof(CPU_DoubleU, l.lower);
463 }
464}
b7bcbe95
FB		 465static inline void gen_mov_F0_vreg(int dp, int reg)
466{
467 if (dp)
8e96005d 468 gen_op_vfp_getreg_F0d(vfp_reg_offset(dp, reg));
b7bcbe95 469 else
8e96005d 470 gen_op_vfp_getreg_F0s(vfp_reg_offset(dp, reg));
b7bcbe95
FB		 471}
472
473static inline void gen_mov_F1_vreg(int dp, int reg)
474{
475 if (dp)
8e96005d 476 gen_op_vfp_getreg_F1d(vfp_reg_offset(dp, reg));
b7bcbe95 477 else
8e96005d 478 gen_op_vfp_getreg_F1s(vfp_reg_offset(dp, reg));
b7bcbe95
FB		 479}
480
481static inline void gen_mov_vreg_F0(int dp, int reg)
482{
483 if (dp)
8e96005d 484 gen_op_vfp_setreg_F0d(vfp_reg_offset(dp, reg));
b7bcbe95 485 else
8e96005d 486 gen_op_vfp_setreg_F0s(vfp_reg_offset(dp, reg));
b7bcbe95
FB		 487}
488
b5ff1b31
FB		 489/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
490 instruction is not defined. */
491static int disas_cp15_insn(DisasContext *s, uint32_t insn)
492{
493 uint32_t rd;
494
495 /* ??? Some cp15 registers are accessible from userspace. */
496 if (IS_USER(s)) {
497 return 1;
498 }
9332f9da
FB		 499 if ((insn & 0x0fff0fff) == 0x0e070f90
500 || (insn & 0x0fff0fff) == 0x0e070f58) {
501 /* Wait for interrupt. */
502 gen_op_movl_T0_im((long)s->pc);
503 gen_op_movl_reg_TN[0][15]();
504 gen_op_wfi();
505 s->is_jmp = DISAS_JUMP;
506 return 0;
507 }
b5ff1b31
FB		 508 rd = (insn >> 12) & 0xf;
509 if (insn & (1 << 20)) {
510 gen_op_movl_T0_cp15(insn);
511 /* If the destination register is r15 then sets condition codes. */
512 if (rd != 15)
513 gen_movl_reg_T0(s, rd);
514 } else {
515 gen_movl_T0_reg(s, rd);
516 gen_op_movl_cp15_T0(insn);
517 }
518 gen_lookup_tb(s);
519 return 0;
520}
521
b7bcbe95
FB		 522/* Disassemble a VFP instruction. Returns nonzero if an error occured
523 (ie. an undefined instruction). */
524static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
525{
526 uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
527 int dp, veclen;
528
529 dp = ((insn & 0xf00) == 0xb00);
530 switch ((insn >> 24) & 0xf) {
531 case 0xe:
532 if (insn & (1 << 4)) {
533 /* single register transfer */
534 if ((insn & 0x6f) != 0x00)
535 return 1;
536 rd = (insn >> 12) & 0xf;
537 if (dp) {
538 if (insn & 0x80)
539 return 1;
540 rn = (insn >> 16) & 0xf;
541 /* Get the existing value even for arm->vfp moves because
542 we only set half the register. */
543 gen_mov_F0_vreg(1, rn);
544 gen_op_vfp_mrrd();
545 if (insn & (1 << 20)) {
546 /* vfp->arm */
547 if (insn & (1 << 21))
548 gen_movl_reg_T1(s, rd);
549 else
550 gen_movl_reg_T0(s, rd);
551 } else {
552 /* arm->vfp */
553 if (insn & (1 << 21))
554 gen_movl_T1_reg(s, rd);
555 else
556 gen_movl_T0_reg(s, rd);
557 gen_op_vfp_mdrr();
558 gen_mov_vreg_F0(dp, rn);
559 }
560 } else {
561 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
562 if (insn & (1 << 20)) {
563 /* vfp->arm */
564 if (insn & (1 << 21)) {
565 /* system register */
566 switch (rn) {
567 case 0: /* fpsid */
568 n = 0x0091A0000;
569 break;
570 case 2: /* fpscr */
571 if (rd == 15)
572 gen_op_vfp_movl_T0_fpscr_flags();
573 else
574 gen_op_vfp_movl_T0_fpscr();
575 break;
576 default:
577 return 1;
578 }
579 } else {
580 gen_mov_F0_vreg(0, rn);
581 gen_op_vfp_mrs();
582 }
583 if (rd == 15) {
b5ff1b31
FB		 584 /* Set the 4 flag bits in the CPSR. */
585 gen_op_movl_cpsr_T0(0xf0000000);
b7bcbe95
FB		 586 } else
587 gen_movl_reg_T0(s, rd);
588 } else {
589 /* arm->vfp */
590 gen_movl_T0_reg(s, rd);
591 if (insn & (1 << 21)) {
592 /* system register */
593 switch (rn) {
594 case 0: /* fpsid */
595 /* Writes are ignored. */
596 break;
597 case 2: /* fpscr */
598 gen_op_vfp_movl_fpscr_T0();
599 /* This could change vector settings, so jump to
600 the next instuction. */
b5ff1b31 601 gen_lookup_tb(s);
b7bcbe95
FB		 602 break;
603 default:
604 return 1;
605 }
606 } else {
607 gen_op_vfp_msr();
608 gen_mov_vreg_F0(0, rn);
609 }
610 }
611 }
612 } else {
613 /* data processing */
614 /* The opcode is in bits 23, 21, 20 and 6. */
615 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
616 if (dp) {
617 if (op == 15) {
618 /* rn is opcode */
619 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
620 } else {
621 /* rn is register number */
622 if (insn & (1 << 7))
623 return 1;
624 rn = (insn >> 16) & 0xf;
625 }
626
627 if (op == 15 && (rn == 15 || rn > 17)) {
628 /* Integer or single precision destination. */
629 rd = ((insn >> 11) & 0x1e) | ((insn >> 22) & 1);
630 } else {
631 if (insn & (1 << 22))
632 return 1;
633 rd = (insn >> 12) & 0xf;
634 }
635
636 if (op == 15 && (rn == 16 || rn == 17)) {
637 /* Integer source. */
638 rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1);
639 } else {
640 if (insn & (1 << 5))
641 return 1;
642 rm = insn & 0xf;
643 }
644 } else {
645 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
646 if (op == 15 && rn == 15) {
647 /* Double precision destination. */
648 if (insn & (1 << 22))
649 return 1;
650 rd = (insn >> 12) & 0xf;
651 } else
652 rd = ((insn >> 11) & 0x1e) | ((insn >> 22) & 1);
653 rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1);
654 }
655
656 veclen = env->vfp.vec_len;
657 if (op == 15 && rn > 3)
658 veclen = 0;
659
660 /* Shut up compiler warnings. */
661 delta_m = 0;
662 delta_d = 0;
663 bank_mask = 0;
664
665 if (veclen > 0) {
666 if (dp)
667 bank_mask = 0xc;
668 else
669 bank_mask = 0x18;
670
671 /* Figure out what type of vector operation this is. */
672 if ((rd & bank_mask) == 0) {
673 /* scalar */
674 veclen = 0;
675 } else {
676 if (dp)
677 delta_d = (env->vfp.vec_stride >> 1) + 1;
678 else
679 delta_d = env->vfp.vec_stride + 1;
680
681 if ((rm & bank_mask) == 0) {
682 /* mixed scalar/vector */
683 delta_m = 0;
684 } else {
685 /* vector */
686 delta_m = delta_d;
687 }
688 }
689 }
690
691 /* Load the initial operands. */
692 if (op == 15) {
693 switch (rn) {
694 case 16:
695 case 17:
696 /* Integer source */
697 gen_mov_F0_vreg(0, rm);
698 break;
699 case 8:
700 case 9:
701 /* Compare */
702 gen_mov_F0_vreg(dp, rd);
703 gen_mov_F1_vreg(dp, rm);
704 break;
705 case 10:
706 case 11:
707 /* Compare with zero */
708 gen_mov_F0_vreg(dp, rd);
709 gen_vfp_F1_ld0(dp);
710 break;
711 default:
712 /* One source operand. */
713 gen_mov_F0_vreg(dp, rm);
714 }
715 } else {
716 /* Two source operands. */
717 gen_mov_F0_vreg(dp, rn);
718 gen_mov_F1_vreg(dp, rm);
719 }
720
721 for (;;) {
722 /* Perform the calculation. */
723 switch (op) {
724 case 0: /* mac: fd + (fn * fm) */
725 gen_vfp_mul(dp);
726 gen_mov_F1_vreg(dp, rd);
727 gen_vfp_add(dp);
728 break;
729 case 1: /* nmac: fd - (fn * fm) */
730 gen_vfp_mul(dp);
731 gen_vfp_neg(dp);
732 gen_mov_F1_vreg(dp, rd);
733 gen_vfp_add(dp);
734 break;
735 case 2: /* msc: -fd + (fn * fm) */
736 gen_vfp_mul(dp);
737 gen_mov_F1_vreg(dp, rd);
738 gen_vfp_sub(dp);
739 break;
740 case 3: /* nmsc: -fd - (fn * fm) */
741 gen_vfp_mul(dp);
742 gen_mov_F1_vreg(dp, rd);
743 gen_vfp_add(dp);
744 gen_vfp_neg(dp);
745 break;
746 case 4: /* mul: fn * fm */
747 gen_vfp_mul(dp);
748 break;
749 case 5: /* nmul: -(fn * fm) */
750 gen_vfp_mul(dp);
751 gen_vfp_neg(dp);
752 break;
753 case 6: /* add: fn + fm */
754 gen_vfp_add(dp);
755 break;
756 case 7: /* sub: fn - fm */
757 gen_vfp_sub(dp);
758 break;
759 case 8: /* div: fn / fm */
760 gen_vfp_div(dp);
761 break;
762 case 15: /* extension space */
763 switch (rn) {
764 case 0: /* cpy */
765 /* no-op */
766 break;
767 case 1: /* abs */
768 gen_vfp_abs(dp);
769 break;
770 case 2: /* neg */
771 gen_vfp_neg(dp);
772 break;
773 case 3: /* sqrt */
774 gen_vfp_sqrt(dp);
775 break;
776 case 8: /* cmp */
777 gen_vfp_cmp(dp);
778 break;
779 case 9: /* cmpe */
780 gen_vfp_cmpe(dp);
781 break;
782 case 10: /* cmpz */
783 gen_vfp_cmp(dp);
784 break;
785 case 11: /* cmpez */
786 gen_vfp_F1_ld0(dp);
787 gen_vfp_cmpe(dp);
788 break;
789 case 15: /* single<->double conversion */
790 if (dp)
791 gen_op_vfp_fcvtsd();
792 else
793 gen_op_vfp_fcvtds();
794 break;
795 case 16: /* fuito */
796 gen_vfp_uito(dp);
797 break;
798 case 17: /* fsito */
799 gen_vfp_sito(dp);
800 break;
801 case 24: /* ftoui */
802 gen_vfp_toui(dp);
803 break;
804 case 25: /* ftouiz */
805 gen_vfp_touiz(dp);
806 break;
807 case 26: /* ftosi */
808 gen_vfp_tosi(dp);
809 break;
810 case 27: /* ftosiz */
811 gen_vfp_tosiz(dp);
812 break;
813 default: /* undefined */
814 printf ("rn:%d\n", rn);
815 return 1;
816 }
817 break;
818 default: /* undefined */
819 printf ("op:%d\n", op);
820 return 1;
821 }
822
823 /* Write back the result. */
824 if (op == 15 && (rn >= 8 && rn <= 11))
825 ; /* Comparison, do nothing. */
826 else if (op == 15 && rn > 17)
827 /* Integer result. */
828 gen_mov_vreg_F0(0, rd);
829 else if (op == 15 && rn == 15)
830 /* conversion */
831 gen_mov_vreg_F0(!dp, rd);
832 else
833 gen_mov_vreg_F0(dp, rd);
834
835 /* break out of the loop if we have finished */
836 if (veclen == 0)
837 break;
838
839 if (op == 15 && delta_m == 0) {
840 /* single source one-many */
841 while (veclen--) {
842 rd = ((rd + delta_d) & (bank_mask - 1))
843 | (rd & bank_mask);
844 gen_mov_vreg_F0(dp, rd);
845 }
846 break;
847 }
848 /* Setup the next operands. */
849 veclen--;
850 rd = ((rd + delta_d) & (bank_mask - 1))
851 | (rd & bank_mask);
852
853 if (op == 15) {
854 /* One source operand. */
855 rm = ((rm + delta_m) & (bank_mask - 1))
856 | (rm & bank_mask);
857 gen_mov_F0_vreg(dp, rm);
858 } else {
859 /* Two source operands. */
860 rn = ((rn + delta_d) & (bank_mask - 1))
861 | (rn & bank_mask);
862 gen_mov_F0_vreg(dp, rn);
863 if (delta_m) {
864 rm = ((rm + delta_m) & (bank_mask - 1))
865 | (rm & bank_mask);
866 gen_mov_F1_vreg(dp, rm);
867 }
868 }
869 }
870 }
871 break;
872 case 0xc:
873 case 0xd:
874 if (dp && (insn & (1 << 22))) {
875 /* two-register transfer */
876 rn = (insn >> 16) & 0xf;
877 rd = (insn >> 12) & 0xf;
878 if (dp) {
879 if (insn & (1 << 5))
880 return 1;
881 rm = insn & 0xf;
882 } else
883 rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1);
884
885 if (insn & (1 << 20)) {
886 /* vfp->arm */
887 if (dp) {
888 gen_mov_F0_vreg(1, rm);
889 gen_op_vfp_mrrd();
890 gen_movl_reg_T0(s, rd);
891 gen_movl_reg_T1(s, rn);
892 } else {
893 gen_mov_F0_vreg(0, rm);
894 gen_op_vfp_mrs();
895 gen_movl_reg_T0(s, rn);
896 gen_mov_F0_vreg(0, rm + 1);
897 gen_op_vfp_mrs();
898 gen_movl_reg_T0(s, rd);
899 }
900 } else {
901 /* arm->vfp */
902 if (dp) {
903 gen_movl_T0_reg(s, rd);
904 gen_movl_T1_reg(s, rn);
905 gen_op_vfp_mdrr();
906 gen_mov_vreg_F0(1, rm);
907 } else {
908 gen_movl_T0_reg(s, rn);
909 gen_op_vfp_msr();
910 gen_mov_vreg_F0(0, rm);
911 gen_movl_T0_reg(s, rd);
912 gen_op_vfp_msr();
913 gen_mov_vreg_F0(0, rm + 1);
914 }
915 }
916 } else {
917 /* Load/store */
918 rn = (insn >> 16) & 0xf;
919 if (dp)
920 rd = (insn >> 12) & 0xf;
921 else
922 rd = ((insn >> 11) & 0x1e) | ((insn >> 22) & 1);
923 gen_movl_T1_reg(s, rn);
924 if ((insn & 0x01200000) == 0x01000000) {
925 /* Single load/store */
926 offset = (insn & 0xff) << 2;
927 if ((insn & (1 << 23)) == 0)
928 offset = -offset;
929 gen_op_addl_T1_im(offset);
930 if (insn & (1 << 20)) {
b5ff1b31 931 gen_vfp_ld(s, dp);
b7bcbe95
FB		 932 gen_mov_vreg_F0(dp, rd);
933 } else {
934 gen_mov_F0_vreg(dp, rd);
b5ff1b31 935 gen_vfp_st(s, dp);
b7bcbe95
FB		 936 }
937 } else {
938 /* load/store multiple */
939 if (dp)
940 n = (insn >> 1) & 0x7f;
941 else
942 n = insn & 0xff;
943
944 if (insn & (1 << 24)) /* pre-decrement */
945 gen_op_addl_T1_im(-((insn & 0xff) << 2));
946
947 if (dp)
948 offset = 8;
949 else
950 offset = 4;
951 for (i = 0; i < n; i++) {
952 if (insn & (1 << 20)) {
953 /* load */
b5ff1b31 954 gen_vfp_ld(s, dp);
b7bcbe95
FB		 955 gen_mov_vreg_F0(dp, rd + i);
956 } else {
957 /* store */
958 gen_mov_F0_vreg(dp, rd + i);
b5ff1b31 959 gen_vfp_st(s, dp);
b7bcbe95
FB		 960 }
961 gen_op_addl_T1_im(offset);
962 }
963 if (insn & (1 << 21)) {
964 /* writeback */
965 if (insn & (1 << 24))
966 offset = -offset * n;
967 else if (dp && (insn & 1))
968 offset = 4;
969 else
970 offset = 0;
971
972 if (offset != 0)
973 gen_op_addl_T1_im(offset);
974 gen_movl_reg_T1(s, rn);
975 }
976 }
977 }
978 break;
979 default:
980 /* Should never happen. */
981 return 1;
982 }
983 return 0;
984}
985
6e256c93 986static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest)
c53be334 987{
6e256c93
FB		 988 TranslationBlock *tb;
989
990 tb = s->tb;
991 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
992 if (n == 0)
993 gen_op_goto_tb0(TBPARAM(tb));
994 else
995 gen_op_goto_tb1(TBPARAM(tb));
996 gen_op_movl_T0_im(dest);
997 gen_op_movl_r15_T0();
998 gen_op_movl_T0_im((long)tb + n);
999 gen_op_exit_tb();
1000 } else {
1001 gen_op_movl_T0_im(dest);
1002 gen_op_movl_r15_T0();
1003 gen_op_movl_T0_0();
1004 gen_op_exit_tb();
1005 }
c53be334
FB		 1006}
1007
8aaca4c0
FB		 1008static inline void gen_jmp (DisasContext *s, uint32_t dest)
1009{
1010 if (__builtin_expect(s->singlestep_enabled, 0)) {
1011 /* An indirect jump so that we still trigger the debug exception. */
5899f386
FB		 1012 if (s->thumb)
1013 dest |= 1;
8aaca4c0
FB		 1014 gen_op_movl_T0_im(dest);
1015 gen_bx(s);
1016 } else {
6e256c93 1017 gen_goto_tb(s, 0, dest);
8aaca4c0
FB		 1018 s->is_jmp = DISAS_TB_JUMP;
1019 }
1020}
1021
b5ff1b31
FB		 1022static inline void gen_mulxy(int x, int y)
1023{
1024 if (x & 2)
1025 gen_op_sarl_T0_im(16);
1026 else
1027 gen_op_sxth_T0();
1028 if (y & 1)
1029 gen_op_sarl_T1_im(16);
1030 else
1031 gen_op_sxth_T1();
1032 gen_op_mul_T0_T1();
1033}
1034
1035/* Return the mask of PSR bits set by a MSR instruction. */
1036static uint32_t msr_mask(DisasContext *s, int flags) {
1037 uint32_t mask;
1038
1039 mask = 0;
1040 if (flags & (1 << 0))
1041 mask |= 0xff;
1042 if (flags & (1 << 1))
1043 mask |= 0xff00;
1044 if (flags & (1 << 2))
1045 mask |= 0xff0000;
1046 if (flags & (1 << 3))
1047 mask |= 0xff000000;
1048 /* Mask out undefined bits and state bits. */
1049 mask &= 0xf89f03df;
1050 /* Mask out privileged bits. */
1051 if (IS_USER(s))
1052 mask &= 0xf80f0200;
1053 return mask;
1054}
1055
1056/* Returns nonzero if access to the PSR is not permitted. */
1057static int gen_set_psr_T0(DisasContext *s, uint32_t mask, int spsr)
1058{
1059 if (spsr) {
1060 /* ??? This is also undefined in system mode. */
1061 if (IS_USER(s))
1062 return 1;
1063 gen_op_movl_spsr_T0(mask);
1064 } else {
1065 gen_op_movl_cpsr_T0(mask);
1066 }
1067 gen_lookup_tb(s);
1068 return 0;
1069}
1070
1071static void gen_exception_return(DisasContext *s)
1072{
1073 gen_op_movl_reg_TN[0][15]();
1074 gen_op_movl_T0_spsr();
1075 gen_op_movl_cpsr_T0(0xffffffff);
1076 s->is_jmp = DISAS_UPDATE;
1077}
1078
b7bcbe95 1079static void disas_arm_insn(CPUState * env, DisasContext *s)
2c0262af
FB		 1080{
1081 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
1082
b5ff1b31 1083 insn = ldl_code(s->pc);
2c0262af
FB		 1084 s->pc += 4;
1085
1086 cond = insn >> 28;
99c475ab 1087 if (cond == 0xf){
b7bcbe95 1088 /* Unconditional instructions. */
99c475ab
FB		 1089 if ((insn & 0x0d70f000) == 0x0550f000)
1090 return; /* PLD */
1091 else if ((insn & 0x0e000000) == 0x0a000000) {
1092 /* branch link and change to thumb (blx <offset>) */
1093 int32_t offset;
1094
1095 val = (uint32_t)s->pc;
1096 gen_op_movl_T0_im(val);
1097 gen_movl_reg_T0(s, 14);
1098 /* Sign-extend the 24-bit offset */
1099 offset = (((int32_t)insn) << 8) >> 8;
1100 /* offset * 4 + bit24 * 2 + (thumb bit) */
1101 val += (offset << 2) | ((insn >> 23) & 2) | 1;
1102 /* pipeline offset */
1103 val += 4;
1104 gen_op_movl_T0_im(val);
1105 gen_bx(s);
1106 return;
b7bcbe95
FB		 1107 } else if ((insn & 0x0fe00000) == 0x0c400000) {
1108 /* Coprocessor double register transfer. */
1109 } else if ((insn & 0x0f000010) == 0x0e000010) {
1110 /* Additional coprocessor register transfer. */
b5ff1b31
FB		 1111 } else if ((insn & 0x0ff10010) == 0x01000000) {
1112 /* cps (privileged) */
1113 } else if ((insn & 0x0ffffdff) == 0x01010000) {
1114 /* setend */
1115 if (insn & (1 << 9)) {
1116 /* BE8 mode not implemented. */
1117 goto illegal_op;
1118 }
1119 return;
99c475ab 1120 }
2c0262af 1121 goto illegal_op;
99c475ab 1122 }
2c0262af
FB		 1123 if (cond != 0xe) {
1124 /* if not always execute, we generate a conditional jump to
1125 next instruction */
e50e6a20
FB		 1126 s->condlabel = gen_new_label();
1127 gen_test_cc[cond ^ 1](s->condlabel);
1128 s->condjmp = 1;
1129 //gen_test_cc[cond ^ 1]((long)s->tb, (long)s->pc);
1130 //s->is_jmp = DISAS_JUMP_NEXT;
2c0262af 1131 }
99c475ab 1132 if ((insn & 0x0f900000) == 0x03000000) {
b5ff1b31 1133 if ((insn & 0x0fb0f000) != 0x0320f000)
99c475ab
FB		 1134 goto illegal_op;
1135 /* CPSR = immediate */
1136 val = insn & 0xff;
1137 shift = ((insn >> 8) & 0xf) * 2;
1138 if (shift)
1139 val = (val >> shift) | (val << (32 - shift));
1140 gen_op_movl_T0_im(val);
b5ff1b31
FB		 1141 if (gen_set_psr_T0(s, msr_mask(s, (insn >> 16) & 0xf),
1142 (insn & (1 << 22)) != 0))
1143 goto illegal_op;
99c475ab
FB		 1144 } else if ((insn & 0x0f900000) == 0x01000000
1145 && (insn & 0x00000090) != 0x00000090) {
1146 /* miscellaneous instructions */
1147 op1 = (insn >> 21) & 3;
1148 sh = (insn >> 4) & 0xf;
1149 rm = insn & 0xf;
1150 switch (sh) {
1151 case 0x0: /* move program status register */
99c475ab 1152 if (op1 & 1) {
b5ff1b31 1153 /* PSR = reg */
99c475ab 1154 gen_movl_T0_reg(s, rm);
b5ff1b31
FB		 1155 if (gen_set_psr_T0(s, msr_mask(s, (insn >> 16) & 0xf),
1156 (op1 & 2) != 0))
1157 goto illegal_op;
99c475ab
FB		 1158 } else {
1159 /* reg = CPSR */
1160 rd = (insn >> 12) & 0xf;
b5ff1b31
FB		 1161 if (op1 & 2) {
1162 if (IS_USER(s))
1163 goto illegal_op;
1164 gen_op_movl_T0_spsr();
1165 } else {
1166 gen_op_movl_T0_cpsr();
1167 }
99c475ab
FB		 1168 gen_movl_reg_T0(s, rd);
1169 }
b8a9e8f1 1170 break;
99c475ab
FB		 1171 case 0x1:
1172 if (op1 == 1) {
1173 /* branch/exchange thumb (bx). */
1174 gen_movl_T0_reg(s, rm);
1175 gen_bx(s);
1176 } else if (op1 == 3) {
1177 /* clz */
1178 rd = (insn >> 12) & 0xf;
1179 gen_movl_T0_reg(s, rm);
1180 gen_op_clz_T0();
1181 gen_movl_reg_T0(s, rd);
1182 } else {
1183 goto illegal_op;
1184 }
1185 break;
b5ff1b31
FB		 1186 case 0x2:
1187 if (op1 == 1) {
1188 ARCH(5J); /* bxj */
1189 /* Trivial implementation equivalent to bx. */
1190 gen_movl_T0_reg(s, rm);
1191 gen_bx(s);
1192 } else {
1193 goto illegal_op;
1194 }
1195 break;
99c475ab
FB		 1196 case 0x3:
1197 if (op1 != 1)
1198 goto illegal_op;
1199
1200 /* branch link/exchange thumb (blx) */
1201 val = (uint32_t)s->pc;
1202 gen_op_movl_T0_im(val);
1203 gen_movl_reg_T0(s, 14);
1204 gen_movl_T0_reg(s, rm);
1205 gen_bx(s);
1206 break;
1207 case 0x5: /* saturating add/subtract */
1208 rd = (insn >> 12) & 0xf;
1209 rn = (insn >> 16) & 0xf;
ff8263a9
FB		 1210 gen_movl_T0_reg(s, rm);
1211 gen_movl_T1_reg(s, rn);
1212 if (op1 & 2)
1213 gen_op_double_T1_saturate();
99c475ab
FB		 1214 if (op1 & 1)
1215 gen_op_subl_T0_T1_saturate();
1216 else
1217 gen_op_addl_T0_T1_saturate();
ff8263a9 1218 gen_movl_reg_T0(s, rd);
99c475ab
FB		 1219 break;
1220 case 0x8: /* signed multiply */
1221 case 0xa:
1222 case 0xc:
1223 case 0xe:
1224 rs = (insn >> 8) & 0xf;
1225 rn = (insn >> 12) & 0xf;
1226 rd = (insn >> 16) & 0xf;
1227 if (op1 == 1) {
1228 /* (32 * 16) >> 16 */
1229 gen_movl_T0_reg(s, rm);
1230 gen_movl_T1_reg(s, rs);
1231 if (sh & 4)
1232 gen_op_sarl_T1_im(16);
1233 else
b5ff1b31 1234 gen_op_sxth_T1();
99c475ab
FB		 1235 gen_op_imulw_T0_T1();
1236 if ((sh & 2) == 0) {
1237 gen_movl_T1_reg(s, rn);
1238 gen_op_addl_T0_T1_setq();
1239 }
1240 gen_movl_reg_T0(s, rd);
1241 } else {
1242 /* 16 * 16 */
1243 gen_movl_T0_reg(s, rm);
99c475ab 1244 gen_movl_T1_reg(s, rs);
b5ff1b31 1245 gen_mulxy(sh & 2, sh & 4);
99c475ab 1246 if (op1 == 2) {
b5ff1b31 1247 gen_op_signbit_T1_T0();
99c475ab
FB		 1248 gen_op_addq_T0_T1(rn, rd);
1249 gen_movl_reg_T0(s, rn);
1250 gen_movl_reg_T1(s, rd);
1251 } else {
99c475ab
FB		 1252 if (op1 == 0) {
1253 gen_movl_T1_reg(s, rn);
1254 gen_op_addl_T0_T1_setq();
1255 }
1256 gen_movl_reg_T0(s, rd);
1257 }
1258 }
1259 break;
1260 default:
1261 goto illegal_op;
1262 }
1263 } else if (((insn & 0x0e000000) == 0 &&
1264 (insn & 0x00000090) != 0x90) ||
1265 ((insn & 0x0e000000) == (1 << 25))) {
2c0262af
FB		 1266 int set_cc, logic_cc, shiftop;
1267
1268 op1 = (insn >> 21) & 0xf;
1269 set_cc = (insn >> 20) & 1;
1270 logic_cc = table_logic_cc[op1] & set_cc;
1271
1272 /* data processing instruction */
1273 if (insn & (1 << 25)) {
1274 /* immediate operand */
1275 val = insn & 0xff;
1276 shift = ((insn >> 8) & 0xf) * 2;
1277 if (shift)
1278 val = (val >> shift) | (val << (32 - shift));
1279 gen_op_movl_T1_im(val);
7ff4d218
FB		 1280 if (logic_cc && shift)
1281 gen_op_mov_CF_T1();
2c0262af
FB		 1282 } else {
1283 /* register */
1284 rm = (insn) & 0xf;
1285 gen_movl_T1_reg(s, rm);
1286 shiftop = (insn >> 5) & 3;
1287 if (!(insn & (1 << 4))) {
1288 shift = (insn >> 7) & 0x1f;
1289 if (shift != 0) {
1290 if (logic_cc) {
1291 gen_shift_T1_im_cc[shiftop](shift);
1292 } else {
1293 gen_shift_T1_im[shiftop](shift);
1294 }
1e8d4eec
FB		 1295 } else if (shiftop != 0) {
1296 if (logic_cc) {
1297 gen_shift_T1_0_cc[shiftop]();
1298 } else {
1299 gen_shift_T1_0[shiftop]();
1300 }
2c0262af
FB		 1301 }
1302 } else {
1303 rs = (insn >> 8) & 0xf;
1304 gen_movl_T0_reg(s, rs);
1305 if (logic_cc) {
1306 gen_shift_T1_T0_cc[shiftop]();
1307 } else {
1308 gen_shift_T1_T0[shiftop]();
1309 }
1310 }
1311 }
1312 if (op1 != 0x0f && op1 != 0x0d) {
1313 rn = (insn >> 16) & 0xf;
1314 gen_movl_T0_reg(s, rn);
1315 }
1316 rd = (insn >> 12) & 0xf;
1317 switch(op1) {
1318 case 0x00:
1319 gen_op_andl_T0_T1();
1320 gen_movl_reg_T0(s, rd);
1321 if (logic_cc)
1322 gen_op_logic_T0_cc();
1323 break;
1324 case 0x01:
1325 gen_op_xorl_T0_T1();
1326 gen_movl_reg_T0(s, rd);
1327 if (logic_cc)
1328 gen_op_logic_T0_cc();
1329 break;
1330 case 0x02:
b5ff1b31
FB		 1331 if (set_cc && rd == 15) {
1332 /* SUBS r15, ... is used for exception return. */
1333 if (IS_USER(s))
1334 goto illegal_op;
2c0262af 1335 gen_op_subl_T0_T1_cc();
b5ff1b31
FB		 1336 gen_exception_return(s);
1337 } else {
1338 if (set_cc)
1339 gen_op_subl_T0_T1_cc();
1340 else
1341 gen_op_subl_T0_T1();
1342 gen_movl_reg_T0(s, rd);
1343 }
2c0262af
FB		 1344 break;
1345 case 0x03:
1346 if (set_cc)
1347 gen_op_rsbl_T0_T1_cc();
1348 else
1349 gen_op_rsbl_T0_T1();
1350 gen_movl_reg_T0(s, rd);
1351 break;
1352 case 0x04:
1353 if (set_cc)
1354 gen_op_addl_T0_T1_cc();
1355 else
1356 gen_op_addl_T0_T1();
1357 gen_movl_reg_T0(s, rd);
1358 break;
1359 case 0x05:
1360 if (set_cc)
1361 gen_op_adcl_T0_T1_cc();
1362 else
1363 gen_op_adcl_T0_T1();
1364 gen_movl_reg_T0(s, rd);
1365 break;
1366 case 0x06:
1367 if (set_cc)
1368 gen_op_sbcl_T0_T1_cc();
1369 else
1370 gen_op_sbcl_T0_T1();
1371 gen_movl_reg_T0(s, rd);
1372 break;
1373 case 0x07:
1374 if (set_cc)
1375 gen_op_rscl_T0_T1_cc();
1376 else
1377 gen_op_rscl_T0_T1();
1378 gen_movl_reg_T0(s, rd);
1379 break;
1380 case 0x08:
1381 if (set_cc) {
1382 gen_op_andl_T0_T1();
1383 gen_op_logic_T0_cc();
1384 }
1385 break;
1386 case 0x09:
1387 if (set_cc) {
1388 gen_op_xorl_T0_T1();
1389 gen_op_logic_T0_cc();
1390 }
1391 break;
1392 case 0x0a:
1393 if (set_cc) {
1394 gen_op_subl_T0_T1_cc();
1395 }
1396 break;
1397 case 0x0b:
1398 if (set_cc) {
1399 gen_op_addl_T0_T1_cc();
1400 }
1401 break;
1402 case 0x0c:
1403 gen_op_orl_T0_T1();
1404 gen_movl_reg_T0(s, rd);
1405 if (logic_cc)
1406 gen_op_logic_T0_cc();
1407 break;
1408 case 0x0d:
b5ff1b31
FB		 1409 if (logic_cc && rd == 15) {
1410 /* MOVS r15, ... is used for exception return. */
1411 if (IS_USER(s))
1412 goto illegal_op;
1413 gen_op_movl_T0_T1();
1414 gen_exception_return(s);
1415 } else {
1416 gen_movl_reg_T1(s, rd);
1417 if (logic_cc)
1418 gen_op_logic_T1_cc();
1419 }
2c0262af
FB		 1420 break;
1421 case 0x0e:
1422 gen_op_bicl_T0_T1();
1423 gen_movl_reg_T0(s, rd);
1424 if (logic_cc)
1425 gen_op_logic_T0_cc();
1426 break;
1427 default:
1428 case 0x0f:
1429 gen_op_notl_T1();
1430 gen_movl_reg_T1(s, rd);
1431 if (logic_cc)
1432 gen_op_logic_T1_cc();
1433 break;
1434 }
1435 } else {
1436 /* other instructions */
1437 op1 = (insn >> 24) & 0xf;
1438 switch(op1) {
1439 case 0x0:
1440 case 0x1:
99c475ab 1441 /* multiplies, extra load/stores */
2c0262af
FB		 1442 sh = (insn >> 5) & 3;
1443 if (sh == 0) {
1444 if (op1 == 0x0) {
1445 rd = (insn >> 16) & 0xf;
1446 rn = (insn >> 12) & 0xf;
1447 rs = (insn >> 8) & 0xf;
1448 rm = (insn) & 0xf;
99c475ab 1449 if (((insn >> 22) & 3) == 0) {
2c0262af
FB		 1450 /* 32 bit mul */
1451 gen_movl_T0_reg(s, rs);
1452 gen_movl_T1_reg(s, rm);
1453 gen_op_mul_T0_T1();
1454 if (insn & (1 << 21)) {
1455 gen_movl_T1_reg(s, rn);
1456 gen_op_addl_T0_T1();
1457 }
1458 if (insn & (1 << 20))
1459 gen_op_logic_T0_cc();
1460 gen_movl_reg_T0(s, rd);
1461 } else {
1462 /* 64 bit mul */
1463 gen_movl_T0_reg(s, rs);
1464 gen_movl_T1_reg(s, rm);
1465 if (insn & (1 << 22))
2c0262af 1466 gen_op_imull_T0_T1();
2e134c9c
FB		 1467 else
1468 gen_op_mull_T0_T1();
99c475ab 1469 if (insn & (1 << 21)) /* mult accumulate */
2c0262af 1470 gen_op_addq_T0_T1(rn, rd);
99c475ab 1471 if (!(insn & (1 << 23))) { /* double accumulate */
b5ff1b31 1472 ARCH(6);
99c475ab
FB		 1473 gen_op_addq_lo_T0_T1(rn);
1474 gen_op_addq_lo_T0_T1(rd);
1475 }
2c0262af
FB		 1476 if (insn & (1 << 20))
1477 gen_op_logicq_cc();
1478 gen_movl_reg_T0(s, rn);
1479 gen_movl_reg_T1(s, rd);
1480 }
1481 } else {
2c0262af
FB		 1482 rn = (insn >> 16) & 0xf;
1483 rd = (insn >> 12) & 0xf;
99c475ab
FB		 1484 if (insn & (1 << 23)) {
1485 /* load/store exclusive */
1486 goto illegal_op;
2c0262af 1487 } else {
99c475ab
FB		 1488 /* SWP instruction */
1489 rm = (insn) & 0xf;
1490
1491 gen_movl_T0_reg(s, rm);
1492 gen_movl_T1_reg(s, rn);
1493 if (insn & (1 << 22)) {
b5ff1b31 1494 gen_ldst(swpb, s);
99c475ab 1495 } else {
b5ff1b31 1496 gen_ldst(swpl, s);
99c475ab
FB		 1497 }
1498 gen_movl_reg_T0(s, rd);
2c0262af 1499 }
2c0262af
FB		 1500 }
1501 } else {
99c475ab 1502 /* Misc load/store */
2c0262af
FB		 1503 rn = (insn >> 16) & 0xf;
1504 rd = (insn >> 12) & 0xf;
1505 gen_movl_T1_reg(s, rn);
beddab75
FB		 1506 if (insn & (1 << 24))
1507 gen_add_datah_offset(s, insn);
2c0262af
FB		 1508 if (insn & (1 << 20)) {
1509 /* load */
1510 switch(sh) {
1511 case 1:
b5ff1b31 1512 gen_ldst(lduw, s);
2c0262af
FB		 1513 break;
1514 case 2:
b5ff1b31 1515 gen_ldst(ldsb, s);
2c0262af
FB		 1516 break;
1517 default:
1518 case 3:
b5ff1b31 1519 gen_ldst(ldsw, s);
2c0262af
FB		 1520 break;
1521 }
e748ba4f 1522 gen_movl_reg_T0(s, rd);
99c475ab
FB		 1523 } else if (sh & 2) {
1524 /* doubleword */
1525 if (sh & 1) {
1526 /* store */
1527 gen_movl_T0_reg(s, rd);
b5ff1b31 1528 gen_ldst(stl, s);
99c475ab
FB		 1529 gen_op_addl_T1_im(4);
1530 gen_movl_T0_reg(s, rd + 1);
b5ff1b31 1531 gen_ldst(stl, s);
99c475ab
FB		 1532 if ((insn & (1 << 24)) || (insn & (1 << 20)))
1533 gen_op_addl_T1_im(-4);
1534 } else {
1535 /* load */
b5ff1b31 1536 gen_ldst(ldl, s);
99c475ab
FB		 1537 gen_movl_reg_T0(s, rd);
1538 gen_op_addl_T1_im(4);
b5ff1b31 1539 gen_ldst(ldl, s);
99c475ab
FB		 1540 gen_movl_reg_T0(s, rd + 1);
1541 if ((insn & (1 << 24)) || (insn & (1 << 20)))
1542 gen_op_addl_T1_im(-4);
1543 }
2c0262af
FB		 1544 } else {
1545 /* store */
e748ba4f 1546 gen_movl_T0_reg(s, rd);
b5ff1b31 1547 gen_ldst(stw, s);
2c0262af
FB		 1548 }
1549 if (!(insn & (1 << 24))) {
1550 gen_add_datah_offset(s, insn);
1551 gen_movl_reg_T1(s, rn);
1552 } else if (insn & (1 << 21)) {
1553 gen_movl_reg_T1(s, rn);
1554 }
1555 }
1556 break;
1557 case 0x4:
1558 case 0x5:
1559 case 0x6:
1560 case 0x7:
1561 /* load/store byte/word */
1562 rn = (insn >> 16) & 0xf;
1563 rd = (insn >> 12) & 0xf;
1564 gen_movl_T1_reg(s, rn);
b5ff1b31 1565 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
2c0262af
FB		 1566 if (insn & (1 << 24))
1567 gen_add_data_offset(s, insn);
1568 if (insn & (1 << 20)) {
1569 /* load */
b5ff1b31 1570#if defined(CONFIG_USER_ONLY)
2c0262af 1571 if (insn & (1 << 22))
b5ff1b31 1572 gen_op_ldub_raw();
2c0262af 1573 else
b5ff1b31
FB		 1574 gen_op_ldl_raw();
1575#else
1576 if (insn & (1 << 22)) {
1577 if (i)
1578 gen_op_ldub_user();
1579 else
1580 gen_op_ldub_kernel();
1581 } else {
1582 if (i)
1583 gen_op_ldl_user();
1584 else
1585 gen_op_ldl_kernel();
1586 }
1587#endif
99c475ab
FB		 1588 if (rd == 15)
1589 gen_bx(s);
1590 else
1591 gen_movl_reg_T0(s, rd);
2c0262af
FB		 1592 } else {
1593 /* store */
1594 gen_movl_T0_reg(s, rd);
b5ff1b31 1595#if defined(CONFIG_USER_ONLY)
2c0262af 1596 if (insn & (1 << 22))
b5ff1b31 1597 gen_op_stb_raw();
2c0262af 1598 else
b5ff1b31
FB		 1599 gen_op_stl_raw();
1600#else
1601 if (insn & (1 << 22)) {
1602 if (i)
1603 gen_op_stb_user();
1604 else
1605 gen_op_stb_kernel();
1606 } else {
1607 if (i)
1608 gen_op_stl_user();
1609 else
1610 gen_op_stl_kernel();
1611 }
1612#endif
2c0262af
FB		 1613 }
1614 if (!(insn & (1 << 24))) {
1615 gen_add_data_offset(s, insn);
1616 gen_movl_reg_T1(s, rn);
1617 } else if (insn & (1 << 21))
1618 gen_movl_reg_T1(s, rn); {
1619 }
1620 break;
1621 case 0x08:
1622 case 0x09:
1623 {
b5ff1b31 1624 int j, n, user;
2c0262af
FB		 1625 /* load/store multiple words */
1626 /* XXX: store correct base if write back */
b5ff1b31
FB		 1627 user = 0;
1628 if (insn & (1 << 22)) {
1629 if (IS_USER(s))
1630 goto illegal_op; /* only usable in supervisor mode */
1631
1632 if ((insn & (1 << 15)) == 0)
1633 user = 1;
1634 }
2c0262af
FB		 1635 rn = (insn >> 16) & 0xf;
1636 gen_movl_T1_reg(s, rn);
1637
1638 /* compute total size */
1639 n = 0;
1640 for(i=0;i<16;i++) {
1641 if (insn & (1 << i))
1642 n++;
1643 }
1644 /* XXX: test invalid n == 0 case ? */
1645 if (insn & (1 << 23)) {
1646 if (insn & (1 << 24)) {
1647 /* pre increment */
1648 gen_op_addl_T1_im(4);
1649 } else {
1650 /* post increment */
1651 }
1652 } else {
1653 if (insn & (1 << 24)) {
1654 /* pre decrement */
1655 gen_op_addl_T1_im(-(n * 4));
1656 } else {
1657 /* post decrement */
1658 if (n != 1)
1659 gen_op_addl_T1_im(-((n - 1) * 4));
1660 }
1661 }
1662 j = 0;
1663 for(i=0;i<16;i++) {
1664 if (insn & (1 << i)) {
1665 if (insn & (1 << 20)) {
1666 /* load */
b5ff1b31
FB		 1667 gen_ldst(ldl, s);
1668 if (i == 15) {
99c475ab 1669 gen_bx(s);
b5ff1b31
FB		 1670 } else if (user) {
1671 gen_op_movl_user_T0(i);
1672 } else {
99c475ab 1673 gen_movl_reg_T0(s, i);
b5ff1b31 1674 }
2c0262af
FB		 1675 } else {
1676 /* store */
1677 if (i == 15) {
1678 /* special case: r15 = PC + 12 */
1679 val = (long)s->pc + 8;
1680 gen_op_movl_TN_im[0](val);
b5ff1b31
FB		 1681 } else if (user) {
1682 gen_op_movl_T0_user(i);
2c0262af
FB		 1683 } else {
1684 gen_movl_T0_reg(s, i);
1685 }
b5ff1b31 1686 gen_ldst(stl, s);
2c0262af
FB		 1687 }
1688 j++;
1689 /* no need to add after the last transfer */
1690 if (j != n)
1691 gen_op_addl_T1_im(4);
1692 }
1693 }
1694 if (insn & (1 << 21)) {
1695 /* write back */
1696 if (insn & (1 << 23)) {
1697 if (insn & (1 << 24)) {
1698 /* pre increment */
1699 } else {
1700 /* post increment */
1701 gen_op_addl_T1_im(4);
1702 }
1703 } else {
1704 if (insn & (1 << 24)) {
1705 /* pre decrement */
1706 if (n != 1)
1707 gen_op_addl_T1_im(-((n - 1) * 4));
1708 } else {
1709 /* post decrement */
1710 gen_op_addl_T1_im(-(n * 4));
1711 }
1712 }
1713 gen_movl_reg_T1(s, rn);
1714 }
b5ff1b31
FB		 1715 if ((insn & (1 << 22)) && !user) {
1716 /* Restore CPSR from SPSR. */
1717 gen_op_movl_T0_spsr();
1718 gen_op_movl_cpsr_T0(0xffffffff);
1719 s->is_jmp = DISAS_UPDATE;
1720 }
2c0262af
FB		 1721 }
1722 break;
1723 case 0xa:
1724 case 0xb:
1725 {
99c475ab 1726 int32_t offset;
2c0262af
FB		 1727
1728 /* branch (and link) */
99c475ab 1729 val = (int32_t)s->pc;
2c0262af
FB		 1730 if (insn & (1 << 24)) {
1731 gen_op_movl_T0_im(val);
1732 gen_op_movl_reg_TN[0][14]();
1733 }
99c475ab 1734 offset = (((int32_t)insn << 8) >> 8);
2c0262af 1735 val += (offset << 2) + 4;
8aaca4c0 1736 gen_jmp(s, val);
2c0262af
FB		 1737 }
1738 break;
b7bcbe95
FB		 1739 case 0xc:
1740 case 0xd:
1741 case 0xe:
1742 /* Coprocessor. */
1743 op1 = (insn >> 8) & 0xf;
1744 switch (op1) {
1745 case 10:
1746 case 11:
1747 if (disas_vfp_insn (env, s, insn))
1748 goto illegal_op;
1749 break;
b5ff1b31
FB		 1750 case 15:
1751 if (disas_cp15_insn (s, insn))
1752 goto illegal_op;
1753 break;
b7bcbe95
FB		 1754 default:
1755 /* unknown coprocessor. */
1756 goto illegal_op;
1757 }
1758 break;
2c0262af
FB		 1759 case 0xf:
1760 /* swi */
1761 gen_op_movl_T0_im((long)s->pc);
1762 gen_op_movl_reg_TN[0][15]();
1763 gen_op_swi();
1764 s->is_jmp = DISAS_JUMP;
1765 break;
2c0262af
FB		 1766 default:
1767 illegal_op:
1768 gen_op_movl_T0_im((long)s->pc - 4);
1769 gen_op_movl_reg_TN[0][15]();
1770 gen_op_undef_insn();
1771 s->is_jmp = DISAS_JUMP;
1772 break;
1773 }
1774 }
1775}
1776
99c475ab
FB		 1777static void disas_thumb_insn(DisasContext *s)
1778{
1779 uint32_t val, insn, op, rm, rn, rd, shift, cond;
1780 int32_t offset;
1781 int i;
1782
b5ff1b31 1783 insn = lduw_code(s->pc);
99c475ab 1784 s->pc += 2;
b5ff1b31 1785
99c475ab
FB		 1786 switch (insn >> 12) {
1787 case 0: case 1:
1788 rd = insn & 7;
1789 op = (insn >> 11) & 3;
1790 if (op == 3) {
1791 /* add/subtract */
1792 rn = (insn >> 3) & 7;
1793 gen_movl_T0_reg(s, rn);
1794 if (insn & (1 << 10)) {
1795 /* immediate */
1796 gen_op_movl_T1_im((insn >> 6) & 7);
1797 } else {
1798 /* reg */
1799 rm = (insn >> 6) & 7;
1800 gen_movl_T1_reg(s, rm);
1801 }
1802 if (insn & (1 << 9))
5899f386 1803 gen_op_subl_T0_T1_cc();
99c475ab
FB		 1804 else
1805 gen_op_addl_T0_T1_cc();
1806 gen_movl_reg_T0(s, rd);
1807 } else {
1808 /* shift immediate */
1809 rm = (insn >> 3) & 7;
1810 shift = (insn >> 6) & 0x1f;
1811 gen_movl_T0_reg(s, rm);
1812 gen_shift_T0_im_thumb[op](shift);
1813 gen_movl_reg_T0(s, rd);
1814 }
1815 break;
1816 case 2: case 3:
1817 /* arithmetic large immediate */
1818 op = (insn >> 11) & 3;
1819 rd = (insn >> 8) & 0x7;
1820 if (op == 0) {
1821 gen_op_movl_T0_im(insn & 0xff);
1822 } else {
1823 gen_movl_T0_reg(s, rd);
1824 gen_op_movl_T1_im(insn & 0xff);
1825 }
1826 switch (op) {
1827 case 0: /* mov */
1828 gen_op_logic_T0_cc();
1829 break;
1830 case 1: /* cmp */
1831 gen_op_subl_T0_T1_cc();
1832 break;
1833 case 2: /* add */
1834 gen_op_addl_T0_T1_cc();
1835 break;
1836 case 3: /* sub */
1837 gen_op_subl_T0_T1_cc();
1838 break;
1839 }
1840 if (op != 1)
1841 gen_movl_reg_T0(s, rd);
1842 break;
1843 case 4:
1844 if (insn & (1 << 11)) {
1845 rd = (insn >> 8) & 7;
5899f386
FB		 1846 /* load pc-relative. Bit 1 of PC is ignored. */
1847 val = s->pc + 2 + ((insn & 0xff) * 4);
1848 val &= ~(uint32_t)2;
99c475ab 1849 gen_op_movl_T1_im(val);
b5ff1b31 1850 gen_ldst(ldl, s);
99c475ab
FB		 1851 gen_movl_reg_T0(s, rd);
1852 break;
1853 }
1854 if (insn & (1 << 10)) {
1855 /* data processing extended or blx */
1856 rd = (insn & 7) | ((insn >> 4) & 8);
1857 rm = (insn >> 3) & 0xf;
1858 op = (insn >> 8) & 3;
1859 switch (op) {
1860 case 0: /* add */
1861 gen_movl_T0_reg(s, rd);
1862 gen_movl_T1_reg(s, rm);
1863 gen_op_addl_T0_T1();
1864 gen_movl_reg_T0(s, rd);
1865 break;
1866 case 1: /* cmp */
1867 gen_movl_T0_reg(s, rd);
1868 gen_movl_T1_reg(s, rm);
1869 gen_op_subl_T0_T1_cc();
1870 break;
1871 case 2: /* mov/cpy */
1872 gen_movl_T0_reg(s, rm);
1873 gen_movl_reg_T0(s, rd);
1874 break;
1875 case 3:/* branch [and link] exchange thumb register */
1876 if (insn & (1 << 7)) {
1877 val = (uint32_t)s->pc | 1;
1878 gen_op_movl_T1_im(val);
1879 gen_movl_reg_T1(s, 14);
1880 }
1881 gen_movl_T0_reg(s, rm);
1882 gen_bx(s);
1883 break;
1884 }
1885 break;
1886 }
1887
1888 /* data processing register */
1889 rd = insn & 7;
1890 rm = (insn >> 3) & 7;
1891 op = (insn >> 6) & 0xf;
1892 if (op == 2 || op == 3 || op == 4 || op == 7) {
1893 /* the shift/rotate ops want the operands backwards */
1894 val = rm;
1895 rm = rd;
1896 rd = val;
1897 val = 1;
1898 } else {
1899 val = 0;
1900 }
1901
1902 if (op == 9) /* neg */
1903 gen_op_movl_T0_im(0);
1904 else if (op != 0xf) /* mvn doesn't read its first operand */
1905 gen_movl_T0_reg(s, rd);
1906
1907 gen_movl_T1_reg(s, rm);
5899f386 1908 switch (op) {
99c475ab
FB		 1909 case 0x0: /* and */
1910 gen_op_andl_T0_T1();
1911 gen_op_logic_T0_cc();
1912 break;
1913 case 0x1: /* eor */
1914 gen_op_xorl_T0_T1();
1915 gen_op_logic_T0_cc();
1916 break;
1917 case 0x2: /* lsl */
1918 gen_op_shll_T1_T0_cc();
1919 break;
1920 case 0x3: /* lsr */
1921 gen_op_shrl_T1_T0_cc();
1922 break;
1923 case 0x4: /* asr */
1924 gen_op_sarl_T1_T0_cc();
1925 break;
1926 case 0x5: /* adc */
1927 gen_op_adcl_T0_T1_cc();
1928 break;
1929 case 0x6: /* sbc */
1930 gen_op_sbcl_T0_T1_cc();
1931 break;
1932 case 0x7: /* ror */
1933 gen_op_rorl_T1_T0_cc();
1934 break;
1935 case 0x8: /* tst */
1936 gen_op_andl_T0_T1();
1937 gen_op_logic_T0_cc();
1938 rd = 16;
5899f386 1939 break;
99c475ab 1940 case 0x9: /* neg */
5899f386 1941 gen_op_subl_T0_T1_cc();
99c475ab
FB		 1942 break;
1943 case 0xa: /* cmp */
1944 gen_op_subl_T0_T1_cc();
1945 rd = 16;
1946 break;
1947 case 0xb: /* cmn */
1948 gen_op_addl_T0_T1_cc();
1949 rd = 16;
1950 break;
1951 case 0xc: /* orr */
1952 gen_op_orl_T0_T1();
1953 gen_op_logic_T0_cc();
1954 break;
1955 case 0xd: /* mul */
1956 gen_op_mull_T0_T1();
1957 gen_op_logic_T0_cc();
1958 break;
1959 case 0xe: /* bic */
1960 gen_op_bicl_T0_T1();
1961 gen_op_logic_T0_cc();
1962 break;
1963 case 0xf: /* mvn */
1964 gen_op_notl_T1();
1965 gen_op_logic_T1_cc();
1966 val = 1;
5899f386 1967 rm = rd;
99c475ab
FB		 1968 break;
1969 }
1970 if (rd != 16) {
1971 if (val)
5899f386 1972 gen_movl_reg_T1(s, rm);
99c475ab
FB		 1973 else
1974 gen_movl_reg_T0(s, rd);
1975 }
1976 break;
1977
1978 case 5:
1979 /* load/store register offset. */
1980 rd = insn & 7;
1981 rn = (insn >> 3) & 7;
1982 rm = (insn >> 6) & 7;
1983 op = (insn >> 9) & 7;
1984 gen_movl_T1_reg(s, rn);
1985 gen_movl_T2_reg(s, rm);
1986 gen_op_addl_T1_T2();
1987
1988 if (op < 3) /* store */
1989 gen_movl_T0_reg(s, rd);
1990
1991 switch (op) {
1992 case 0: /* str */
b5ff1b31 1993 gen_ldst(stl, s);
99c475ab
FB		 1994 break;
1995 case 1: /* strh */
b5ff1b31 1996 gen_ldst(stw, s);
99c475ab
FB		 1997 break;
1998 case 2: /* strb */
b5ff1b31 1999 gen_ldst(stb, s);
99c475ab
FB		 2000 break;
2001 case 3: /* ldrsb */
b5ff1b31 2002 gen_ldst(ldsb, s);
99c475ab
FB		 2003 break;
2004 case 4: /* ldr */
b5ff1b31 2005 gen_ldst(ldl, s);
99c475ab
FB		 2006 break;
2007 case 5: /* ldrh */
b5ff1b31 2008 gen_ldst(lduw, s);
99c475ab
FB		 2009 break;
2010 case 6: /* ldrb */
b5ff1b31 2011 gen_ldst(ldub, s);
99c475ab
FB		 2012 break;
2013 case 7: /* ldrsh */
b5ff1b31 2014 gen_ldst(ldsw, s);
99c475ab
FB		 2015 break;
2016 }
2017 if (op >= 3) /* load */
2018 gen_movl_reg_T0(s, rd);
2019 break;
2020
2021 case 6:
2022 /* load/store word immediate offset */
2023 rd = insn & 7;
2024 rn = (insn >> 3) & 7;
2025 gen_movl_T1_reg(s, rn);
2026 val = (insn >> 4) & 0x7c;
2027 gen_op_movl_T2_im(val);
2028 gen_op_addl_T1_T2();
2029
2030 if (insn & (1 << 11)) {
2031 /* load */
b5ff1b31 2032 gen_ldst(ldl, s);
99c475ab
FB		 2033 gen_movl_reg_T0(s, rd);
2034 } else {
2035 /* store */
2036 gen_movl_T0_reg(s, rd);
b5ff1b31 2037 gen_ldst(stl, s);
99c475ab
FB		 2038 }
2039 break;
2040
2041 case 7:
2042 /* load/store byte immediate offset */
2043 rd = insn & 7;
2044 rn = (insn >> 3) & 7;
2045 gen_movl_T1_reg(s, rn);
2046 val = (insn >> 6) & 0x1f;
2047 gen_op_movl_T2_im(val);
2048 gen_op_addl_T1_T2();
2049
2050 if (insn & (1 << 11)) {
2051 /* load */
b5ff1b31 2052 gen_ldst(ldub, s);
99c475ab
FB		 2053 gen_movl_reg_T0(s, rd);
2054 } else {
2055 /* store */
2056 gen_movl_T0_reg(s, rd);
b5ff1b31 2057 gen_ldst(stb, s);
99c475ab
FB		 2058 }
2059 break;
2060
2061 case 8:
2062 /* load/store halfword immediate offset */
2063 rd = insn & 7;
2064 rn = (insn >> 3) & 7;
2065 gen_movl_T1_reg(s, rn);
2066 val = (insn >> 5) & 0x3e;
2067 gen_op_movl_T2_im(val);
2068 gen_op_addl_T1_T2();
2069
2070 if (insn & (1 << 11)) {
2071 /* load */
b5ff1b31 2072 gen_ldst(lduw, s);
99c475ab
FB		 2073 gen_movl_reg_T0(s, rd);
2074 } else {
2075 /* store */
2076 gen_movl_T0_reg(s, rd);
b5ff1b31 2077 gen_ldst(stw, s);
99c475ab
FB		 2078 }
2079 break;
2080
2081 case 9:
2082 /* load/store from stack */
2083 rd = (insn >> 8) & 7;
2084 gen_movl_T1_reg(s, 13);
2085 val = (insn & 0xff) * 4;
2086 gen_op_movl_T2_im(val);
2087 gen_op_addl_T1_T2();
2088
2089 if (insn & (1 << 11)) {
2090 /* load */
b5ff1b31 2091 gen_ldst(ldl, s);
99c475ab
FB		 2092 gen_movl_reg_T0(s, rd);
2093 } else {
2094 /* store */
2095 gen_movl_T0_reg(s, rd);
b5ff1b31 2096 gen_ldst(stl, s);
99c475ab
FB		 2097 }
2098 break;
2099
2100 case 10:
2101 /* add to high reg */
2102 rd = (insn >> 8) & 7;
5899f386
FB		 2103 if (insn & (1 << 11)) {
2104 /* SP */
2105 gen_movl_T0_reg(s, 13);
2106 } else {
2107 /* PC. bit 1 is ignored. */
2108 gen_op_movl_T0_im((s->pc + 2) & ~(uint32_t)2);
2109 }
99c475ab
FB		 2110 val = (insn & 0xff) * 4;
2111 gen_op_movl_T1_im(val);
2112 gen_op_addl_T0_T1();
2113 gen_movl_reg_T0(s, rd);
2114 break;
2115
2116 case 11:
2117 /* misc */
2118 op = (insn >> 8) & 0xf;
2119 switch (op) {
2120 case 0:
2121 /* adjust stack pointer */
2122 gen_movl_T1_reg(s, 13);
2123 val = (insn & 0x7f) * 4;
2124 if (insn & (1 << 7))
2125 val = -(int32_t)val;
2126 gen_op_movl_T2_im(val);
2127 gen_op_addl_T1_T2();
2128 gen_movl_reg_T1(s, 13);
2129 break;
2130
2131 case 4: case 5: case 0xc: case 0xd:
2132 /* push/pop */
2133 gen_movl_T1_reg(s, 13);
5899f386
FB		 2134 if (insn & (1 << 8))
2135 offset = 4;
99c475ab 2136 else
5899f386
FB		 2137 offset = 0;
2138 for (i = 0; i < 8; i++) {
2139 if (insn & (1 << i))
2140 offset += 4;
2141 }
2142 if ((insn & (1 << 11)) == 0) {
2143 gen_op_movl_T2_im(-offset);
2144 gen_op_addl_T1_T2();
2145 }
2146 gen_op_movl_T2_im(4);
99c475ab
FB		 2147 for (i = 0; i < 8; i++) {
2148 if (insn & (1 << i)) {
2149 if (insn & (1 << 11)) {
2150 /* pop */
b5ff1b31 2151 gen_ldst(ldl, s);
99c475ab
FB		 2152 gen_movl_reg_T0(s, i);
2153 } else {
2154 /* push */
2155 gen_movl_T0_reg(s, i);
b5ff1b31 2156 gen_ldst(stl, s);
99c475ab 2157 }
5899f386 2158 /* advance to the next address. */
99c475ab
FB		 2159 gen_op_addl_T1_T2();
2160 }
2161 }
2162 if (insn & (1 << 8)) {
2163 if (insn & (1 << 11)) {
2164 /* pop pc */
b5ff1b31 2165 gen_ldst(ldl, s);
99c475ab
FB		 2166 /* don't set the pc until the rest of the instruction
2167 has completed */
2168 } else {
2169 /* push lr */
2170 gen_movl_T0_reg(s, 14);
b5ff1b31 2171 gen_ldst(stl, s);
99c475ab
FB		 2172 }
2173 gen_op_addl_T1_T2();
2174 }
5899f386
FB		 2175 if ((insn & (1 << 11)) == 0) {
2176 gen_op_movl_T2_im(-offset);
2177 gen_op_addl_T1_T2();
2178 }
99c475ab
FB		 2179 /* write back the new stack pointer */
2180 gen_movl_reg_T1(s, 13);
2181 /* set the new PC value */
2182 if ((insn & 0x0900) == 0x0900)
2183 gen_bx(s);
2184 break;
2185
2186 default:
2187 goto undef;
2188 }
2189 break;
2190
2191 case 12:
2192 /* load/store multiple */
2193 rn = (insn >> 8) & 0x7;
2194 gen_movl_T1_reg(s, rn);
2195 gen_op_movl_T2_im(4);
99c475ab
FB		 2196 for (i = 0; i < 8; i++) {
2197 if (insn & (1 << i)) {
99c475ab
FB		 2198 if (insn & (1 << 11)) {
2199 /* load */
b5ff1b31 2200 gen_ldst(ldl, s);
99c475ab
FB		 2201 gen_movl_reg_T0(s, i);
2202 } else {
2203 /* store */
2204 gen_movl_T0_reg(s, i);
b5ff1b31 2205 gen_ldst(stl, s);
99c475ab 2206 }
5899f386
FB		 2207 /* advance to the next address */
2208 gen_op_addl_T1_T2();
99c475ab
FB		 2209 }
2210 }
5899f386 2211 /* Base register writeback. */
b5ff1b31
FB		 2212 if ((insn & (1 << rn)) == 0)
2213 gen_movl_reg_T1(s, rn);
99c475ab
FB		 2214 break;
2215
2216 case 13:
2217 /* conditional branch or swi */
2218 cond = (insn >> 8) & 0xf;
2219 if (cond == 0xe)
2220 goto undef;
2221
2222 if (cond == 0xf) {
2223 /* swi */
2224 gen_op_movl_T0_im((long)s->pc | 1);
2225 /* Don't set r15. */
2226 gen_op_movl_reg_TN[0][15]();
2227 gen_op_swi();
2228 s->is_jmp = DISAS_JUMP;
2229 break;
2230 }
2231 /* generate a conditional jump to next instruction */
e50e6a20
FB		 2232 s->condlabel = gen_new_label();
2233 gen_test_cc[cond ^ 1](s->condlabel);
2234 s->condjmp = 1;
2235 //gen_test_cc[cond ^ 1]((long)s->tb, (long)s->pc);
2236 //s->is_jmp = DISAS_JUMP_NEXT;
99c475ab
FB		 2237 gen_movl_T1_reg(s, 15);
2238
2239 /* jump to the offset */
5899f386 2240 val = (uint32_t)s->pc + 2;
99c475ab 2241 offset = ((int32_t)insn << 24) >> 24;
5899f386 2242 val += offset << 1;
8aaca4c0 2243 gen_jmp(s, val);
99c475ab
FB		 2244 break;
2245
2246 case 14:
2247 /* unconditional branch */
2248 if (insn & (1 << 11))
2249 goto undef; /* Second half of a blx */
2250 val = (uint32_t)s->pc;
2251 offset = ((int32_t)insn << 21) >> 21;
2252 val += (offset << 1) + 2;
8aaca4c0 2253 gen_jmp(s, val);
99c475ab
FB		 2254 break;
2255
2256 case 15:
2257 /* branch and link [and switch to arm] */
2258 offset = ((int32_t)insn << 21) >> 10;
b5ff1b31 2259 insn = lduw_code(s->pc);
99c475ab
FB		 2260 offset |= insn & 0x7ff;
2261
2262 val = (uint32_t)s->pc + 2;
2263 gen_op_movl_T1_im(val | 1);
2264 gen_movl_reg_T1(s, 14);
2265
5899f386 2266 val += offset << 1;
2531fc7b 2267 if (insn & (1 << 12)) {
99c475ab 2268 /* bl */
8aaca4c0 2269 gen_jmp(s, val);
99c475ab
FB		 2270 } else {
2271 /* blx */
5899f386 2272 val &= ~(uint32_t)2;
99c475ab
FB		 2273 gen_op_movl_T0_im(val);
2274 gen_bx(s);
2275 }
2276 }
2277 return;
2278undef:
5899f386 2279 gen_op_movl_T0_im((long)s->pc - 2);
99c475ab
FB		 2280 gen_op_movl_reg_TN[0][15]();
2281 gen_op_undef_insn();
2282 s->is_jmp = DISAS_JUMP;
2283}
2284
2c0262af
FB		 2285/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
2286 basic block 'tb'. If search_pc is TRUE, also generate PC
2287 information for each intermediate instruction. */
2288static inline int gen_intermediate_code_internal(CPUState *env,
2289 TranslationBlock *tb,
2290 int search_pc)
2291{
2292 DisasContext dc1, *dc = &dc1;
2293 uint16_t *gen_opc_end;
2294 int j, lj;
0fa85d43 2295 target_ulong pc_start;
b5ff1b31 2296 uint32_t next_page_start;
2c0262af
FB		 2297
2298 /* generate intermediate code */
0fa85d43 2299 pc_start = tb->pc;
2c0262af
FB		 2300
2301 dc->tb = tb;
2302
2303 gen_opc_ptr = gen_opc_buf;
2304 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2305 gen_opparam_ptr = gen_opparam_buf;
2306
2307 dc->is_jmp = DISAS_NEXT;
2308 dc->pc = pc_start;
8aaca4c0 2309 dc->singlestep_enabled = env->singlestep_enabled;
e50e6a20 2310 dc->condjmp = 0;
5899f386 2311 dc->thumb = env->thumb;
b5ff1b31
FB		 2312#if !defined(CONFIG_USER_ONLY)
2313 dc->user = (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR;
2314#endif
2315 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
e50e6a20 2316 nb_gen_labels = 0;
2c0262af
FB		 2317 lj = -1;
2318 do {
1fddef4b
FB		 2319 if (env->nb_breakpoints > 0) {
2320 for(j = 0; j < env->nb_breakpoints; j++) {
2321 if (env->breakpoints[j] == dc->pc) {
2322 gen_op_movl_T0_im((long)dc->pc);
2323 gen_op_movl_reg_TN[0][15]();
2324 gen_op_debug();
2325 dc->is_jmp = DISAS_JUMP;
2326 break;
2327 }
2328 }
2329 }
2c0262af
FB		 2330 if (search_pc) {
2331 j = gen_opc_ptr - gen_opc_buf;
2332 if (lj < j) {
2333 lj++;
2334 while (lj < j)
2335 gen_opc_instr_start[lj++] = 0;
2336 }
0fa85d43 2337 gen_opc_pc[lj] = dc->pc;
2c0262af
FB		 2338 gen_opc_instr_start[lj] = 1;
2339 }
e50e6a20 2340
99c475ab
FB		 2341 if (env->thumb)
2342 disas_thumb_insn(dc);
2343 else
b7bcbe95 2344 disas_arm_insn(env, dc);
e50e6a20
FB		 2345
2346 if (dc->condjmp && !dc->is_jmp) {
2347 gen_set_label(dc->condlabel);
2348 dc->condjmp = 0;
2349 }
2350 /* Translation stops when a conditional branch is enoutered.
2351 * Otherwise the subsequent code could get translated several times.
b5ff1b31
FB		 2352 * Also stop translation when a page boundary is reached. This
2353 * ensures prefech aborts occur at the right place. */
1fddef4b
FB		 2354 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
2355 !env->singlestep_enabled &&
b5ff1b31
FB		 2356 dc->pc < next_page_start);
2357 /* At this stage dc->condjmp will only be set when the skipped
2358 * instruction was a conditional branch, and the PC has already been
e50e6a20 2359 * written. */
8aaca4c0
FB		 2360 if (__builtin_expect(env->singlestep_enabled, 0)) {
2361 /* Make sure the pc is updated, and raise a debug exception. */
e50e6a20
FB		 2362 if (dc->condjmp) {
2363 gen_op_debug();
2364 gen_set_label(dc->condlabel);
2365 }
2366 if (dc->condjmp || !dc->is_jmp) {
8aaca4c0
FB		 2367 gen_op_movl_T0_im((long)dc->pc);
2368 gen_op_movl_reg_TN[0][15]();
e50e6a20 2369 dc->condjmp = 0;
8aaca4c0
FB		 2370 }
2371 gen_op_debug();
2372 } else {
2373 switch(dc->is_jmp) {
8aaca4c0 2374 case DISAS_NEXT:
6e256c93 2375 gen_goto_tb(dc, 1, dc->pc);
8aaca4c0
FB		 2376 break;
2377 default:
2378 case DISAS_JUMP:
2379 case DISAS_UPDATE:
2380 /* indicate that the hash table must be used to find the next TB */
2381 gen_op_movl_T0_0();
2382 gen_op_exit_tb();
2383 break;
2384 case DISAS_TB_JUMP:
2385 /* nothing more to generate */
2386 break;
2387 }
e50e6a20
FB		 2388 if (dc->condjmp) {
2389 gen_set_label(dc->condlabel);
6e256c93 2390 gen_goto_tb(dc, 1, dc->pc);
e50e6a20
FB		 2391 dc->condjmp = 0;
2392 }
2c0262af
FB		 2393 }
2394 *gen_opc_ptr = INDEX_op_end;
2395
2396#ifdef DEBUG_DISAS
e19e89a5 2397 if (loglevel & CPU_LOG_TB_IN_ASM) {
2c0262af
FB		 2398 fprintf(logfile, "----------------\n");
2399 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
5899f386 2400 target_disas(logfile, pc_start, dc->pc - pc_start, env->thumb);
2c0262af 2401 fprintf(logfile, "\n");
e19e89a5
FB		 2402 if (loglevel & (CPU_LOG_TB_OP)) {
2403 fprintf(logfile, "OP:\n");
2404 dump_ops(gen_opc_buf, gen_opparam_buf);
2405 fprintf(logfile, "\n");
2406 }
2c0262af
FB		 2407 }
2408#endif
b5ff1b31
FB		 2409 if (search_pc) {
2410 j = gen_opc_ptr - gen_opc_buf;
2411 lj++;
2412 while (lj <= j)
2413 gen_opc_instr_start[lj++] = 0;
2414 tb->size = 0;
2415 } else {
2c0262af 2416 tb->size = dc->pc - pc_start;
b5ff1b31 2417 }
2c0262af
FB		 2418 return 0;
2419}
2420
2421int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
2422{
2423 return gen_intermediate_code_internal(env, tb, 0);
2424}
2425
2426int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
2427{
2428 return gen_intermediate_code_internal(env, tb, 1);
2429}
2430
b5ff1b31
FB		 2431void cpu_reset(CPUARMState *env)
2432{
2433#if defined (CONFIG_USER_ONLY)
2434 /* SVC mode with interrupts disabled. */
2435 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
2436#else
2437 env->uncached_cpsr = ARM_CPU_MODE_USR;
2438#endif
2439 env->regs[15] = 0;
2440}
2441
2c0262af
FB		 2442CPUARMState *cpu_arm_init(void)
2443{
2444 CPUARMState *env;
2445
173d6cfe 2446 env = qemu_mallocz(sizeof(CPUARMState));
2c0262af
FB		 2447 if (!env)
2448 return NULL;
173d6cfe 2449 cpu_exec_init(env);
b5ff1b31
FB		 2450 cpu_reset(env);
2451 tlb_flush(env, 1);
2c0262af
FB		 2452 return env;
2453}
2454
2455void cpu_arm_close(CPUARMState *env)
2456{
2457 free(env);
2458}
2459
b5ff1b31
FB		 2460static const char *cpu_mode_names[16] = {
2461 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
2462 "???", "???", "???", "und", "???", "???", "???", "sys"
2463};
7fe48483
FB		 2464void cpu_dump_state(CPUState *env, FILE *f,
2465 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2466 int flags)
2c0262af
FB		 2467{
2468 int i;
bc380d17 2469 union {
b7bcbe95
FB		 2470 uint32_t i;
2471 float s;
2472 } s0, s1;
2473 CPU_DoubleU d;
b5ff1b31 2474 uint32_t psr;
2c0262af
FB		 2475
2476 for(i=0;i<16;i++) {
7fe48483 2477 cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]);
2c0262af 2478 if ((i % 4) == 3)
7fe48483 2479 cpu_fprintf(f, "\n");
2c0262af 2480 else
7fe48483 2481 cpu_fprintf(f, " ");
2c0262af 2482 }
b5ff1b31
FB		 2483 psr = cpsr_read(env);
2484 cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d %x\n",
2485 psr,
2486 psr & (1 << 31) ? 'N' : '-',
2487 psr & (1 << 30) ? 'Z' : '-',
2488 psr & (1 << 29) ? 'C' : '-',
2489 psr & (1 << 28) ? 'V' : '-',
2490 psr & CPSR_T ? 'T' : 'A',
2491 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
b7bcbe95
FB		 2492
2493 for (i = 0; i < 16; i++) {
8e96005d
FB		 2494 d.d = env->vfp.regs[i];
2495 s0.i = d.l.lower;
2496 s1.i = d.l.upper;
b7bcbe95
FB		 2497 cpu_fprintf(f, "s%02d=%08x(%8f) s%02d=%08x(%8f) d%02d=%08x%08x(%8f)\n",
2498 i * 2, (int)s0.i, s0.s,
2499 i * 2 + 1, (int)s0.i, s0.s,
2500 i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower,
2501 d.d);
b7bcbe95 2502 }
74c161bd 2503 cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.fpscr);
2c0262af 2504}
a6b025d3 2505
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