[qemu.git] / hw / misc / zynq_slcr.c

/*
 * Status and system control registers for Xilinx Zynq Platform
 *
 * Copyright (c) 2011 Michal Simek <[email protected]>
 * Copyright (c) 2012 PetaLogix Pty Ltd.
 * Based on hw/arm_sysctl.c, written by Paul Brook
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "hw/hw.h"
#include "qemu/timer.h"
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "qemu/log.h"

#ifndef ZYNQ_SLCR_ERR_DEBUG
#define ZYNQ_SLCR_ERR_DEBUG 0
#endif

#define DB_PRINT(...) do { \
        if (ZYNQ_SLCR_ERR_DEBUG) { \
            fprintf(stderr,  ": %s: ", __func__); \
            fprintf(stderr, ## __VA_ARGS__); \
        } \
    } while (0);

#define XILINX_LOCK_KEY 0x767b
#define XILINX_UNLOCK_KEY 0xdf0d

#define R_PSS_RST_CTRL_SOFT_RST 0x1

enum {
    SCL             = 0x000 / 4,
    LOCK,
    UNLOCK,
    LOCKSTA,

    ARM_PLL_CTRL    = 0x100 / 4,
    DDR_PLL_CTRL,
    IO_PLL_CTRL,
    PLL_STATUS,
    ARM_PLL_CFG,
    DDR_PLL_CFG,
    IO_PLL_CFG,

    ARM_CLK_CTRL    = 0x120 / 4,
    DDR_CLK_CTRL,
    DCI_CLK_CTRL,
    APER_CLK_CTRL,
    USB0_CLK_CTRL,
    USB1_CLK_CTRL,
    GEM0_RCLK_CTRL,
    GEM1_RCLK_CTRL,
    GEM0_CLK_CTRL,
    GEM1_CLK_CTRL,
    SMC_CLK_CTRL,
    LQSPI_CLK_CTRL,
    SDIO_CLK_CTRL,
    UART_CLK_CTRL,
    SPI_CLK_CTRL,
    CAN_CLK_CTRL,
    CAN_MIOCLK_CTRL,
    DBG_CLK_CTRL,
    PCAP_CLK_CTRL,
    TOPSW_CLK_CTRL,

#define FPGA_CTRL_REGS(n, start) \
    FPGA ## n ## _CLK_CTRL = (start) / 4, \
    FPGA ## n ## _THR_CTRL, \
    FPGA ## n ## _THR_CNT, \
    FPGA ## n ## _THR_STA,
    FPGA_CTRL_REGS(0, 0x170)
    FPGA_CTRL_REGS(1, 0x180)
    FPGA_CTRL_REGS(2, 0x190)
    FPGA_CTRL_REGS(3, 0x1a0)

    BANDGAP_TRIP    = 0x1b8 / 4,
    PLL_PREDIVISOR  = 0x1c0 / 4,
    CLK_621_TRUE,

    PSS_RST_CTRL    = 0x200 / 4,
    DDR_RST_CTRL,
    TOPSW_RESET_CTRL,
    DMAC_RST_CTRL,
    USB_RST_CTRL,
    GEM_RST_CTRL,
    SDIO_RST_CTRL,
    SPI_RST_CTRL,
    CAN_RST_CTRL,
    I2C_RST_CTRL,
    UART_RST_CTRL,
    GPIO_RST_CTRL,
    LQSPI_RST_CTRL,
    SMC_RST_CTRL,
    OCM_RST_CTRL,
    FPGA_RST_CTRL   = 0x240 / 4,
    A9_CPU_RST_CTRL,

    RS_AWDT_CTRL    = 0x24c / 4,
    RST_REASON,

    REBOOT_STATUS   = 0x258 / 4,
    BOOT_MODE,

    APU_CTRL        = 0x300 / 4,
    WDT_CLK_SEL,

    TZ_DMA_NS       = 0x440 / 4,
    TZ_DMA_IRQ_NS,
    TZ_DMA_PERIPH_NS,

    PSS_IDCODE      = 0x530 / 4,

    DDR_URGENT      = 0x600 / 4,
    DDR_CAL_START   = 0x60c / 4,
    DDR_REF_START   = 0x614 / 4,
    DDR_CMD_STA,
    DDR_URGENT_SEL,
    DDR_DFI_STATUS,

    MIO             = 0x700 / 4,
#define MIO_LENGTH 54

    MIO_LOOPBACK    = 0x804 / 4,
    MIO_MST_TRI0,
    MIO_MST_TRI1,

    SD0_WP_CD_SEL   = 0x830 / 4,
    SD1_WP_CD_SEL,

    LVL_SHFTR_EN    = 0x900 / 4,
    OCM_CFG         = 0x910 / 4,

    CPU_RAM         = 0xa00 / 4,

    IOU             = 0xa30 / 4,

    DMAC_RAM        = 0xa50 / 4,

    AFI0            = 0xa60 / 4,
    AFI1 = AFI0 + 3,
    AFI2 = AFI1 + 3,
    AFI3 = AFI2 + 3,
#define AFI_LENGTH 3

    OCM             = 0xa90 / 4,

    DEVCI_RAM       = 0xaa0 / 4,

    CSG_RAM         = 0xab0 / 4,

    GPIOB_CTRL      = 0xb00 / 4,
    GPIOB_CFG_CMOS18,
    GPIOB_CFG_CMOS25,
    GPIOB_CFG_CMOS33,
    GPIOB_CFG_HSTL  = 0xb14 / 4,
    GPIOB_DRVR_BIAS_CTRL,

    DDRIOB          = 0xb40 / 4,
#define DDRIOB_LENGTH 14
};

#define ZYNQ_SLCR_MMIO_SIZE     0x1000
#define ZYNQ_SLCR_NUM_REGS      (ZYNQ_SLCR_MMIO_SIZE / 4)

#define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
#define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)

typedef struct ZynqSLCRState {
    SysBusDevice parent_obj;

    MemoryRegion iomem;

    uint32_t regs[ZYNQ_SLCR_NUM_REGS];
} ZynqSLCRState;

static void zynq_slcr_reset(DeviceState *d)
{
    ZynqSLCRState *s = ZYNQ_SLCR(d);
    int i;

    DB_PRINT("RESET\n");

    s->regs[LOCKSTA] = 1;
    /* 0x100 - 0x11C */
    s->regs[ARM_PLL_CTRL]   = 0x0001A008;
    s->regs[DDR_PLL_CTRL]   = 0x0001A008;
    s->regs[IO_PLL_CTRL]    = 0x0001A008;
    s->regs[PLL_STATUS]     = 0x0000003F;
    s->regs[ARM_PLL_CFG]    = 0x00014000;
    s->regs[DDR_PLL_CFG]    = 0x00014000;
    s->regs[IO_PLL_CFG]     = 0x00014000;

    /* 0x120 - 0x16C */
    s->regs[ARM_CLK_CTRL]   = 0x1F000400;
    s->regs[DDR_CLK_CTRL]   = 0x18400003;
    s->regs[DCI_CLK_CTRL]   = 0x01E03201;
    s->regs[APER_CLK_CTRL]  = 0x01FFCCCD;
    s->regs[USB0_CLK_CTRL]  = s->regs[USB1_CLK_CTRL]    = 0x00101941;
    s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL]   = 0x00000001;
    s->regs[GEM0_CLK_CTRL]  = s->regs[GEM1_CLK_CTRL]    = 0x00003C01;
    s->regs[SMC_CLK_CTRL]   = 0x00003C01;
    s->regs[LQSPI_CLK_CTRL] = 0x00002821;
    s->regs[SDIO_CLK_CTRL]  = 0x00001E03;
    s->regs[UART_CLK_CTRL]  = 0x00003F03;
    s->regs[SPI_CLK_CTRL]   = 0x00003F03;
    s->regs[CAN_CLK_CTRL]   = 0x00501903;
    s->regs[DBG_CLK_CTRL]   = 0x00000F03;
    s->regs[PCAP_CLK_CTRL]  = 0x00000F01;

    /* 0x170 - 0x1AC */
    s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL]
                            = s->regs[FPGA3_CLK_CTRL] = 0x00101800;
    s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA]
                           = s->regs[FPGA3_THR_STA] = 0x00010000;

    /* 0x1B0 - 0x1D8 */
    s->regs[BANDGAP_TRIP]   = 0x0000001F;
    s->regs[PLL_PREDIVISOR] = 0x00000001;
    s->regs[CLK_621_TRUE]   = 0x00000001;

    /* 0x200 - 0x25C */
    s->regs[FPGA_RST_CTRL]  = 0x01F33F0F;
    s->regs[RST_REASON]     = 0x00000040;

    s->regs[BOOT_MODE]      = 0x00000001;

    /* 0x700 - 0x7D4 */
    for (i = 0; i < 54; i++) {
        s->regs[MIO + i] = 0x00001601;
    }
    for (i = 2; i <= 8; i++) {
        s->regs[MIO + i] = 0x00000601;
    }

    s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF;

    s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3]
                         = s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7]
                         = 0x00010101;
    s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101;
    s->regs[CPU_RAM + 6] = 0x00000001;

    s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3]
                     = 0x09090909;
    s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909;
    s->regs[IOU + 6] = 0x00000909;

    s->regs[DMAC_RAM] = 0x00000009;

    s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909;
    s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909;
    s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909;
    s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909;
    s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2]
                      = s->regs[AFI3 + 2] = 0x00000909;

    s->regs[OCM + 0]    = 0x01010101;
    s->regs[OCM + 1]    = s->regs[OCM + 2] = 0x09090909;

    s->regs[DEVCI_RAM]  = 0x00000909;
    s->regs[CSG_RAM]    = 0x00000001;

    s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2]
                        = s->regs[DDRIOB + 3] = 0x00000e00;
    s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6]
                        = 0x00000e00;
    s->regs[DDRIOB + 12] = 0x00000021;
}


static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
{
    switch (offset) {
    case LOCK:
    case UNLOCK:
    case DDR_CAL_START:
    case DDR_REF_START:
        return !rnw; /* Write only */
    case LOCKSTA:
    case FPGA0_THR_STA:
    case FPGA1_THR_STA:
    case FPGA2_THR_STA:
    case FPGA3_THR_STA:
    case BOOT_MODE:
    case PSS_IDCODE:
    case DDR_CMD_STA:
    case DDR_DFI_STATUS:
    case PLL_STATUS:
        return rnw;/* read only */
    case SCL:
    case ARM_PLL_CTRL ... IO_PLL_CTRL:
    case ARM_PLL_CFG ... IO_PLL_CFG:
    case ARM_CLK_CTRL ... TOPSW_CLK_CTRL:
    case FPGA0_CLK_CTRL ... FPGA0_THR_CNT:
    case FPGA1_CLK_CTRL ... FPGA1_THR_CNT:
    case FPGA2_CLK_CTRL ... FPGA2_THR_CNT:
    case FPGA3_CLK_CTRL ... FPGA3_THR_CNT:
    case BANDGAP_TRIP:
    case PLL_PREDIVISOR:
    case CLK_621_TRUE:
    case PSS_RST_CTRL ... A9_CPU_RST_CTRL:
    case RS_AWDT_CTRL:
    case RST_REASON:
    case REBOOT_STATUS:
    case APU_CTRL:
    case WDT_CLK_SEL:
    case TZ_DMA_NS ... TZ_DMA_PERIPH_NS:
    case DDR_URGENT:
    case DDR_URGENT_SEL:
    case MIO ... MIO + MIO_LENGTH - 1:
    case MIO_LOOPBACK ... MIO_MST_TRI1:
    case SD0_WP_CD_SEL:
    case SD1_WP_CD_SEL:
    case LVL_SHFTR_EN:
    case OCM_CFG:
    case CPU_RAM:
    case IOU:
    case DMAC_RAM:
    case AFI0 ... AFI3 + AFI_LENGTH - 1:
    case OCM:
    case DEVCI_RAM:
    case CSG_RAM:
    case GPIOB_CTRL ... GPIOB_CFG_CMOS33:
    case GPIOB_CFG_HSTL:
    case GPIOB_DRVR_BIAS_CTRL:
    case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1:
        return true;
    default:
        return false;
    }
}

static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
    unsigned size)
{
    ZynqSLCRState *s = opaque;
    offset /= 4;
    uint32_t ret = s->regs[offset];

    if (!zynq_slcr_check_offset(offset, true)) {
        qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to "
                      " addr %" HWADDR_PRIx "\n", offset * 4);
    }

    DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret);
    return ret;
}

static void zynq_slcr_write(void *opaque, hwaddr offset,
                          uint64_t val, unsigned size)
{
    ZynqSLCRState *s = (ZynqSLCRState *)opaque;
    offset /= 4;

    DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val);

    if (!zynq_slcr_check_offset(offset, false)) {
        qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid write access to "
                      "addr %" HWADDR_PRIx "\n", offset * 4);
        return;
    }

    switch (offset) {
    case SCL:
        s->regs[SCL] = val & 0x1;
        return;
    case LOCK:
        if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
            DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
                (unsigned)val & 0xFFFF);
            s->regs[LOCKSTA] = 1;
        } else {
            DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
                (int)offset, (unsigned)val & 0xFFFF);
        }
        return;
    case UNLOCK:
        if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
            DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
                (unsigned)val & 0xFFFF);
            s->regs[LOCKSTA] = 0;
        } else {
            DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
                (int)offset, (unsigned)val & 0xFFFF);
        }
        return;
    }

    if (s->regs[LOCKSTA]) {
        qemu_log_mask(LOG_GUEST_ERROR,
                      "SCLR registers are locked. Unlock them first\n");
        return;
    }
    s->regs[offset] = val;

    switch (offset) {
    case PSS_RST_CTRL:
        if (val & R_PSS_RST_CTRL_SOFT_RST) {
            qemu_system_reset_request();
        }
        break;
    }
}

static const MemoryRegionOps slcr_ops = {
    .read = zynq_slcr_read,
    .write = zynq_slcr_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void zynq_slcr_init(Object *obj)
{
    ZynqSLCRState *s = ZYNQ_SLCR(obj);

    memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr",
                          ZYNQ_SLCR_MMIO_SIZE);
    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
}

static const VMStateDescription vmstate_zynq_slcr = {
    .name = "zynq_slcr",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
        VMSTATE_END_OF_LIST()
    }
};

static void zynq_slcr_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->vmsd = &vmstate_zynq_slcr;
    dc->reset = zynq_slcr_reset;
}

static const TypeInfo zynq_slcr_info = {
    .class_init = zynq_slcr_class_init,
    .name  = TYPE_ZYNQ_SLCR,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size  = sizeof(ZynqSLCRState),
    .instance_init = zynq_slcr_init,
};

static void zynq_slcr_register_types(void)
{
    type_register_static(&zynq_slcr_info);
}

type_init(zynq_slcr_register_types)
Commit	Line	Data
e3260506 PC	1	/*
	2	* Status and system control registers for Xilinx Zynq Platform
	3	*
	4	* Copyright (c) 2011 Michal Simek <[email protected]>
	5	* Copyright (c) 2012 PetaLogix Pty Ltd.
	6	* Based on hw/arm_sysctl.c, written by Paul Brook
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version
	11	* 2 of the License, or (at your option) any later version.
	12	*
	13	* You should have received a copy of the GNU General Public License along
	14	* with this program; if not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
8ef94f0b	17	#include "qemu/osdep.h"
83c9f4ca	18	#include "hw/hw.h"
1de7afc9	19	#include "qemu/timer.h"
83c9f4ca	20	#include "hw/sysbus.h"
9c17d615	21	#include "sysemu/sysemu.h"
03dd024f	22	#include "qemu/log.h"
e3260506	23
6954a1cd PC	24	#ifndef ZYNQ_SLCR_ERR_DEBUG
	25	#define ZYNQ_SLCR_ERR_DEBUG 0
	26	#endif
	27
e3260506	28	#define DB_PRINT(...) do { \
6954a1cd PC	29	if (ZYNQ_SLCR_ERR_DEBUG) { \
	30	fprintf(stderr, ": %s: ", __func__); \
	31	fprintf(stderr, ## __VA_ARGS__); \
	32	} \
e3260506	33	} while (0);
e3260506 PC	34
	35	#define XILINX_LOCK_KEY 0x767b
	36	#define XILINX_UNLOCK_KEY 0xdf0d
	37
69991d7d SH	38	#define R_PSS_RST_CTRL_SOFT_RST 0x1
69991d7d SH	39
db302f8f PC	40	enum {
	41	SCL = 0x000 / 4,
	42	LOCK,
	43	UNLOCK,
	44	LOCKSTA,
	45
	46	ARM_PLL_CTRL = 0x100 / 4,
	47	DDR_PLL_CTRL,
	48	IO_PLL_CTRL,
	49	PLL_STATUS,
	50	ARM_PLL_CFG,
	51	DDR_PLL_CFG,
	52	IO_PLL_CFG,
	53
	54	ARM_CLK_CTRL = 0x120 / 4,
	55	DDR_CLK_CTRL,
	56	DCI_CLK_CTRL,
	57	APER_CLK_CTRL,
	58	USB0_CLK_CTRL,
	59	USB1_CLK_CTRL,
	60	GEM0_RCLK_CTRL,
	61	GEM1_RCLK_CTRL,
	62	GEM0_CLK_CTRL,
	63	GEM1_CLK_CTRL,
	64	SMC_CLK_CTRL,
	65	LQSPI_CLK_CTRL,
	66	SDIO_CLK_CTRL,
	67	UART_CLK_CTRL,
	68	SPI_CLK_CTRL,
	69	CAN_CLK_CTRL,
	70	CAN_MIOCLK_CTRL,
	71	DBG_CLK_CTRL,
	72	PCAP_CLK_CTRL,
	73	TOPSW_CLK_CTRL,
	74
	75	#define FPGA_CTRL_REGS(n, start) \
	76	FPGA ## n ## _CLK_CTRL = (start) / 4, \
	77	FPGA ## n ## _THR_CTRL, \
	78	FPGA ## n ## _THR_CNT, \
	79	FPGA ## n ## _THR_STA,
	80	FPGA_CTRL_REGS(0, 0x170)
	81	FPGA_CTRL_REGS(1, 0x180)
	82	FPGA_CTRL_REGS(2, 0x190)
	83	FPGA_CTRL_REGS(3, 0x1a0)
	84
	85	BANDGAP_TRIP = 0x1b8 / 4,
	86	PLL_PREDIVISOR = 0x1c0 / 4,
	87	CLK_621_TRUE,
	88
	89	PSS_RST_CTRL = 0x200 / 4,
	90	DDR_RST_CTRL,
	91	TOPSW_RESET_CTRL,
	92	DMAC_RST_CTRL,
	93	USB_RST_CTRL,
	94	GEM_RST_CTRL,
	95	SDIO_RST_CTRL,
	96	SPI_RST_CTRL,
	97	CAN_RST_CTRL,
	98	I2C_RST_CTRL,
	99	UART_RST_CTRL,
	100	GPIO_RST_CTRL,
	101	LQSPI_RST_CTRL,
	102	SMC_RST_CTRL,
	103	OCM_RST_CTRL,
104	FPGA_RST_CTRL = 0x240 / 4,
105	A9_CPU_RST_CTRL,
106
107	RS_AWDT_CTRL = 0x24c / 4,
108	RST_REASON,
109
110	REBOOT_STATUS = 0x258 / 4,
111	BOOT_MODE,
112
113	APU_CTRL = 0x300 / 4,
114	WDT_CLK_SEL,
115
116	TZ_DMA_NS = 0x440 / 4,
117	TZ_DMA_IRQ_NS,
118	TZ_DMA_PERIPH_NS,
119
120	PSS_IDCODE = 0x530 / 4,
121
122	DDR_URGENT = 0x600 / 4,
123	DDR_CAL_START = 0x60c / 4,
124	DDR_REF_START = 0x614 / 4,
125	DDR_CMD_STA,
126	DDR_URGENT_SEL,
127	DDR_DFI_STATUS,
128
129	MIO = 0x700 / 4,
130	#define MIO_LENGTH 54
131
132	MIO_LOOPBACK = 0x804 / 4,
133	MIO_MST_TRI0,
134	MIO_MST_TRI1,
135
136	SD0_WP_CD_SEL = 0x830 / 4,
137	SD1_WP_CD_SEL,
138
139	LVL_SHFTR_EN = 0x900 / 4,
140	OCM_CFG = 0x910 / 4,
141
142	CPU_RAM = 0xa00 / 4,
143
144	IOU = 0xa30 / 4,
145
146	DMAC_RAM = 0xa50 / 4,
147
148	AFI0 = 0xa60 / 4,
149	AFI1 = AFI0 + 3,
150	AFI2 = AFI1 + 3,
151	AFI3 = AFI2 + 3,
152	#define AFI_LENGTH 3
153
154	OCM = 0xa90 / 4,
155
156	DEVCI_RAM = 0xaa0 / 4,
157
158	CSG_RAM = 0xab0 / 4,
159
160	GPIOB_CTRL = 0xb00 / 4,
161	GPIOB_CFG_CMOS18,
162	GPIOB_CFG_CMOS25,
163	GPIOB_CFG_CMOS33,
164	GPIOB_CFG_HSTL = 0xb14 / 4,
165	GPIOB_DRVR_BIAS_CTRL,
166
167	DDRIOB = 0xb40 / 4,
168	#define DDRIOB_LENGTH 14
169	};
170
171	#define ZYNQ_SLCR_MMIO_SIZE 0x1000
172	#define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4)
e3260506	173
a054e2c2 AF	174	#define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
	175	#define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
	176
	177	typedef struct ZynqSLCRState {
	178	SysBusDevice parent_obj;
	179
e3260506 PC	180	MemoryRegion iomem;
e3260506 PC	181
db302f8f	182	uint32_t regs[ZYNQ_SLCR_NUM_REGS];
e3260506 PC	183	} ZynqSLCRState;
	184
	185	static void zynq_slcr_reset(DeviceState *d)
	186	{
a054e2c2	187	ZynqSLCRState *s = ZYNQ_SLCR(d);
e3260506	188	int i;
e3260506 PC	189
	190	DB_PRINT("RESET\n");
	191
db302f8f	192	s->regs[LOCKSTA] = 1;
e3260506	193	/* 0x100 - 0x11C */
db302f8f PC	194	s->regs[ARM_PLL_CTRL] = 0x0001A008;
	195	s->regs[DDR_PLL_CTRL] = 0x0001A008;
	196	s->regs[IO_PLL_CTRL] = 0x0001A008;
	197	s->regs[PLL_STATUS] = 0x0000003F;
	198	s->regs[ARM_PLL_CFG] = 0x00014000;
	199	s->regs[DDR_PLL_CFG] = 0x00014000;
	200	s->regs[IO_PLL_CFG] = 0x00014000;
e3260506 PC	201
e3260506 PC	202	/* 0x120 - 0x16C */
db302f8f PC	203	s->regs[ARM_CLK_CTRL] = 0x1F000400;
	204	s->regs[DDR_CLK_CTRL] = 0x18400003;
	205	s->regs[DCI_CLK_CTRL] = 0x01E03201;
	206	s->regs[APER_CLK_CTRL] = 0x01FFCCCD;
	207	s->regs[USB0_CLK_CTRL] = s->regs[USB1_CLK_CTRL] = 0x00101941;
	208	s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL] = 0x00000001;
	209	s->regs[GEM0_CLK_CTRL] = s->regs[GEM1_CLK_CTRL] = 0x00003C01;
	210	s->regs[SMC_CLK_CTRL] = 0x00003C01;
	211	s->regs[LQSPI_CLK_CTRL] = 0x00002821;
	212	s->regs[SDIO_CLK_CTRL] = 0x00001E03;
	213	s->regs[UART_CLK_CTRL] = 0x00003F03;
	214	s->regs[SPI_CLK_CTRL] = 0x00003F03;
	215	s->regs[CAN_CLK_CTRL] = 0x00501903;
	216	s->regs[DBG_CLK_CTRL] = 0x00000F03;
	217	s->regs[PCAP_CLK_CTRL] = 0x00000F01;
e3260506 PC	218
e3260506 PC	219	/* 0x170 - 0x1AC */
db302f8f PC	220	s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL]
	221	= s->regs[FPGA3_CLK_CTRL] = 0x00101800;
	222	s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA]
	223	= s->regs[FPGA3_THR_STA] = 0x00010000;
e3260506 PC	224
e3260506 PC	225	/* 0x1B0 - 0x1D8 */
db302f8f PC	226	s->regs[BANDGAP_TRIP] = 0x0000001F;
	227	s->regs[PLL_PREDIVISOR] = 0x00000001;
	228	s->regs[CLK_621_TRUE] = 0x00000001;
e3260506 PC	229
e3260506 PC	230	/* 0x200 - 0x25C */
db302f8f PC	231	s->regs[FPGA_RST_CTRL] = 0x01F33F0F;
	232	s->regs[RST_REASON] = 0x00000040;
	233
	234	s->regs[BOOT_MODE] = 0x00000001;
e3260506 PC	235
	236	/* 0x700 - 0x7D4 */
	237	for (i = 0; i < 54; i++) {
db302f8f	238	s->regs[MIO + i] = 0x00001601;
e3260506 PC	239	}
e3260506 PC	240	for (i = 2; i <= 8; i++) {
db302f8f	241	s->regs[MIO + i] = 0x00000601;
e3260506 PC	242	}
e3260506 PC	243
db302f8f	244	s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF;
e3260506	245
db302f8f PC	246	s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3]
	247	= s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7]
	248	= 0x00010101;
	249	s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101;
	250	s->regs[CPU_RAM + 6] = 0x00000001;
e3260506	251
db302f8f PC	252	s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3]
	253	= 0x09090909;
	254	s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909;
	255	s->regs[IOU + 6] = 0x00000909;
e3260506	256
db302f8f	257	s->regs[DMAC_RAM] = 0x00000009;
e3260506	258
db302f8f PC	259	s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909;
	260	s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909;
	261	s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909;
	262	s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909;
	263	s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2]
	264	= s->regs[AFI3 + 2] = 0x00000909;
e3260506	265
db302f8f PC	266	s->regs[OCM + 0] = 0x01010101;
db302f8f PC	267	s->regs[OCM + 1] = s->regs[OCM + 2] = 0x09090909;
e3260506	268
db302f8f PC	269	s->regs[DEVCI_RAM] = 0x00000909;
db302f8f PC	270	s->regs[CSG_RAM] = 0x00000001;
e3260506	271
db302f8f PC	272	s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2]
	273	= s->regs[DDRIOB + 3] = 0x00000e00;
	274	s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6]
	275	= 0x00000e00;
	276	s->regs[DDRIOB + 12] = 0x00000021;
e3260506 PC	277	}
e3260506 PC	278
e3260506	279
db302f8f PC	280	static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
db302f8f PC	281	{
e3260506	282	switch (offset) {
db302f8f PC	283	case LOCK:
	284	case UNLOCK:
	285	case DDR_CAL_START:
	286	case DDR_REF_START:
	287	return !rnw; /* Write only */
	288	case LOCKSTA:
	289	case FPGA0_THR_STA:
	290	case FPGA1_THR_STA:
	291	case FPGA2_THR_STA:
	292	case FPGA3_THR_STA:
	293	case BOOT_MODE:
	294	case PSS_IDCODE:
	295	case DDR_CMD_STA:
	296	case DDR_DFI_STATUS:
	297	case PLL_STATUS:
	298	return rnw;/* read only */
	299	case SCL:
	300	case ARM_PLL_CTRL ... IO_PLL_CTRL:
	301	case ARM_PLL_CFG ... IO_PLL_CFG:
	302	case ARM_CLK_CTRL ... TOPSW_CLK_CTRL:
	303	case FPGA0_CLK_CTRL ... FPGA0_THR_CNT:
	304	case FPGA1_CLK_CTRL ... FPGA1_THR_CNT:
	305	case FPGA2_CLK_CTRL ... FPGA2_THR_CNT:
	306	case FPGA3_CLK_CTRL ... FPGA3_THR_CNT:
	307	case BANDGAP_TRIP:
	308	case PLL_PREDIVISOR:
	309	case CLK_621_TRUE:
	310	case PSS_RST_CTRL ... A9_CPU_RST_CTRL:
	311	case RS_AWDT_CTRL:
	312	case RST_REASON:
	313	case REBOOT_STATUS:
	314	case APU_CTRL:
	315	case WDT_CLK_SEL:
	316	case TZ_DMA_NS ... TZ_DMA_PERIPH_NS:
	317	case DDR_URGENT:
	318	case DDR_URGENT_SEL:
	319	case MIO ... MIO + MIO_LENGTH - 1:
	320	case MIO_LOOPBACK ... MIO_MST_TRI1:
	321	case SD0_WP_CD_SEL:
	322	case SD1_WP_CD_SEL:
	323	case LVL_SHFTR_EN:
	324	case OCM_CFG:
	325	case CPU_RAM:
	326	case IOU:
	327	case DMAC_RAM:
	328	case AFI0 ... AFI3 + AFI_LENGTH - 1:
	329	case OCM:
	330	case DEVCI_RAM:
	331	case CSG_RAM:
	332	case GPIOB_CTRL ... GPIOB_CFG_CMOS33:
	333	case GPIOB_CFG_HSTL:
	334	case GPIOB_DRVR_BIAS_CTRL:
	335	case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1:
	336	return true;
e3260506	337	default:
db302f8f	338	return false;
e3260506 PC	339	}
	340	}
	341
a8170e5e	342	static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
e3260506 PC	343	unsigned size)
e3260506 PC	344	{
db302f8f PC	345	ZynqSLCRState *s = opaque;
	346	offset /= 4;
	347	uint32_t ret = s->regs[offset];
e3260506	348
db302f8f PC	349	if (!zynq_slcr_check_offset(offset, true)) {
	350	qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to "
	351	" addr %" HWADDR_PRIx "\n", offset * 4);
	352	}
	353
	354	DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret);
e3260506 PC	355	return ret;
	356	}
	357
a8170e5e	358	static void zynq_slcr_write(void *opaque, hwaddr offset,
e3260506 PC	359	uint64_t val, unsigned size)
	360	{
	361	ZynqSLCRState s = (ZynqSLCRState )opaque;
db302f8f PC	362	offset /= 4;
	363
	364	DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val);
e3260506	365
db302f8f PC	366	if (!zynq_slcr_check_offset(offset, false)) {
	367	qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid write access to "
	368	"addr %" HWADDR_PRIx "\n", offset * 4);
	369	return;
	370	}
e3260506 PC	371
e3260506 PC	372	switch (offset) {
db302f8f PC	373	case SCL:
	374	s->regs[SCL] = val & 0x1;
	375	return;
	376	case LOCK:
e3260506 PC	377	if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
	378	DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
	379	(unsigned)val & 0xFFFF);
db302f8f	380	s->regs[LOCKSTA] = 1;
e3260506 PC	381	} else {
	382	DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
	383	(int)offset, (unsigned)val & 0xFFFF);
	384	}
	385	return;
db302f8f	386	case UNLOCK:
e3260506 PC	387	if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
	388	DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
	389	(unsigned)val & 0xFFFF);
db302f8f	390	s->regs[LOCKSTA] = 0;
e3260506 PC	391	} else {
	392	DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
	393	(int)offset, (unsigned)val & 0xFFFF);
	394	}
	395	return;
e3260506 PC	396	}
e3260506 PC	397
c209b053 PC	398	if (s->regs[LOCKSTA]) {
	399	qemu_log_mask(LOG_GUEST_ERROR,
	400	"SCLR registers are locked. Unlock them first\n");
db302f8f PC	401	return;
db302f8f PC	402	}
c209b053	403	s->regs[offset] = val;
db302f8f PC	404
	405	switch (offset) {
	406	case PSS_RST_CTRL:
	407	if (val & R_PSS_RST_CTRL_SOFT_RST) {
	408	qemu_system_reset_request();
	409	}
	410	break;
e3260506 PC	411	}
	412	}
	413
	414	static const MemoryRegionOps slcr_ops = {
	415	.read = zynq_slcr_read,
	416	.write = zynq_slcr_write,
	417	.endianness = DEVICE_NATIVE_ENDIAN,
	418	};
	419
15e3611e	420	static void zynq_slcr_init(Object *obj)
e3260506	421	{
15e3611e	422	ZynqSLCRState *s = ZYNQ_SLCR(obj);
e3260506	423
15e3611e	424	memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr",
db302f8f	425	ZYNQ_SLCR_MMIO_SIZE);
15e3611e	426	sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
e3260506 PC	427	}
	428
	429	static const VMStateDescription vmstate_zynq_slcr = {
	430	.name = "zynq_slcr",
db302f8f PC	431	.version_id = 2,
db302f8f PC	432	.minimum_version_id = 2,
8f1e884b	433	.fields = (VMStateField[]) {
db302f8f	434	VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
e3260506 PC	435	VMSTATE_END_OF_LIST()
	436	}
	437	};
	438
	439	static void zynq_slcr_class_init(ObjectClass klass, void data)
	440	{
	441	DeviceClass *dc = DEVICE_CLASS(klass);
e3260506	442
e3260506 PC	443	dc->vmsd = &vmstate_zynq_slcr;
	444	dc->reset = zynq_slcr_reset;
	445	}
	446
8c43a6f0	447	static const TypeInfo zynq_slcr_info = {
e3260506	448	.class_init = zynq_slcr_class_init,
a054e2c2	449	.name = TYPE_ZYNQ_SLCR,
e3260506 PC	450	.parent = TYPE_SYS_BUS_DEVICE,
e3260506 PC	451	.instance_size = sizeof(ZynqSLCRState),
15e3611e	452	.instance_init = zynq_slcr_init,
e3260506 PC	453	};
	454
	455	static void zynq_slcr_register_types(void)
	456	{
	457	type_register_static(&zynq_slcr_info);
	458	}
	459
	460	type_init(zynq_slcr_register_types)